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Core: improve DisplayControlRegHandler::Write32

This commit is contained in:
zilmar 2023-10-19 19:28:38 +10:30
parent d6a2ae80c1
commit 8f062975c3
2 changed files with 36 additions and 10 deletions
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44
Source/Project64-core/N64System/MemoryHandler/DisplayControlRegHandler.cpp
View File

@ -98,37 +98,47 @@ bool DisplayControlRegHandler::Write32(uint32_t Address, uint32_t Value, uint32_
DPC_CURRENT_REG = DPC_START_REG; DPC_CURRENT_REG = DPC_START_REG;
DPC_STATUS_REG &= ~DPC_STATUS_START_VALID; DPC_STATUS_REG &= ~DPC_STATUS_START_VALID;
} }
if (m_Plugins->Gfx()->ProcessRDPList) ProcessRDPList();
{
m_Plugins->Gfx()->ProcessRDPList();
}
break; break;
//case 0x04100008: g_Reg->DPC_CURRENT_REG = Value; break; //case 0x04100008: g_Reg->DPC_CURRENT_REG = Value; break;
case 0x0410000C: case 0x0410000C:
if ((MaskedValue & DPC_CLR_XBUS_DMEM_DMA) != 0) if ((MaskedValue & DPC_CLR_XBUS_DMEM_DMA) != 0 && (Value & DPC_SET_XBUS_DMEM_DMA) == 0)
{ {
DPC_STATUS_REG &= ~DPC_STATUS_XBUS_DMEM_DMA; DPC_STATUS_REG &= ~DPC_STATUS_XBUS_DMEM_DMA;
} }
if ((MaskedValue & DPC_SET_XBUS_DMEM_DMA) != 0) if ((MaskedValue & DPC_SET_XBUS_DMEM_DMA) != 0 && (Value & DPC_CLR_XBUS_DMEM_DMA) == 0)
{ {
DPC_STATUS_REG |= DPC_STATUS_XBUS_DMEM_DMA; DPC_STATUS_REG |= DPC_STATUS_XBUS_DMEM_DMA;
} }
if ((MaskedValue & DPC_CLR_FREEZE) != 0) if ((MaskedValue & DPC_CLR_FREEZE) != 0 && (Value & DPC_SET_FREEZE) == 0)
{ {
DPC_STATUS_REG &= ~DPC_STATUS_FREEZE; DPC_STATUS_REG &= ~DPC_STATUS_FREEZE;
ProcessRDPList();
} }
if ((MaskedValue & DPC_SET_FREEZE) != 0) if ((MaskedValue & DPC_SET_FREEZE) != 0 && (Value & DPC_CLR_FREEZE) == 0)
{ {
DPC_STATUS_REG |= DPC_STATUS_FREEZE; DPC_STATUS_REG |= DPC_STATUS_FREEZE;
} }
if ((MaskedValue & DPC_CLR_FLUSH) != 0) if ((MaskedValue & DPC_CLR_FLUSH) != 0 && (Value & DPC_SET_FLUSH) == 0)
{ {
DPC_STATUS_REG &= ~DPC_STATUS_FLUSH; DPC_STATUS_REG &= ~DPC_STATUS_FLUSH;
} }
if ((MaskedValue & DPC_SET_FLUSH) != 0) if ((MaskedValue & DPC_SET_FLUSH) != 0 && (Value & DPC_CLR_FLUSH) == 0)
{ {
DPC_STATUS_REG |= DPC_STATUS_FLUSH; DPC_STATUS_REG |= DPC_STATUS_FLUSH;
} }
if ((MaskedValue & DPC_CLR_TMEM_CTR) != 0)
{
DPC_STATUS_REG &= ~DPC_STATUS_TMEM_BUSY;
}
if ((MaskedValue & DPC_CLR_PIPE_CTR) != 0)
{
DPC_STATUS_REG &= ~DPC_STATUS_PIPE_BUSY;
}
if ((MaskedValue & DPC_CLR_CMD_CTR) != 0)
{
DPC_STATUS_REG &= ~DPC_STATUS_CMD_BUSY;
}
if ((MaskedValue & DPC_CLR_FREEZE) != 0) if ((MaskedValue & DPC_CLR_FREEZE) != 0)
{ {
if ((SP_STATUS_REG & SP_STATUS_HALT) == 0) if ((SP_STATUS_REG & SP_STATUS_HALT) == 0)
@ -148,3 +158,17 @@ bool DisplayControlRegHandler::Write32(uint32_t Address, uint32_t Value, uint32_
} }
return true; return true;
} }
void DisplayControlRegHandler::ProcessRDPList(void)
{
if ((DPC_STATUS_REG & DPC_STATUS_FREEZE) != 0)
{
return;
}
DPC_STATUS_REG |= DPC_STATUS_PIPE_BUSY | DPC_STATUS_START_GCLK;
if (DPC_END_REG > DPC_CURRENT_REG && m_Plugins->Gfx()->ProcessRDPList != nullptr)
{
m_Plugins->Gfx()->ProcessRDPList();
}
DPC_STATUS_REG |= DPC_STATUS_CBUF_READY;
}

2
Source/Project64-core/N64System/MemoryHandler/DisplayControlRegHandler.h
View File

@ -74,6 +74,8 @@ private:
DisplayControlRegHandler(const DisplayControlRegHandler &); DisplayControlRegHandler(const DisplayControlRegHandler &);
DisplayControlRegHandler & operator=(const DisplayControlRegHandler &); DisplayControlRegHandler & operator=(const DisplayControlRegHandler &);
void ProcessRDPList(void);
CN64System & m_System; CN64System & m_System;
CPlugins * m_Plugins; CPlugins * m_Plugins;
uint32_t & m_PC; uint32_t & m_PC;