Update RSP Registers.h
Change multi line comments into single line comments, fix some typos and capitalization errors, and fix abbreviations
This commit is contained in:
Derek "Turtle" Roe
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bfceec349e
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8efe8cc800
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@ -1,69 +1,69 @@
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#include "Types.h"
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#define SP_STATUS_HALT 0x001 /* Bit 0: halt */
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#define SP_STATUS_BROKE 0x002 /* Bit 1: broke */
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#define SP_STATUS_DMA_BUSY 0x004 /* Bit 2: dma busy */
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#define SP_STATUS_DMA_FULL 0x008 /* Bit 3: dma full */
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#define SP_STATUS_IO_FULL 0x010 /* Bit 4: io full */
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#define SP_STATUS_SSTEP 0x020 /* Bit 5: single step */
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#define SP_STATUS_INTR_BREAK 0x040 /* Bit 6: interrupt on break */
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#define SP_STATUS_SIG0 0x080 /* Bit 7: signal 0 set */
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#define SP_STATUS_SIG1 0x100 /* Bit 8: signal 1 set */
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#define SP_STATUS_SIG2 0x200 /* Bit 9: signal 2 set */
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#define SP_STATUS_SIG3 0x400 /* Bit 10: signal 3 set */
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#define SP_STATUS_SIG4 0x800 /* Bit 11: signal 4 set */
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#define SP_STATUS_SIG5 0x1000 /* Bit 12: signal 5 set */
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#define SP_STATUS_SIG6 0x2000 /* Bit 13: signal 6 set */
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#define SP_STATUS_SIG7 0x4000 /* Bit 14: signal 7 set */
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#define SP_STATUS_HALT 0x001 // Bit 0: halt
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#define SP_STATUS_BROKE 0x002 // Bit 1: broke
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#define SP_STATUS_DMA_BUSY 0x004 // Bit 2: DMA busy
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#define SP_STATUS_DMA_FULL 0x008 // Bit 3: DMA full
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#define SP_STATUS_IO_FULL 0x010 // Bit 4: IO full
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#define SP_STATUS_SSTEP 0x020 // Bit 5: single step
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#define SP_STATUS_INTR_BREAK 0x040 // Bit 6: interrupt on break
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#define SP_STATUS_SIG0 0x080 // Bit 7: signal 0 set
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#define SP_STATUS_SIG1 0x100 // Bit 8: signal 1 set
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#define SP_STATUS_SIG2 0x200 // Bit 9: signal 2 set
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#define SP_STATUS_SIG3 0x400 // Bit 10: signal 3 set
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#define SP_STATUS_SIG4 0x800 // Bit 11: signal 4 set
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#define SP_STATUS_SIG5 0x1000 // Bit 12: signal 5 set
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#define SP_STATUS_SIG6 0x2000 // Bit 13: signal 6 set
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#define SP_STATUS_SIG7 0x4000 // Bit 14: signal 7 set
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#define SP_CLR_HALT 0x00001 /* Bit 0: clear halt */
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#define SP_SET_HALT 0x00002 /* Bit 1: set halt */
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#define SP_CLR_BROKE 0x00004 /* Bit 2: clear broke */
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#define SP_CLR_INTR 0x00008 /* Bit 3: clear intr */
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#define SP_SET_INTR 0x00010 /* Bit 4: set intr */
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#define SP_CLR_SSTEP 0x00020 /* Bit 5: clear sstep */
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#define SP_SET_SSTEP 0x00040 /* Bit 6: set sstep */
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#define SP_CLR_INTR_BREAK 0x00080 /* Bit 7: clear intr on break */
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#define SP_SET_INTR_BREAK 0x00100 /* Bit 8: set intr on break */
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#define SP_CLR_SIG0 0x00200 /* Bit 9: clear signal 0 */
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#define SP_SET_SIG0 0x00400 /* Bit 10: set signal 0 */
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#define SP_CLR_SIG1 0x00800 /* Bit 11: clear signal 1 */
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#define SP_SET_SIG1 0x01000 /* Bit 12: set signal 1 */
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#define SP_CLR_SIG2 0x02000 /* Bit 13: clear signal 2 */
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#define SP_SET_SIG2 0x04000 /* Bit 14: set signal 2 */
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#define SP_CLR_SIG3 0x08000 /* Bit 15: clear signal 3 */
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#define SP_SET_SIG3 0x10000 /* Bit 16: set signal 3 */
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#define SP_CLR_SIG4 0x20000 /* Bit 17: clear signal 4 */
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#define SP_SET_SIG4 0x40000 /* Bit 18: set signal 4 */
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#define SP_CLR_SIG5 0x80000 /* Bit 19: clear signal 5 */
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#define SP_SET_SIG5 0x100000 /* Bit 20: set signal 5 */
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#define SP_CLR_SIG6 0x200000 /* Bit 21: clear signal 6 */
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#define SP_SET_SIG6 0x400000 /* Bit 22: set signal 6 */
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#define SP_CLR_SIG7 0x800000 /* Bit 23: clear signal 7 */
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#define SP_SET_SIG7 0x1000000 /* Bit 24: set signal 7 */
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#define SP_CLR_HALT 0x00001 // Bit 0: clear halt
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#define SP_SET_HALT 0x00002 // Bit 1: set halt
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#define SP_CLR_BROKE 0x00004 // Bit 2: clear broke
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#define SP_CLR_INTR 0x00008 // Bit 3: clear INTR
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#define SP_SET_INTR 0x00010 // Bit 4: set INTR
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#define SP_CLR_SSTEP 0x00020 // Bit 5: clear SSTEP
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#define SP_SET_SSTEP 0x00040 // Bit 6: set SSTEP
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#define SP_CLR_INTR_BREAK 0x00080 // Bit 7: clear INTR on break
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#define SP_SET_INTR_BREAK 0x00100 // Bit 8: set INTR on break
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#define SP_CLR_SIG0 0x00200 // Bit 9: clear signal 0
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#define SP_SET_SIG0 0x00400 // Bit 10: set signal 0
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#define SP_CLR_SIG1 0x00800 // Bit 11: clear signal 1
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#define SP_SET_SIG1 0x01000 // Bit 12: set signal 1
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#define SP_CLR_SIG2 0x02000 // Bit 13: clear signal 2
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#define SP_SET_SIG2 0x04000 // Bit 14: set signal 2
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#define SP_CLR_SIG3 0x08000 // Bit 15: clear signal 3
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#define SP_SET_SIG3 0x10000 // Bit 16: set signal 3
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#define SP_CLR_SIG4 0x20000 // Bit 17: clear signal 4
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#define SP_SET_SIG4 0x40000 // Bit 18: set signal 4
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#define SP_CLR_SIG5 0x80000 // Bit 19: clear signal 5
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#define SP_SET_SIG5 0x100000 // Bit 20: set signal 5
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#define SP_CLR_SIG6 0x200000 // Bit 21: clear signal 6
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#define SP_SET_SIG6 0x400000 // Bit 22: set signal 6
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#define SP_CLR_SIG7 0x800000 // Bit 23: clear signal 7
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#define SP_SET_SIG7 0x1000000 // Bit 24: set signal 7
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#define DPC_CLR_XBUS_DMEM_DMA 0x0001 /* Bit 0: clear xbus_dmem_dma */
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#define DPC_SET_XBUS_DMEM_DMA 0x0002 /* Bit 1: set xbus_dmem_dma */
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#define DPC_CLR_FREEZE 0x0004 /* Bit 2: clear freeze */
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#define DPC_SET_FREEZE 0x0008 /* Bit 3: set freeze */
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#define DPC_CLR_FLUSH 0x0010 /* Bit 4: clear flush */
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#define DPC_SET_FLUSH 0x0020 /* Bit 5: set flush */
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#define DPC_CLR_TMEM_CTR 0x0040 /* Bit 6: clear tmem ctr */
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#define DPC_CLR_PIPE_CTR 0x0080 /* Bit 7: clear pipe ctr */
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#define DPC_CLR_CMD_CTR 0x0100 /* Bit 8: clear cmd ctr */
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#define DPC_CLR_CLOCK_CTR 0x0200 /* Bit 9: clear clock ctr */
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#define DPC_CLR_XBUS_DMEM_DMA 0x0001 // Bit 0: clear xbus_dmem_dma
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#define DPC_SET_XBUS_DMEM_DMA 0x0002 // Bit 1: set xbus_dmem_dma
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#define DPC_CLR_FREEZE 0x0004 // Bit 2: clear freeze
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#define DPC_SET_FREEZE 0x0008 // Bit 3: set freeze
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#define DPC_CLR_FLUSH 0x0010 // Bit 4: clear flush
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#define DPC_SET_FLUSH 0x0020 // Bit 5: set flush
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#define DPC_CLR_TMEM_CTR 0x0040 // Bit 6: clear TMEM CTR
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#define DPC_CLR_PIPE_CTR 0x0080 // Bit 7: clear pipe CTR
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#define DPC_CLR_CMD_CTR 0x0100 // Bit 8: clear CMD CTR
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#define DPC_CLR_CLOCK_CTR 0x0200 // Bit 9: clear clock CTR
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#define DPC_STATUS_XBUS_DMEM_DMA 0x001 /* Bit 0: xbus_dmem_dma */
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#define DPC_STATUS_FREEZE 0x002 /* Bit 1: freeze */
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#define DPC_STATUS_FLUSH 0x004 /* Bit 2: flush */
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#define DPC_STATUS_START_GCLK 0x008 /* Bit 3: start gclk */
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#define DPC_STATUS_TMEM_BUSY 0x010 /* Bit 4: tmem busy */
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#define DPC_STATUS_PIPE_BUSY 0x020 /* Bit 5: pipe busy */
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#define DPC_STATUS_CMD_BUSY 0x040 /* Bit 6: cmd busy */
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#define DPC_STATUS_CBUF_READY 0x080 /* Bit 7: cbuf ready */
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#define DPC_STATUS_DMA_BUSY 0x100 /* Bit 8: dma busy */
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#define DPC_STATUS_END_VALID 0x200 /* Bit 9: end valid */
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#define DPC_STATUS_START_VALID 0x400 /* Bit 10: start valid */
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#define DPC_STATUS_XBUS_DMEM_DMA 0x001 // Bit 0: xbus_dmem_dma
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#define DPC_STATUS_FREEZE 0x002 // Bit 1: freeze
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#define DPC_STATUS_FLUSH 0x004 // Bit 2: flush
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#define DPC_STATUS_START_GCLK 0x008 // Bit 3: start GCLK
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#define DPC_STATUS_TMEM_BUSY 0x010 // Bit 4: TMEM busy
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#define DPC_STATUS_PIPE_BUSY 0x020 // Bit 5: pipe busy
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#define DPC_STATUS_CMD_BUSY 0x040 // Bit 6: CMD busy
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#define DPC_STATUS_CBUF_READY 0x080 // Bit 7: CBUF ready
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#define DPC_STATUS_DMA_BUSY 0x100 // Bit 8: DMA busy
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#define DPC_STATUS_END_VALID 0x200 // Bit 9: end valid
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#define DPC_STATUS_START_VALID 0x400 // Bit 10: start valid
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#define R4300i_SP_Intr 0x1
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@ -117,7 +117,7 @@ void Enter_RSP_Register_Window ( void );
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void InitilizeRSPRegisters (void);
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void UpdateRSPRegistersScreen ( void );
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/*** RSP Registers ***/
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// RSP registers
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extern UWORD32 RSP_GPR[32], RSP_Flags[4];
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extern UDWORD RSP_ACCUM[8];
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extern VECTOR RSP_Vect[32];
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