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Core: Move InitRegisters to register class

This commit is contained in:
zilmar 2023-09-14 12:01:16 +09:30
parent a5a4873e84
commit 8b14b6d7d1
4 changed files with 253 additions and 249 deletions
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274
Source/Project64-core/N64System/Mips/Register.cpp
View File

@ -2,6 +2,8 @@
#include <Project64-core/Logging.h> #include <Project64-core/Logging.h>
#include <Project64-core/N64System/Mips/Register.h> #include <Project64-core/N64System/Mips/Register.h>
#include <Project64-core/N64System/N64Disk.h>
#include <Project64-core/N64System/N64Rom.h>
#include <Project64-core/N64System/N64System.h> #include <Project64-core/N64System/N64System.h>
#include <Project64-core/N64System/SystemGlobals.h> #include <Project64-core/N64System/SystemGlobals.h>
#include <fenv.h> #include <fenv.h>
@ -263,7 +265,7 @@ DisplayControlReg::DisplayControlReg(uint32_t * _DisplayProcessor) :
{ {
} }
CRegisters::CRegisters(CN64System * System, CSystemEvents * SystemEvents) : CRegisters::CRegisters(CN64System & System, CSystemEvents & SystemEvents) :
CP0registers(m_CP0), CP0registers(m_CP0),
RDRAMRegistersReg(m_RDRAM_Registers), RDRAMRegistersReg(m_RDRAM_Registers),
MIPSInterfaceReg(m_Mips_Interface), MIPSInterfaceReg(m_Mips_Interface),
@ -276,12 +278,13 @@ CRegisters::CRegisters(CN64System * System, CSystemEvents * SystemEvents) :
SerialInterfaceReg(m_SerialInterface), SerialInterfaceReg(m_SerialInterface),
DiskInterfaceReg(m_DiskInterface), DiskInterfaceReg(m_DiskInterface),
m_System(System), m_System(System),
m_SystemEvents(SystemEvents) m_SystemEvents(SystemEvents),
m_SystemTimer(System.m_SystemTimer)
{ {
Reset(); Init();
} }
void CRegisters::Reset() void CRegisters::Init(void)
{ {
m_FirstInterupt = true; m_FirstInterupt = true;
@ -315,6 +318,215 @@ void CRegisters::Reset()
FixFpuLocations(); FixFpuLocations();
} }
void CRegisters::Reset(bool bPostPif, CMipsMemoryVM & MMU)
{
Init();
// COP0 registers
RANDOM_REGISTER = 0x1F;
COUNT_REGISTER = 0x5000;
MI_VERSION_REG = 0x02020102;
SP_STATUS_REG = 0x00000001;
CAUSE_REGISTER.Value = 0x0000005C;
CONTEXT_REGISTER.Value = 0x007FFFF0;
EPC_REGISTER = 0xFFFFFFFFFFFFFFFF;
BAD_VADDR_REGISTER = 0xFFFFFFFFFFFFFFFF;
ERROREPC_REGISTER = 0xFFFFFFFFFFFFFFFF;
PREVID_REGISTER = 0x00000B22;
CONFIG_REGISTER = 0x7006E463;
STATUS_REGISTER.Value = 0x34000000;
// N64DD registers
// Start N64DD in reset state and motor not spinning
ASIC_STATUS = DD_STATUS_RST_STATE | DD_STATUS_MTR_N_SPIN;
ASIC_ID_REG = 0x00030000;
if (g_DDRom && (g_DDRom->CicChipID() == CIC_NUS_8401 || (g_Disk && g_Disk->GetCountry() == Country_Unknown)))
ASIC_ID_REG = 0x00040000;
//REVISION_REGISTER = 0x00000511;
FixFpuLocations();
if (bPostPif)
{
m_PROGRAM_COUNTER = 0xA4000040;
m_GPR[0].DW = 0x0000000000000000;
m_GPR[6].DW = 0xFFFFFFFFA4001F0C;
m_GPR[7].DW = 0xFFFFFFFFA4001F08;
m_GPR[8].DW = 0x00000000000000C0;
m_GPR[9].DW = 0x0000000000000000;
m_GPR[10].DW = 0x0000000000000040;
m_GPR[11].DW = 0xFFFFFFFFA4000040;
m_GPR[16].DW = 0x0000000000000000;
m_GPR[17].DW = 0x0000000000000000;
m_GPR[18].DW = 0x0000000000000000;
m_GPR[19].DW = 0x0000000000000000;
m_GPR[21].DW = 0x0000000000000000;
m_GPR[26].DW = 0x0000000000000000;
m_GPR[27].DW = 0x0000000000000000;
m_GPR[28].DW = 0x0000000000000000;
m_GPR[29].DW = 0xFFFFFFFFA4001FF0;
m_GPR[30].DW = 0x0000000000000000;
if (g_Rom->IsPal())
{
switch (g_Rom->CicChipID())
{
case CIC_UNKNOWN:
case CIC_NUS_6102:
case CIC_MINI_IPL3:
m_GPR[5].DW = 0xFFFFFFFFC0F1D859;
m_GPR[14].DW = 0x000000002DE108EA;
m_GPR[24].DW = 0x0000000000000000;
break;
case CIC_NUS_6103:
m_GPR[5].DW = 0xFFFFFFFFD4646273;
m_GPR[14].DW = 0x000000001AF99984;
m_GPR[24].DW = 0x0000000000000000;
break;
case CIC_NUS_6105:
MMU.UpdateMemoryValue32(0xA4001004, 0xBDA807FC);
m_GPR[5].DW = 0xFFFFFFFFDECAAAD1;
m_GPR[14].DW = 0x000000000CF85C13;
m_GPR[24].DW = 0x0000000000000002;
break;
case CIC_NUS_6106:
m_GPR[5].DW = 0xFFFFFFFFB04DC903;
m_GPR[14].DW = 0x000000001AF99984;
m_GPR[24].DW = 0x0000000000000002;
break;
}
m_GPR[20].DW = 0x0000000000000000;
m_GPR[23].DW = 0x0000000000000006;
m_GPR[31].DW = 0xFFFFFFFFA4001554;
}
else
{
switch (g_Rom->CicChipID())
{
case CIC_UNKNOWN:
case CIC_NUS_6102:
case CIC_MINI_IPL3:
m_GPR[5].DW = 0xFFFFFFFFC95973D5;
m_GPR[14].DW = 0x000000002449A366;
break;
case CIC_NUS_6103:
m_GPR[5].DW = 0xFFFFFFFF95315A28;
m_GPR[14].DW = 0x000000005BACA1DF;
break;
case CIC_NUS_6105:
MMU.UpdateMemoryValue32(0xA4001004, 0x8DA807FC);
m_GPR[5].DW = 0x000000005493FB9A;
m_GPR[14].DW = 0xFFFFFFFFC2C20384;
case CIC_NUS_6106:
m_GPR[5].DW = 0xFFFFFFFFE067221F;
m_GPR[14].DW = 0x000000005CD2B70F;
break;
case CIC_NUS_6101:
case CIC_NUS_6104:
case CIC_NUS_5167:
case CIC_NUS_8303:
case CIC_NUS_DDUS:
case CIC_NUS_8401:
case CIC_NUS_5101:
default:
// No specific values
break;
}
m_GPR[20].DW = 0x0000000000000001;
m_GPR[23].DW = 0x0000000000000000;
m_GPR[24].DW = 0x0000000000000003;
m_GPR[31].DW = 0xFFFFFFFFA4001550;
}
switch (g_Rom->CicChipID())
{
case CIC_NUS_6101:
m_GPR[22].DW = 0x000000000000003F;
break;
case CIC_NUS_8303: // 64DD IPL CIC
case CIC_NUS_8401: // 64DD IPL tool CIC
case CIC_NUS_5167: // 64DD conversion CIC
m_GPR[22].DW = 0x00000000000000DD;
break;
case CIC_NUS_DDUS: // 64DD US IPL CIC
m_GPR[22].DW = 0x00000000000000DE;
break;
case CIC_NUS_5101: // Aleck64 CIC
m_GPR[22].DW = 0x00000000000000AC;
break;
case CIC_UNKNOWN:
case CIC_NUS_6102:
case CIC_MINI_IPL3:
m_GPR[1].DW = 0x0000000000000001;
m_GPR[2].DW = 0x000000000EBDA536;
m_GPR[3].DW = 0x000000000EBDA536;
m_GPR[4].DW = 0x000000000000A536;
m_GPR[12].DW = 0xFFFFFFFFED10D0B3;
m_GPR[13].DW = 0x000000001402A4CC;
m_GPR[15].DW = 0x000000003103E121;
m_GPR[22].DW = 0x000000000000003F;
m_GPR[25].DW = 0xFFFFFFFF9DEBB54F;
break;
case CIC_NUS_6103:
m_GPR[1].DW = 0x0000000000000001;
m_GPR[2].DW = 0x0000000049A5EE96;
m_GPR[3].DW = 0x0000000049A5EE96;
m_GPR[4].DW = 0x000000000000EE96;
m_GPR[12].DW = 0xFFFFFFFFCE9DFBF7;
m_GPR[13].DW = 0xFFFFFFFFCE9DFBF7;
m_GPR[15].DW = 0x0000000018B63D28;
m_GPR[22].DW = 0x0000000000000078;
m_GPR[25].DW = 0xFFFFFFFF825B21C9;
break;
case CIC_NUS_6105:
MMU.UpdateMemoryValue32(0xA4001000, 0x3C0DBFC0);
MMU.UpdateMemoryValue32(0xA4001008, 0x25AD07C0);
MMU.UpdateMemoryValue32(0xA400100C, 0x31080080);
MMU.UpdateMemoryValue32(0xA4001010, 0x5500FFFC);
MMU.UpdateMemoryValue32(0xA4001014, 0x3C0DBFC0);
MMU.UpdateMemoryValue32(0xA4001018, 0x8DA80024);
MMU.UpdateMemoryValue32(0xA400101C, 0x3C0BB000);
m_GPR[1].DW = 0x0000000000000000;
m_GPR[2].DW = 0xFFFFFFFFF58B0FBF;
m_GPR[3].DW = 0xFFFFFFFFF58B0FBF;
m_GPR[4].DW = 0x0000000000000FBF;
m_GPR[12].DW = 0xFFFFFFFF9651F81E;
m_GPR[13].DW = 0x000000002D42AAC5;
m_GPR[15].DW = 0x0000000056584D60;
m_GPR[22].DW = 0x0000000000000091;
m_GPR[25].DW = 0xFFFFFFFFCDCE565F;
break;
case CIC_NUS_6106:
m_GPR[1].DW = 0x0000000000000000;
m_GPR[2].DW = 0xFFFFFFFFA95930A4;
m_GPR[3].DW = 0xFFFFFFFFA95930A4;
m_GPR[4].DW = 0x00000000000030A4;
m_GPR[12].DW = 0xFFFFFFFFBCB59510;
m_GPR[13].DW = 0xFFFFFFFFBCB59510;
m_GPR[15].DW = 0x000000007A3C07F4;
m_GPR[22].DW = 0x0000000000000085;
m_GPR[25].DW = 0x00000000465E3F72;
break;
}
}
else
{
m_PROGRAM_COUNTER = 0xBFC00000;
/* PIF_Ram[36] = 0x00; PIF_Ram[39] = 0x3F; // Common PIF RAM start values
switch (g_Rom->CicChipID()) {
case CIC_NUS_6101: PIF_Ram[37] = 0x06; PIF_Ram[38] = 0x3F; break;
case CIC_UNKNOWN:
case CIC_NUS_6102: PIF_Ram[37] = 0x02; PIF_Ram[38] = 0x3F; break;
case CIC_NUS_6103: PIF_Ram[37] = 0x02; PIF_Ram[38] = 0x78; break;
case CIC_NUS_6105: PIF_Ram[37] = 0x02; PIF_Ram[38] = 0x91; break;
case CIC_NUS_6106: PIF_Ram[37] = 0x02; PIF_Ram[38] = 0x85; break;
}*/
}
}
void CRegisters::SetAsCurrentSystem() void CRegisters::SetAsCurrentSystem()
{ {
_PROGRAM_COUNTER = &m_PROGRAM_COUNTER; _PROGRAM_COUNTER = &m_PROGRAM_COUNTER;
@ -338,7 +550,7 @@ uint64_t CRegisters::Cop0_MF(COP0Reg Reg)
if (Reg == COP0Reg_Count || Reg == COP0Reg_Wired || Reg == COP0Reg_Random) if (Reg == COP0Reg_Count || Reg == COP0Reg_Wired || Reg == COP0Reg_Random)
{ {
g_SystemTimer->UpdateTimers(); m_SystemTimer.UpdateTimers();
} }
else if (Reg == COP0Reg_7 || Reg == COP0Reg_21 || Reg == COP0Reg_22 || Reg == COP0Reg_23 || Reg == COP0Reg_24 || Reg == COP0Reg_25 || Reg == COP0Reg_31) else if (Reg == COP0Reg_7 || Reg == COP0Reg_21 || Reg == COP0Reg_22 || Reg == COP0Reg_23 || Reg == COP0Reg_24 || Reg == COP0Reg_25 || Reg == COP0Reg_31)
{ {
@ -388,7 +600,7 @@ void CRegisters::Cop0_MT(COP0Reg Reg, uint64_t Value)
m_CP0[Reg] = Value & 0x1FFE000; m_CP0[Reg] = Value & 0x1FFE000;
break; break;
case COP0Reg_Wired: case COP0Reg_Wired:
g_SystemTimer->UpdateTimers(); m_SystemTimer.UpdateTimers();
m_CP0[Reg] = Value & 0x3F; m_CP0[Reg] = Value & 0x3F;
break; break;
case COP0Reg_7: case COP0Reg_7:
@ -396,18 +608,18 @@ void CRegisters::Cop0_MT(COP0Reg Reg, uint64_t Value)
// Ignore - Read only // Ignore - Read only
break; break;
case COP0Reg_Count: case COP0Reg_Count:
g_SystemTimer->UpdateTimers(); m_SystemTimer.UpdateTimers();
m_CP0[Reg] = Value; m_CP0[Reg] = Value;
g_SystemTimer->UpdateCompareTimer(); m_SystemTimer.UpdateCompareTimer();
break; break;
case COP0Reg_EntryHi: case COP0Reg_EntryHi:
m_CP0[Reg] = Value & 0xC00000FFFFFFE0FF; m_CP0[Reg] = Value & 0xC00000FFFFFFE0FF;
break; break;
case COP0Reg_Compare: case COP0Reg_Compare:
g_SystemTimer->UpdateTimers(); m_SystemTimer.UpdateTimers();
m_CP0[Reg] = Value; m_CP0[Reg] = Value;
CAUSE_REGISTER.PendingInterrupts &= ~CAUSE_IP7; CAUSE_REGISTER.PendingInterrupts &= ~CAUSE_IP7;
g_SystemTimer->UpdateCompareTimer(); m_SystemTimer.UpdateCompareTimer();
break; break;
case COP0Reg_Status: case COP0Reg_Status:
{ {
@ -473,7 +685,7 @@ void CRegisters::Cop1_CT(uint32_t Reg, uint32_t Value)
((StatusReg.Cause.InvalidOperation & StatusReg.Enable.InvalidOperation) != 0) || ((StatusReg.Cause.InvalidOperation & StatusReg.Enable.InvalidOperation) != 0) ||
(StatusReg.Cause.UnimplementedOperation != 0)) (StatusReg.Cause.UnimplementedOperation != 0))
{ {
g_Reg->TriggerException(EXC_FPE); TriggerException(EXC_FPE);
} }
} }
} }
@ -490,15 +702,15 @@ void CRegisters::Cop2_MT(uint32_t /*Reg*/, uint64_t Value)
void CRegisters::CheckInterrupts() void CRegisters::CheckInterrupts()
{ {
uint32_t mi_intr_reg = MI_INTR_REG; uint32_t MI_INTR_REG_Value = MI_INTR_REG;
if (!m_System->bFixedAudio() && CpuType() != CPU_SyncCores) if (!m_System.bFixedAudio() && CpuType() != CPU_SyncCores)
{ {
mi_intr_reg &= ~MI_INTR_AI; MI_INTR_REG_Value &= ~MI_INTR_AI;
mi_intr_reg |= (m_AudioIntrReg & MI_INTR_AI); MI_INTR_REG_Value |= (m_AudioIntrReg & MI_INTR_AI);
} }
mi_intr_reg |= (m_RspIntrReg & MI_INTR_SP); MI_INTR_REG_Value |= (m_RspIntrReg & MI_INTR_SP);
mi_intr_reg |= (m_GfxIntrReg & MI_INTR_DP); MI_INTR_REG_Value |= (m_GfxIntrReg & MI_INTR_DP);
if ((MI_INTR_MASK_REG & mi_intr_reg) != 0) if ((MI_INTR_MASK_REG & MI_INTR_REG_Value) != 0)
{ {
CAUSE_REGISTER.PendingInterrupts |= CAUSE_IP2; CAUSE_REGISTER.PendingInterrupts |= CAUSE_IP2;
} }
@ -506,7 +718,7 @@ void CRegisters::CheckInterrupts()
{ {
CAUSE_REGISTER.PendingInterrupts &= ~CAUSE_IP2; CAUSE_REGISTER.PendingInterrupts &= ~CAUSE_IP2;
} }
MI_INTR_REG = mi_intr_reg; MI_INTR_REG = MI_INTR_REG_Value;
COP0Status STATUS_REGISTER_Value = STATUS_REGISTER; COP0Status STATUS_REGISTER_Value = STATUS_REGISTER;
if (STATUS_REGISTER_Value.InterruptEnable == 0 || STATUS_REGISTER_Value.ExceptionLevel != 0 || STATUS_REGISTER_Value.ErrorLevel != 0) if (STATUS_REGISTER_Value.InterruptEnable == 0 || STATUS_REGISTER_Value.ExceptionLevel != 0 || STATUS_REGISTER_Value.ErrorLevel != 0)
@ -524,7 +736,7 @@ void CRegisters::CheckInterrupts()
g_Recompiler->ClearRecompCode_Virt(0x80000000, 0x200, CRecompiler::Remove_InitialCode); g_Recompiler->ClearRecompCode_Virt(0x80000000, 0x200, CRecompiler::Remove_InitialCode);
} }
} }
m_SystemEvents->QueueEvent(SysEvent_ExecuteInterrupt); m_SystemEvents.QueueEvent(SysEvent_ExecuteInterrupt);
} }
} }
@ -549,7 +761,7 @@ void CRegisters::DoAddressError(uint64_t BadVaddr, bool FromRead)
XCONTEXT_REGISTER.BadVPN2 = BadVaddr >> 13; XCONTEXT_REGISTER.BadVPN2 = BadVaddr >> 13;
XCONTEXT_REGISTER.R = BadVaddr >> 61; XCONTEXT_REGISTER.R = BadVaddr >> 61;
if (m_System->m_PipelineStage == PIPELINE_STAGE_JUMP) if (m_System.m_PipelineStage == PIPELINE_STAGE_JUMP)
{ {
CAUSE_REGISTER.BranchDelay = 1; CAUSE_REGISTER.BranchDelay = 1;
EPC_REGISTER = (int32_t)(m_PROGRAM_COUNTER - 4); EPC_REGISTER = (int32_t)(m_PROGRAM_COUNTER - 4);
@ -560,8 +772,8 @@ void CRegisters::DoAddressError(uint64_t BadVaddr, bool FromRead)
EPC_REGISTER = (int32_t)m_PROGRAM_COUNTER; EPC_REGISTER = (int32_t)m_PROGRAM_COUNTER;
} }
STATUS_REGISTER.ExceptionLevel = 1; STATUS_REGISTER.ExceptionLevel = 1;
m_System->m_JumpToLocation = 0x80000180; m_System.m_JumpToLocation = 0x80000180;
m_System->m_PipelineStage = PIPELINE_STAGE_JUMP; m_System.m_PipelineStage = PIPELINE_STAGE_JUMP;
} }
void CRegisters::FixFpuLocations() void CRegisters::FixFpuLocations()
@ -615,11 +827,11 @@ void CRegisters::DoTLBReadMiss(bool DelaySlot, uint64_t BadVaddr)
} }
if (g_TLB->AddressDefined((uint32_t)BadVaddr)) if (g_TLB->AddressDefined((uint32_t)BadVaddr))
{ {
m_System->m_JumpToLocation = 0x80000180; m_System.m_JumpToLocation = 0x80000180;
} }
else else
{ {
m_System->m_JumpToLocation = 0x80000000; m_System.m_JumpToLocation = 0x80000000;
} }
STATUS_REGISTER.ExceptionLevel = 1; STATUS_REGISTER.ExceptionLevel = 1;
} }
@ -629,9 +841,9 @@ void CRegisters::DoTLBReadMiss(bool DelaySlot, uint64_t BadVaddr)
{ {
g_Notify->DisplayError(stdstr_f("TLBMiss - EXL set\nBadVaddr = %X\nAddress defined: %s", (uint32_t)BadVaddr, g_TLB->AddressDefined((uint32_t)BadVaddr) ? "true" : "false").c_str()); g_Notify->DisplayError(stdstr_f("TLBMiss - EXL set\nBadVaddr = %X\nAddress defined: %s", (uint32_t)BadVaddr, g_TLB->AddressDefined((uint32_t)BadVaddr) ? "true" : "false").c_str());
} }
m_System->m_JumpToLocation = 0x80000180; m_System.m_JumpToLocation = 0x80000180;
} }
m_System->m_PipelineStage = PIPELINE_STAGE_JUMP; m_System.m_PipelineStage = PIPELINE_STAGE_JUMP;
} }
void CRegisters::DoTLBWriteMiss(bool DelaySlot, uint64_t BadVaddr) void CRegisters::DoTLBWriteMiss(bool DelaySlot, uint64_t BadVaddr)
@ -689,9 +901,9 @@ void CRegisters::TriggerException(uint32_t ExceptionCode, uint32_t Coprocessor)
CAUSE_REGISTER.ExceptionCode = ExceptionCode; CAUSE_REGISTER.ExceptionCode = ExceptionCode;
CAUSE_REGISTER.CoprocessorUnitNumber = Coprocessor; CAUSE_REGISTER.CoprocessorUnitNumber = Coprocessor;
CAUSE_REGISTER.BranchDelay = m_System->m_PipelineStage == PIPELINE_STAGE_JUMP; CAUSE_REGISTER.BranchDelay = m_System.m_PipelineStage == PIPELINE_STAGE_JUMP;
EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER - (CAUSE_REGISTER.BranchDelay ? 4 : 0)); EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER - (CAUSE_REGISTER.BranchDelay ? 4 : 0));
STATUS_REGISTER.ExceptionLevel = 1; STATUS_REGISTER.ExceptionLevel = 1;
m_System->m_PipelineStage = PIPELINE_STAGE_JUMP; m_System.m_PipelineStage = PIPELINE_STAGE_JUMP;
m_System->m_JumpToLocation = 0x80000180; m_System.m_JumpToLocation = 0x80000180;
} }

10
Source/Project64-core/N64System/Mips/Register.h
View File

@ -447,15 +447,16 @@ public:
COP0Reg_ErrEPC = 30, COP0Reg_ErrEPC = 30,
COP0Reg_31 = 31, COP0Reg_31 = 31,
}; };
CRegisters(CN64System * System, CSystemEvents * SystemEvents); CRegisters(CN64System & System, CSystemEvents & SystemEvents);
void Init(void);
void CheckInterrupts(); void CheckInterrupts();
void DoAddressError(uint64_t BadVaddr, bool FromRead); void DoAddressError(uint64_t BadVaddr, bool FromRead);
bool DoIntrException(); bool DoIntrException();
void DoTLBReadMiss(bool DelaySlot, uint64_t BadVaddr); void DoTLBReadMiss(bool DelaySlot, uint64_t BadVaddr);
void DoTLBWriteMiss(bool DelaySlot, uint64_t BadVaddr); void DoTLBWriteMiss(bool DelaySlot, uint64_t BadVaddr);
void FixFpuLocations(); void FixFpuLocations();
void Reset(); void Reset(bool bPostPif, CMipsMemoryVM & MMU);
void SetAsCurrentSystem(); void SetAsCurrentSystem();
void TriggerException(uint32_t ExceptionCode, uint32_t Coprocessor = 0); void TriggerException(uint32_t ExceptionCode, uint32_t Coprocessor = 0);
@ -502,6 +503,7 @@ private:
CRegisters & operator=(const CRegisters &); CRegisters & operator=(const CRegisters &);
bool m_FirstInterupt; bool m_FirstInterupt;
CN64System * m_System; CN64System & m_System;
CSystemEvents * m_SystemEvents; CSystemEvents & m_SystemEvents;
CSystemTimer & m_SystemTimer;
}; };

215
Source/Project64-core/N64System/N64System.cpp
View File

@ -32,8 +32,8 @@ CN64System::CN64System(CPlugins * Plugins, uint32_t randomizer_seed, bool SavesR
m_SyncPlugins(nullptr), m_SyncPlugins(nullptr),
m_MMU_VM(*this, SavesReadOnly), m_MMU_VM(*this, SavesReadOnly),
//m_Cheats(m_MMU_VM), //m_Cheats(m_MMU_VM),
m_Reg(*this, *this),
m_TLB(this), m_TLB(this),
m_Reg(this, this),
m_Recomp(nullptr), m_Recomp(nullptr),
m_InReset(false), m_InReset(false),
m_NextTimer(0), m_NextTimer(0),
@ -927,7 +927,7 @@ void CN64System::Reset(bool bInitReg, bool ClearMenory)
{ {
bool PostPif = true; bool PostPif = true;
InitRegisters(PostPif, m_MMU_VM); m_Reg.Reset(PostPif, m_MMU_VM);
if (PostPif) if (PostPif)
{ {
memcpy((m_MMU_VM.Dmem() + 0x40), (g_Rom->GetRomAddress() + 0x040), 0xFBC); memcpy((m_MMU_VM.Dmem() + 0x40), (g_Rom->GetRomAddress() + 0x040), 0xFBC);
@ -935,7 +935,7 @@ void CN64System::Reset(bool bInitReg, bool ClearMenory)
} }
else else
{ {
m_Reg.Reset(); m_Reg.Init();
} }
m_SystemTimer.Reset(); m_SystemTimer.Reset();
@ -1021,215 +1021,6 @@ bool CN64System::SetActiveSystem(bool bActive)
return bRes; return bRes;
} }
void CN64System::InitRegisters(bool bPostPif, CMipsMemoryVM & MMU)
{
m_Reg.Reset();
// COP0 registers
m_Reg.RANDOM_REGISTER = 0x1F;
m_Reg.COUNT_REGISTER = 0x5000;
m_Reg.MI_VERSION_REG = 0x02020102;
m_Reg.SP_STATUS_REG = 0x00000001;
m_Reg.CAUSE_REGISTER.Value = 0x0000005C;
m_Reg.CONTEXT_REGISTER.Value = 0x007FFFF0;
m_Reg.EPC_REGISTER = 0xFFFFFFFFFFFFFFFF;
m_Reg.BAD_VADDR_REGISTER = 0xFFFFFFFFFFFFFFFF;
m_Reg.ERROREPC_REGISTER = 0xFFFFFFFFFFFFFFFF;
m_Reg.PREVID_REGISTER = 0x00000B22;
m_Reg.CONFIG_REGISTER = 0x7006E463;
m_Reg.STATUS_REGISTER.Value = 0x34000000;
// N64DD registers
// Start N64DD in reset state and motor not spinning
m_Reg.ASIC_STATUS = DD_STATUS_RST_STATE | DD_STATUS_MTR_N_SPIN;
m_Reg.ASIC_ID_REG = 0x00030000;
if (g_DDRom && (g_DDRom->CicChipID() == CIC_NUS_8401 || (g_Disk && g_Disk->GetCountry() == Country_Unknown)))
m_Reg.ASIC_ID_REG = 0x00040000;
//m_Reg.REVISION_REGISTER = 0x00000511;
m_Reg.FixFpuLocations();
if (bPostPif)
{
m_Reg.m_PROGRAM_COUNTER = 0xA4000040;
m_Reg.m_GPR[0].DW = 0x0000000000000000;
m_Reg.m_GPR[6].DW = 0xFFFFFFFFA4001F0C;
m_Reg.m_GPR[7].DW = 0xFFFFFFFFA4001F08;
m_Reg.m_GPR[8].DW = 0x00000000000000C0;
m_Reg.m_GPR[9].DW = 0x0000000000000000;
m_Reg.m_GPR[10].DW = 0x0000000000000040;
m_Reg.m_GPR[11].DW = 0xFFFFFFFFA4000040;
m_Reg.m_GPR[16].DW = 0x0000000000000000;
m_Reg.m_GPR[17].DW = 0x0000000000000000;
m_Reg.m_GPR[18].DW = 0x0000000000000000;
m_Reg.m_GPR[19].DW = 0x0000000000000000;
m_Reg.m_GPR[21].DW = 0x0000000000000000;
m_Reg.m_GPR[26].DW = 0x0000000000000000;
m_Reg.m_GPR[27].DW = 0x0000000000000000;
m_Reg.m_GPR[28].DW = 0x0000000000000000;
m_Reg.m_GPR[29].DW = 0xFFFFFFFFA4001FF0;
m_Reg.m_GPR[30].DW = 0x0000000000000000;
if (g_Rom->IsPal())
{
switch (g_Rom->CicChipID())
{
case CIC_UNKNOWN:
case CIC_NUS_6102:
case CIC_MINI_IPL3:
m_Reg.m_GPR[5].DW = 0xFFFFFFFFC0F1D859;
m_Reg.m_GPR[14].DW = 0x000000002DE108EA;
m_Reg.m_GPR[24].DW = 0x0000000000000000;
break;
case CIC_NUS_6103:
m_Reg.m_GPR[5].DW = 0xFFFFFFFFD4646273;
m_Reg.m_GPR[14].DW = 0x000000001AF99984;
m_Reg.m_GPR[24].DW = 0x0000000000000000;
break;
case CIC_NUS_6105:
MMU.UpdateMemoryValue32(0xA4001004, 0xBDA807FC);
m_Reg.m_GPR[5].DW = 0xFFFFFFFFDECAAAD1;
m_Reg.m_GPR[14].DW = 0x000000000CF85C13;
m_Reg.m_GPR[24].DW = 0x0000000000000002;
break;
case CIC_NUS_6106:
m_Reg.m_GPR[5].DW = 0xFFFFFFFFB04DC903;
m_Reg.m_GPR[14].DW = 0x000000001AF99984;
m_Reg.m_GPR[24].DW = 0x0000000000000002;
break;
}
m_Reg.m_GPR[20].DW = 0x0000000000000000;
m_Reg.m_GPR[23].DW = 0x0000000000000006;
m_Reg.m_GPR[31].DW = 0xFFFFFFFFA4001554;
}
else
{
switch (g_Rom->CicChipID())
{
case CIC_UNKNOWN:
case CIC_NUS_6102:
case CIC_MINI_IPL3:
m_Reg.m_GPR[5].DW = 0xFFFFFFFFC95973D5;
m_Reg.m_GPR[14].DW = 0x000000002449A366;
break;
case CIC_NUS_6103:
m_Reg.m_GPR[5].DW = 0xFFFFFFFF95315A28;
m_Reg.m_GPR[14].DW = 0x000000005BACA1DF;
break;
case CIC_NUS_6105:
MMU.UpdateMemoryValue32(0xA4001004, 0x8DA807FC);
m_Reg.m_GPR[5].DW = 0x000000005493FB9A;
m_Reg.m_GPR[14].DW = 0xFFFFFFFFC2C20384;
case CIC_NUS_6106:
m_Reg.m_GPR[5].DW = 0xFFFFFFFFE067221F;
m_Reg.m_GPR[14].DW = 0x000000005CD2B70F;
break;
case CIC_NUS_6101:
case CIC_NUS_6104:
case CIC_NUS_5167:
case CIC_NUS_8303:
case CIC_NUS_DDUS:
case CIC_NUS_8401:
case CIC_NUS_5101:
default:
// No specific values
break;
}
m_Reg.m_GPR[20].DW = 0x0000000000000001;
m_Reg.m_GPR[23].DW = 0x0000000000000000;
m_Reg.m_GPR[24].DW = 0x0000000000000003;
m_Reg.m_GPR[31].DW = 0xFFFFFFFFA4001550;
}
switch (g_Rom->CicChipID())
{
case CIC_NUS_6101:
m_Reg.m_GPR[22].DW = 0x000000000000003F;
break;
case CIC_NUS_8303: // 64DD IPL CIC
case CIC_NUS_8401: // 64DD IPL tool CIC
case CIC_NUS_5167: // 64DD conversion CIC
m_Reg.m_GPR[22].DW = 0x00000000000000DD;
break;
case CIC_NUS_DDUS: // 64DD US IPL CIC
m_Reg.m_GPR[22].DW = 0x00000000000000DE;
break;
case CIC_NUS_5101: // Aleck64 CIC
m_Reg.m_GPR[22].DW = 0x00000000000000AC;
break;
case CIC_UNKNOWN:
case CIC_NUS_6102:
case CIC_MINI_IPL3:
m_Reg.m_GPR[1].DW = 0x0000000000000001;
m_Reg.m_GPR[2].DW = 0x000000000EBDA536;
m_Reg.m_GPR[3].DW = 0x000000000EBDA536;
m_Reg.m_GPR[4].DW = 0x000000000000A536;
m_Reg.m_GPR[12].DW = 0xFFFFFFFFED10D0B3;
m_Reg.m_GPR[13].DW = 0x000000001402A4CC;
m_Reg.m_GPR[15].DW = 0x000000003103E121;
m_Reg.m_GPR[22].DW = 0x000000000000003F;
m_Reg.m_GPR[25].DW = 0xFFFFFFFF9DEBB54F;
break;
case CIC_NUS_6103:
m_Reg.m_GPR[1].DW = 0x0000000000000001;
m_Reg.m_GPR[2].DW = 0x0000000049A5EE96;
m_Reg.m_GPR[3].DW = 0x0000000049A5EE96;
m_Reg.m_GPR[4].DW = 0x000000000000EE96;
m_Reg.m_GPR[12].DW = 0xFFFFFFFFCE9DFBF7;
m_Reg.m_GPR[13].DW = 0xFFFFFFFFCE9DFBF7;
m_Reg.m_GPR[15].DW = 0x0000000018B63D28;
m_Reg.m_GPR[22].DW = 0x0000000000000078;
m_Reg.m_GPR[25].DW = 0xFFFFFFFF825B21C9;
break;
case CIC_NUS_6105:
MMU.UpdateMemoryValue32(0xA4001000, 0x3C0DBFC0);
MMU.UpdateMemoryValue32(0xA4001008, 0x25AD07C0);
MMU.UpdateMemoryValue32(0xA400100C, 0x31080080);
MMU.UpdateMemoryValue32(0xA4001010, 0x5500FFFC);
MMU.UpdateMemoryValue32(0xA4001014, 0x3C0DBFC0);
MMU.UpdateMemoryValue32(0xA4001018, 0x8DA80024);
MMU.UpdateMemoryValue32(0xA400101C, 0x3C0BB000);
m_Reg.m_GPR[1].DW = 0x0000000000000000;
m_Reg.m_GPR[2].DW = 0xFFFFFFFFF58B0FBF;
m_Reg.m_GPR[3].DW = 0xFFFFFFFFF58B0FBF;
m_Reg.m_GPR[4].DW = 0x0000000000000FBF;
m_Reg.m_GPR[12].DW = 0xFFFFFFFF9651F81E;
m_Reg.m_GPR[13].DW = 0x000000002D42AAC5;
m_Reg.m_GPR[15].DW = 0x0000000056584D60;
m_Reg.m_GPR[22].DW = 0x0000000000000091;
m_Reg.m_GPR[25].DW = 0xFFFFFFFFCDCE565F;
break;
case CIC_NUS_6106:
m_Reg.m_GPR[1].DW = 0x0000000000000000;
m_Reg.m_GPR[2].DW = 0xFFFFFFFFA95930A4;
m_Reg.m_GPR[3].DW = 0xFFFFFFFFA95930A4;
m_Reg.m_GPR[4].DW = 0x00000000000030A4;
m_Reg.m_GPR[12].DW = 0xFFFFFFFFBCB59510;
m_Reg.m_GPR[13].DW = 0xFFFFFFFFBCB59510;
m_Reg.m_GPR[15].DW = 0x000000007A3C07F4;
m_Reg.m_GPR[22].DW = 0x0000000000000085;
m_Reg.m_GPR[25].DW = 0x00000000465E3F72;
break;
}
}
else
{
m_Reg.m_PROGRAM_COUNTER = 0xBFC00000;
/* PIF_Ram[36] = 0x00; PIF_Ram[39] = 0x3F; // Common PIF RAM start values
switch (g_Rom->CicChipID()) {
case CIC_NUS_6101: PIF_Ram[37] = 0x06; PIF_Ram[38] = 0x3F; break;
case CIC_UNKNOWN:
case CIC_NUS_6102: PIF_Ram[37] = 0x02; PIF_Ram[38] = 0x3F; break;
case CIC_NUS_6103: PIF_Ram[37] = 0x02; PIF_Ram[38] = 0x78; break;
case CIC_NUS_6105: PIF_Ram[37] = 0x02; PIF_Ram[38] = 0x91; break;
case CIC_NUS_6106: PIF_Ram[37] = 0x02; PIF_Ram[38] = 0x85; break;
}*/
}
}
void CN64System::ExecuteCPU() void CN64System::ExecuteCPU()
{ {
WriteTrace(TraceN64System, TraceDebug, "Start"); WriteTrace(TraceN64System, TraceDebug, "Start");

3
Source/Project64-core/N64System/N64System.h
View File

@ -162,7 +162,6 @@ private:
void DumpSyncErrors(CN64System * SecondCPU); void DumpSyncErrors(CN64System * SecondCPU);
void StartEmulation2(bool NewThread); void StartEmulation2(bool NewThread);
bool SetActiveSystem(bool bActive = true); bool SetActiveSystem(bool bActive = true);
void InitRegisters(bool bPostPif, CMipsMemoryVM & MMU);
void DisplayRSPListCount(); void DisplayRSPListCount();
void NotifyCallback(CN64SystemCB Type); void NotifyCallback(CN64SystemCB Type);
void DelayedJump(uint32_t JumpLocation); void DelayedJump(uint32_t JumpLocation);
@ -186,8 +185,8 @@ private:
CPlugins * m_SyncPlugins; CPlugins * m_SyncPlugins;
CN64System * m_SyncCPU; CN64System * m_SyncCPU;
CMipsMemoryVM m_MMU_VM; CMipsMemoryVM m_MMU_VM;
CTLB m_TLB;
CRegisters m_Reg; CRegisters m_Reg;
CTLB m_TLB;
CMempak m_Mempak; CMempak m_Mempak;
CFramePerSecond m_FPS; CFramePerSecond m_FPS;
CProfiling m_CPU_Usage; // Used to track the CPU usage CProfiling m_CPU_Usage; // Used to track the CPU usage