From 87dc96752d62193ced1ccff48548287b6e2651f3 Mon Sep 17 00:00:00 2001
From: LegendOfDragoon <the_f1u@yahoo.com>
Date: Fri, 9 Oct 2015 11:39:46 -0700
Subject: [PATCH] Implement Recompiler version of LBV

---
 Source/RSP/Recompiler Ops.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/Source/RSP/Recompiler Ops.c b/Source/RSP/Recompiler Ops.c
index c49fa6449..2bf2fe1f2 100644
--- a/Source/RSP/Recompiler Ops.c	
+++ b/Source/RSP/Recompiler Ops.c	
@@ -98,6 +98,7 @@ DWORD BranchCompare = 0;
 #	define CompileVnand
 #endif
 #ifdef RSP_VectorLoads
+#	define CompileLbv
 #	define CompileSqv		/* Verified 12/17/2000 - Jabo */
 #	define CompileSdv		/* Verified 12/17/2000 - Jabo */
 #	define CompileSsv		/* Verified 12/17/2000 - Jabo */
@@ -5042,7 +5043,24 @@ void Compile_Vector_VNOOP ( void ) {
 /************************** lc2 functions **************************/
 
 void Compile_Opcode_LBV ( void ) {
-	Cheat_r4300iOpcode(RSP_Opcode_LBV,"RSP_Opcode_LBV");
+	char Reg[256];
+	int offset = RSPOpC.voffset << 0;
+
+	#ifndef CompileLbv
+	Cheat_r4300iOpcode(RSP_Opcode_LBV,"RSP_Opcode_LBV"); return;
+	#endif
+
+	CPU_Message("  %X %s", CompilePC, RSPOpcodeName(RSPOpC.Hex, CompilePC));
+
+	MoveVariableToX86reg(&RSP_GPR[RSPOpC.base].UW, GPR_Name(RSPOpC.base), x86_EBX);
+	if (offset != 0)
+		AddConstToX86Reg(x86_EBX, offset);
+
+	AndConstToX86Reg(x86_EBX, 0x0FFF);
+	XorConstToX86Reg(x86_EBX, 3);
+	MoveN64MemToX86regByte(x86_ECX, x86_EBX);
+	sprintf(Reg, "RSP_Vect[%i].B[%i]", RSPOpC.rt, 15 - RSPOpC.del);
+	MoveX86regByteToVariable(x86_ECX, &RSP_Vect[RSPOpC.rt].B[15 - RSPOpC.del], Reg);
 }
 
 void Compile_Opcode_LSV ( void ) {