diff --git a/Source/Project64-core/N64System/Mips/Disk.cpp b/Source/Project64-core/N64System/Mips/Disk.cpp
index 10040ddb7..d82503850 100644
--- a/Source/Project64-core/N64System/Mips/Disk.cpp
+++ b/Source/Project64-core/N64System/Mips/Disk.cpp
@@ -176,7 +176,7 @@ void DiskCommand()
     {
         // Other commands are basically instant
         g_Reg->ASIC_STATUS |= DD_STATUS_MECHA_INT;
-        g_Reg->FAKE_CAUSE_REGISTER |= CAUSE_IP3;
+        g_Reg->CAUSE_REGISTER.PendingInterrupts |= CAUSE_IP3;
         g_Reg->CheckInterrupts();
     }
 }
@@ -226,7 +226,9 @@ void DiskBMControl(void)
     }
 
     if (!(g_Reg->ASIC_STATUS & DD_STATUS_MECHA_INT) && !(g_Reg->ASIC_STATUS & DD_STATUS_BM_INT))
-        g_Reg->FAKE_CAUSE_REGISTER &= ~CAUSE_IP3;
+    {
+        g_Reg->CAUSE_REGISTER.PendingInterrupts &= ~CAUSE_IP3;
+    }
 
     if (g_Reg->ASIC_BM_CTL & DD_BM_CTL_START)
     {
@@ -245,7 +247,7 @@ void DiskGapSectorCheck()
         if (SECTORS_PER_BLOCK < dd_current)
         {
             g_Reg->ASIC_STATUS &= ~DD_STATUS_BM_INT;
-            g_Reg->FAKE_CAUSE_REGISTER &= ~CAUSE_IP3;
+            g_Reg->CAUSE_REGISTER.PendingInterrupts &= ~CAUSE_IP3;
             g_Reg->CheckInterrupts();
             DiskBMUpdate();
         }
@@ -303,7 +305,7 @@ void DiskBMUpdate()
         }
 
         g_Reg->ASIC_STATUS |= DD_STATUS_BM_INT;
-        g_Reg->FAKE_CAUSE_REGISTER |= CAUSE_IP3;
+        g_Reg->CAUSE_REGISTER.PendingInterrupts |= CAUSE_IP3;
         g_Reg->CheckInterrupts();
         return;
     }
@@ -348,7 +350,7 @@ void DiskBMUpdate()
         }
 
         g_Reg->ASIC_STATUS |= DD_STATUS_BM_INT;
-        g_Reg->FAKE_CAUSE_REGISTER |= CAUSE_IP3;
+        g_Reg->CAUSE_REGISTER.PendingInterrupts |= CAUSE_IP3;
         g_Reg->CheckInterrupts();
     }
 }
@@ -381,13 +383,13 @@ void DiskDMACheck(void)
     if (g_Reg->PI_CART_ADDR_REG == 0x05000000)
     {
         g_Reg->ASIC_STATUS &= ~(DD_STATUS_BM_INT | DD_STATUS_BM_ERR | DD_STATUS_C2_XFER);
-        g_Reg->FAKE_CAUSE_REGISTER &= ~CAUSE_IP3;
+        g_Reg->CAUSE_REGISTER.PendingInterrupts &= ~CAUSE_IP3;
         g_Reg->CheckInterrupts();
     }
     else if (g_Reg->PI_CART_ADDR_REG == 0x05000400)
     {
         g_Reg->ASIC_STATUS &= ~(DD_STATUS_BM_INT | DD_STATUS_BM_ERR | DD_STATUS_DATA_RQ);
-        g_Reg->FAKE_CAUSE_REGISTER &= ~CAUSE_IP3;
+        g_Reg->CAUSE_REGISTER.PendingInterrupts &= ~CAUSE_IP3;
         g_Reg->CheckInterrupts();
     }
 }
\ No newline at end of file
diff --git a/Source/Project64-core/N64System/Mips/Register.cpp b/Source/Project64-core/N64System/Mips/Register.cpp
index 2318ccb86..4b41ce391 100644
--- a/Source/Project64-core/N64System/Mips/Register.cpp
+++ b/Source/Project64-core/N64System/Mips/Register.cpp
@@ -241,15 +241,14 @@ CP0registers::CP0registers(uint64_t * _CP0) :
     ENTRYHI_REGISTER(_CP0[10]),
     COMPARE_REGISTER(_CP0[11]),
     STATUS_REGISTER(_CP0[12]),
-    CAUSE_REGISTER(_CP0[13]),
+    CAUSE_REGISTER((COP0Cause &)_CP0[13]),
     EPC_REGISTER(_CP0[14]),
     PREVID_REGISTER(_CP0[15]),
     CONFIG_REGISTER(_CP0[16]),
     XCONTEXT_REGISTER((COP0XContext &)_CP0[20]),
     TAGLO_REGISTER(_CP0[28]),
     TAGHI_REGISTER(_CP0[29]),
-    ERROREPC_REGISTER(_CP0[30]),
-    FAKE_CAUSE_REGISTER(_CP0[32])
+    ERROREPC_REGISTER(_CP0[30])
 {
 }
 
@@ -359,7 +358,7 @@ void CRegisters::Cop0_MT(COP0Reg Reg, uint64_t Value)
         LogMessage("%08X: Writing 0x%I64U to %s register (originally: 0x%I64U)", (*_PROGRAM_COUNTER), Value, CRegName::Cop0[Reg], m_CP0[Reg]);
         if (Reg == 11) // Compare
         {
-            LogMessage("%08X: Cause register changed from %08X to %08X", (*_PROGRAM_COUNTER), CAUSE_REGISTER, (g_Reg->CAUSE_REGISTER & ~CAUSE_IP7));
+            LogMessage("%08X: Cause register changed from %08X to %08X", (*_PROGRAM_COUNTER), (uint32_t)CAUSE_REGISTER.Value, (uint32_t)(g_Reg->CAUSE_REGISTER.Value & ~CAUSE_IP7));
         }
     }
     m_CP0Latch = Value;
@@ -410,7 +409,7 @@ void CRegisters::Cop0_MT(COP0Reg Reg, uint64_t Value)
     case COP0Reg_Compare:
         g_SystemTimer->UpdateTimers();
         m_CP0[Reg] = Value;
-        FAKE_CAUSE_REGISTER &= ~CAUSE_IP7;
+        CAUSE_REGISTER.PendingInterrupts &= ~CAUSE_IP7;
         g_SystemTimer->UpdateCompareTimer();
         break;
     case COP0Reg_Status:
@@ -503,11 +502,11 @@ void CRegisters::CheckInterrupts()
     mi_intr_reg |= (m_GfxIntrReg & MI_INTR_DP);
     if ((MI_INTR_MASK_REG & mi_intr_reg) != 0)
     {
-        FAKE_CAUSE_REGISTER |= CAUSE_IP2;
+        CAUSE_REGISTER.PendingInterrupts |= CAUSE_IP2;
     }
     else
     {
-        FAKE_CAUSE_REGISTER &= ~CAUSE_IP2;
+        CAUSE_REGISTER.PendingInterrupts &= ~CAUSE_IP2;
     }
     MI_INTR_REG = mi_intr_reg;
     status_register = (uint32_t)STATUS_REGISTER;
@@ -525,7 +524,7 @@ void CRegisters::CheckInterrupts()
         return;
     }
 
-    if ((status_register & FAKE_CAUSE_REGISTER & 0xFF00) != 0)
+    if ((status_register & CAUSE_REGISTER.Value & 0xFF00) != 0)
     {
         if (m_FirstInterupt)
         {
@@ -548,11 +547,11 @@ void CRegisters::DoAddressError(bool DelaySlot, uint64_t BadVaddr, bool FromRead
 
     if (FromRead)
     {
-        CAUSE_REGISTER = EXC_RADE;
+        CAUSE_REGISTER.ExceptionCode = EXC_RADE;
     }
     else
     {
-        CAUSE_REGISTER = EXC_WADE;
+        CAUSE_REGISTER.ExceptionCode = EXC_WADE;
     }
     BAD_VADDR_REGISTER = BadVaddr;
     CONTEXT_REGISTER.BadVPN2 = BadVaddr >> 13;
@@ -561,11 +560,12 @@ void CRegisters::DoAddressError(bool DelaySlot, uint64_t BadVaddr, bool FromRead
 
     if (DelaySlot)
     {
-        CAUSE_REGISTER |= CAUSE_BD;
+        CAUSE_REGISTER.BranchDelay = 1;
         EPC_REGISTER = (int32_t)(m_PROGRAM_COUNTER - 4);
     }
     else
     {
+        CAUSE_REGISTER.BranchDelay = 0;
         EPC_REGISTER = (int32_t)m_PROGRAM_COUNTER;
     }
     STATUS_REGISTER |= STATUS_EXL;
@@ -606,14 +606,15 @@ void CRegisters::DoBreakException(bool DelaySlot)
         }
     }
 
-    CAUSE_REGISTER = EXC_BREAK;
+    CAUSE_REGISTER.ExceptionCode = EXC_BREAK;
     if (DelaySlot)
     {
-        CAUSE_REGISTER |= CAUSE_BD;
+        CAUSE_REGISTER.BranchDelay = 1;
         EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER - 4);
     }
     else
     {
+        CAUSE_REGISTER.BranchDelay = 0;
         EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER);
     }
     STATUS_REGISTER |= STATUS_EXL;
@@ -622,15 +623,16 @@ void CRegisters::DoBreakException(bool DelaySlot)
 
 void CRegisters::DoFloatingPointException(bool DelaySlot)
 {
-    CAUSE_REGISTER = EXC_FPE;
+    CAUSE_REGISTER.ExceptionCode = EXC_FPE;
     if (DelaySlot)
     {
         EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER - 4);
-        CAUSE_REGISTER |= CAUSE_BD;
+        CAUSE_REGISTER.BranchDelay = 1;
     }
     else
     {
         EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER);
+        CAUSE_REGISTER.BranchDelay = 0;
     }
     STATUS_REGISTER |= STATUS_EXL;
     m_PROGRAM_COUNTER = 0x80000180;
@@ -638,15 +640,16 @@ void CRegisters::DoFloatingPointException(bool DelaySlot)
 
 void CRegisters::DoTrapException(bool DelaySlot)
 {
-    CAUSE_REGISTER = EXC_TRAP;
+    CAUSE_REGISTER.ExceptionCode = EXC_TRAP;
     if (DelaySlot)
     {
         EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER - 4);
-        CAUSE_REGISTER |= CAUSE_BD;
+        CAUSE_REGISTER.BranchDelay = 1;
     }
     else
     {
         EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER);
+        CAUSE_REGISTER.BranchDelay = 0;
     }
     m_PROGRAM_COUNTER = 0x80000180;
 }
@@ -665,26 +668,27 @@ void CRegisters::DoCopUnusableException(bool DelaySlot, int32_t Coprocessor)
         }
     }
 
-    CAUSE_REGISTER = EXC_CPU;
+    CAUSE_REGISTER.ExceptionCode = EXC_CPU;
     if (Coprocessor == 1)
     {
-        CAUSE_REGISTER |= 0x10000000;
+        CAUSE_REGISTER.Value |= 0x10000000;
     }
     else if (Coprocessor == 2)
     {
-        CAUSE_REGISTER |= 0x20000000;
+        CAUSE_REGISTER.Value |= 0x20000000;
     }
     else if (Coprocessor == 3)
     {
-        CAUSE_REGISTER |= 0x30000000;
+        CAUSE_REGISTER.Value |= 0x30000000;
     }
     if (DelaySlot)
     {
-        CAUSE_REGISTER |= CAUSE_BD;
+        CAUSE_REGISTER.BranchDelay = 1;
         EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER - 4);
     }
     else
     {
+        CAUSE_REGISTER.BranchDelay = 0;
         EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER);
     }
     STATUS_REGISTER |= STATUS_EXL;
@@ -713,16 +717,16 @@ bool CRegisters::DoIntrException(bool DelaySlot)
         LogMessage("%08X: Interrupt generated", m_PROGRAM_COUNTER);
     }
 
-    CAUSE_REGISTER = FAKE_CAUSE_REGISTER;
-    CAUSE_REGISTER |= EXC_INT;
+    CAUSE_REGISTER.ExceptionCode = EXC_INT;
 
     if (DelaySlot)
     {
-        CAUSE_REGISTER |= CAUSE_BD;
+        CAUSE_REGISTER.BranchDelay = 1;
         EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER - 4);
     }
     else
     {
+        CAUSE_REGISTER.BranchDelay = 0;
         EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER);
     }
 
@@ -733,14 +737,15 @@ bool CRegisters::DoIntrException(bool DelaySlot)
 
 void CRegisters::DoIllegalInstructionException(bool DelaySlot)
 {
-    CAUSE_REGISTER = EXC_II;
+    CAUSE_REGISTER.ExceptionCode = EXC_II;
     if (DelaySlot)
     {
-        CAUSE_REGISTER |= CAUSE_BD;
+        CAUSE_REGISTER.BranchDelay = 1;
         EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER - 4);
     }
     else
     {
+        CAUSE_REGISTER.BranchDelay = 0;
         EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER);
     }
     m_PROGRAM_COUNTER = 0x80000180;
@@ -749,14 +754,15 @@ void CRegisters::DoIllegalInstructionException(bool DelaySlot)
 
 void CRegisters::DoOverflowException(bool DelaySlot)
 {
-    CAUSE_REGISTER = EXC_OV;
+    CAUSE_REGISTER.ExceptionCode = EXC_OV;
     if (DelaySlot)
     {
-        CAUSE_REGISTER |= CAUSE_BD;
+        CAUSE_REGISTER.BranchDelay = 1;
         EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER - 4);
     }
     else
     {
+        CAUSE_REGISTER.BranchDelay = 0;
         EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER);
     }
     m_PROGRAM_COUNTER = 0x80000180;
@@ -765,7 +771,7 @@ void CRegisters::DoOverflowException(bool DelaySlot)
 
 void CRegisters::DoTLBReadMiss(bool DelaySlot, uint64_t BadVaddr)
 {
-    CAUSE_REGISTER = EXC_RMISS;
+    CAUSE_REGISTER.ExceptionCode = EXC_RMISS;
     BAD_VADDR_REGISTER = BadVaddr;
     CONTEXT_REGISTER.BadVPN2 = BadVaddr >> 13;
     ENTRYHI_REGISTER = (BadVaddr & 0xFFFFE000);
@@ -773,11 +779,12 @@ void CRegisters::DoTLBReadMiss(bool DelaySlot, uint64_t BadVaddr)
     {
         if (DelaySlot)
         {
-            CAUSE_REGISTER |= CAUSE_BD;
+            CAUSE_REGISTER.BranchDelay = 1;
             EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER - 4);
         }
         else
         {
+            CAUSE_REGISTER.BranchDelay = 0;
             EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER);
         }
         if (g_TLB->AddressDefined((uint32_t)BadVaddr))
@@ -802,7 +809,7 @@ void CRegisters::DoTLBReadMiss(bool DelaySlot, uint64_t BadVaddr)
 
 void CRegisters::DoTLBWriteMiss(bool DelaySlot, uint64_t BadVaddr)
 {
-    CAUSE_REGISTER = EXC_WMISS;
+    CAUSE_REGISTER.ExceptionCode = EXC_WMISS;
     BAD_VADDR_REGISTER = BadVaddr;
     CONTEXT_REGISTER.BadVPN2 = BadVaddr >> 13;
     ENTRYHI_REGISTER = (BadVaddr & 0xFFFFE000);
@@ -810,11 +817,12 @@ void CRegisters::DoTLBWriteMiss(bool DelaySlot, uint64_t BadVaddr)
     {
         if (DelaySlot)
         {
-            CAUSE_REGISTER |= CAUSE_BD;
+            CAUSE_REGISTER.BranchDelay = 1;
             EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER - 4);
         }
         else
         {
+            CAUSE_REGISTER.BranchDelay = 0;
             EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER);
         }
         if (g_TLB->AddressDefined((uint32_t)BadVaddr))
@@ -851,14 +859,15 @@ void CRegisters::DoSysCallException(bool DelaySlot)
         }
     }
 
-    CAUSE_REGISTER = EXC_SYSCALL;
+    CAUSE_REGISTER.ExceptionCode = EXC_SYSCALL;
     if (DelaySlot)
     {
-        CAUSE_REGISTER |= CAUSE_BD;
+        CAUSE_REGISTER.BranchDelay = 1;
         EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER - 4);
     }
     else
     {
+        CAUSE_REGISTER.BranchDelay = 0;
         EPC_REGISTER = (int64_t)(int32_t)m_PROGRAM_COUNTER;
     }
     STATUS_REGISTER |= STATUS_EXL;
diff --git a/Source/Project64-core/N64System/Mips/Register.h b/Source/Project64-core/N64System/Mips/Register.h
index 1298bed6f..4aa20f939 100644
--- a/Source/Project64-core/N64System/Mips/Register.h
+++ b/Source/Project64-core/N64System/Mips/Register.h
@@ -19,6 +19,21 @@
 #pragma warning(push)
 #pragma warning(disable : 4201) // Non-standard extension used: nameless struct/union
 
+union COP0Cause
+{
+    uint64_t Value;
+
+    struct
+    {
+        unsigned : 2;
+        unsigned ExceptionCode : 5;
+        unsigned : 1;
+        unsigned PendingInterrupts : 8;
+        unsigned : 15;
+        unsigned BranchDelay : 1;
+    };
+};
+
 union COP0Context
 {
     uint64_t Value;
@@ -113,7 +128,7 @@ public:
     uint64_t & ENTRYHI_REGISTER;
     uint64_t & COMPARE_REGISTER;
     uint64_t & STATUS_REGISTER;
-    uint64_t & CAUSE_REGISTER;
+    COP0Cause & CAUSE_REGISTER;
     uint64_t & EPC_REGISTER;
     uint64_t & PREVID_REGISTER;
     uint64_t & CONFIG_REGISTER;
@@ -121,7 +136,6 @@ public:
     uint64_t & TAGLO_REGISTER;
     uint64_t & TAGHI_REGISTER;
     uint64_t & ERROREPC_REGISTER;
-    uint64_t & FAKE_CAUSE_REGISTER;
 
 private:
     CP0registers();
@@ -152,36 +166,34 @@ enum
     STATUS_CU3 = 0x80000000,
 
     // Cause flags
-    CAUSE_EXC_CODE = 0xFF,
-    CAUSE_IP0 = 0x100,
-    CAUSE_IP1 = 0x200,
-    CAUSE_IP2 = 0x400,
-    CAUSE_IP3 = 0x800,
-    CAUSE_IP4 = 0x1000,
-    CAUSE_IP5 = 0x2000,
-    CAUSE_IP6 = 0x4000,
-    CAUSE_IP7 = 0x8000,
-    CAUSE_BD = 0x80000000,
+    CAUSE_IP0 = 0x1,
+    CAUSE_IP1 = 0x2,
+    CAUSE_IP2 = 0x4,
+    CAUSE_IP3 = 0x8,
+    CAUSE_IP4 = 0x10,
+    CAUSE_IP5 = 0x20,
+    CAUSE_IP6 = 0x40,
+    CAUSE_IP7 = 0x80,
 
     // Cause exception ID's
-    EXC_INT = 0,      // Interrupt
-    EXC_MOD = 4,      // TLB mod
-    EXC_RMISS = 8,    // Read TLB miss
-    EXC_WMISS = 12,   // Write TLB miss
-    EXC_RADE = 16,    // Read address error
-    EXC_WADE = 20,    // Write address error
-    EXC_IBE = 24,     // Instruction bus error
-    EXC_DBE = 28,     // Data bus error
-    EXC_SYSCALL = 32, // Syscall
-    EXC_BREAK = 36,   // Breakpoint
-    EXC_II = 40,      // Illegal instruction
-    EXC_CPU = 44,     // Co-processor unusable
-    EXC_OV = 48,      // Overflow
-    EXC_TRAP = 52,    // Trap exception
-    EXC_VCEI = 56,    // Virtual coherency on instruction fetch
-    EXC_FPE = 60,     // Floating point exception
-    EXC_WATCH = 92,   // Watchpoint reference
-    EXC_VCED = 124,   // Virtual coherency on data read
+    EXC_INT = 0,     // Interrupt
+    EXC_MOD = 1,     // TLB mod
+    EXC_RMISS = 2,   // Read TLB miss
+    EXC_WMISS = 3,   // Write TLB miss
+    EXC_RADE = 4,    // Read address error
+    EXC_WADE = 5,    // Write address error
+    EXC_IBE = 6,     // Instruction bus error
+    EXC_DBE = 7,     // Data bus error
+    EXC_SYSCALL = 8, // Syscall
+    EXC_BREAK = 9,   // Breakpoint
+    EXC_II = 10,     // Illegal instruction
+    EXC_CPU = 11,    // Co-processor unusable
+    EXC_OV = 12,     // Overflow
+    EXC_TRAP = 13,   // Trap exception
+    EXC_VCEI = 14,   // Virtual coherency on instruction fetch
+    EXC_FPE = 15,    // Floating point exception
+    EXC_WATCH = 23,  // Watchpoint reference
+    EXC_VCED = 31,   // Virtual coherency on data read
 };
 
 // Float point control status register flags
@@ -411,7 +423,7 @@ public:
     // General registers
     uint32_t m_PROGRAM_COUNTER;
     MIPS_DWORD m_GPR[32];
-    uint64_t m_CP0[33];
+    uint64_t m_CP0[32];
     uint64_t m_CP0Latch;
     MIPS_DWORD m_HI;
     MIPS_DWORD m_LO;
diff --git a/Source/Project64-core/N64System/Mips/SystemTiming.cpp b/Source/Project64-core/N64System/Mips/SystemTiming.cpp
index dc9daf265..870925ccd 100644
--- a/Source/Project64-core/N64System/Mips/SystemTiming.cpp
+++ b/Source/Project64-core/N64System/Mips/SystemTiming.cpp
@@ -193,7 +193,7 @@ void CSystemTimer::TimerDone()
     switch (m_Current)
     {
     case CSystemTimer::CompareTimer:
-        m_Reg.FAKE_CAUSE_REGISTER |= CAUSE_IP7;
+        m_Reg.CAUSE_REGISTER.PendingInterrupts |= CAUSE_IP7;
         m_Reg.CheckInterrupts();
         UpdateCompareTimer();
         break;
@@ -225,7 +225,7 @@ void CSystemTimer::TimerDone()
     case CSystemTimer::DDSeekTimer:
         StopTimer(CSystemTimer::DDSeekTimer);
         m_Reg.ASIC_STATUS |= DD_STATUS_MECHA_INT;
-        m_Reg.FAKE_CAUSE_REGISTER |= CAUSE_IP3;
+        m_Reg.CAUSE_REGISTER.PendingInterrupts |= CAUSE_IP3;
         m_Reg.CheckInterrupts();
         break;
     case CSystemTimer::DDMotorTimer:
diff --git a/Source/Project64-core/N64System/N64System.cpp b/Source/Project64-core/N64System/N64System.cpp
index f88ce4117..c82fa1a9e 100644
--- a/Source/Project64-core/N64System/N64System.cpp
+++ b/Source/Project64-core/N64System/N64System.cpp
@@ -852,7 +852,7 @@ void CN64System::GameReset()
 {
     m_SystemTimer.SetTimer(CSystemTimer::SoftResetTimer, 0x3000000, false);
     m_Plugins->Gfx()->ShowCFB();
-    m_Reg.FAKE_CAUSE_REGISTER |= CAUSE_IP4;
+    m_Reg.CAUSE_REGISTER.PendingInterrupts |= CAUSE_IP4;
     m_Plugins->Gfx()->SoftReset();
     if (m_SyncCPU)
     {
@@ -1030,7 +1030,7 @@ void CN64System::InitRegisters(bool bPostPif, CMipsMemoryVM & MMU)
     m_Reg.COUNT_REGISTER = 0x5000;
     m_Reg.MI_VERSION_REG = 0x02020102;
     m_Reg.SP_STATUS_REG = 0x00000001;
-    m_Reg.CAUSE_REGISTER = 0x0000005C;
+    m_Reg.CAUSE_REGISTER.Value = 0x0000005C;
     m_Reg.CONTEXT_REGISTER.Value = 0x007FFFF0;
     m_Reg.EPC_REGISTER = 0xFFFFFFFFFFFFFFFF;
     m_Reg.BAD_VADDR_REGISTER = 0xFFFFFFFFFFFFFFFF;
diff --git a/Source/Project64/UserInterface/Debugger/Debugger-RegisterTabData.h b/Source/Project64/UserInterface/Debugger/Debugger-RegisterTabData.h
index 1c4386a73..d8fd6e8b8 100644
--- a/Source/Project64/UserInterface/Debugger/Debugger-RegisterTabData.h
+++ b/Source/Project64/UserInterface/Debugger/Debugger-RegisterTabData.h
@@ -164,7 +164,6 @@ public:
         {IDC_COP0_15_LBL, IDC_COP0_15_EDIT},
         {IDC_COP0_16_LBL, IDC_COP0_16_EDIT},
         {IDC_COP0_17_LBL, IDC_COP0_17_EDIT},
-        {IDC_COP0_18_LBL, IDC_COP0_18_EDIT},
     };
 
     static constexpr TabRecord COP0 = TabRecord{sizeof(COP0Fields), COP0Fields};
diff --git a/Source/Project64/UserInterface/Debugger/Debugger-RegisterTabs.cpp b/Source/Project64/UserInterface/Debugger/Debugger-RegisterTabs.cpp
index 8c8e3b154..16a182941 100644
--- a/Source/Project64/UserInterface/Debugger/Debugger-RegisterTabs.cpp
+++ b/Source/Project64/UserInterface/Debugger/Debugger-RegisterTabs.cpp
@@ -144,16 +144,15 @@ void CRegisterTabs::RefreshEdits()
     m_COP0Edits[9].SetValue((uint32_t)g_Reg->ENTRYHI_REGISTER, DisplayMode::ZeroExtend);
     m_COP0Edits[10].SetValue((uint32_t)g_Reg->COMPARE_REGISTER, DisplayMode::ZeroExtend);
     m_COP0Edits[11].SetValue((uint32_t)g_Reg->STATUS_REGISTER, DisplayMode::ZeroExtend);
-    m_COP0Edits[12].SetValue((uint32_t)g_Reg->CAUSE_REGISTER, DisplayMode::ZeroExtend);
+    m_COP0Edits[12].SetValue((uint32_t)g_Reg->CAUSE_REGISTER.Value, DisplayMode::ZeroExtend);
     m_COP0Edits[13].SetValue((uint32_t)g_Reg->EPC_REGISTER, DisplayMode::ZeroExtend);
     m_COP0Edits[14].SetValue((uint32_t)g_Reg->CONFIG_REGISTER, DisplayMode::ZeroExtend);
     m_COP0Edits[15].SetValue((uint32_t)g_Reg->TAGLO_REGISTER, DisplayMode::ZeroExtend);
     m_COP0Edits[16].SetValue((uint32_t)g_Reg->TAGHI_REGISTER, DisplayMode::ZeroExtend);
     m_COP0Edits[17].SetValue((uint32_t)g_Reg->ERROREPC_REGISTER, DisplayMode::ZeroExtend);
-    m_COP0Edits[18].SetValue((uint32_t)g_Reg->FAKE_CAUSE_REGISTER, DisplayMode::ZeroExtend);
 
     CAUSE cause;
-    cause.intval = (uint32_t)g_Reg->CAUSE_REGISTER;
+    cause.intval = (uint32_t)g_Reg->CAUSE_REGISTER.Value;
 
     const char * szExceptionCode = ExceptionCodes[cause.exceptionCode];
     m_CauseTip.SetWindowText(stdstr(szExceptionCode).ToUTF16().c_str());
@@ -324,13 +323,12 @@ void CRegisterTabs::RegisterChanged(HWND hDlg, TAB_ID srcTabId, WPARAM wParam)
     case IDC_COP0_9_EDIT: g_Reg->ENTRYHI_REGISTER = value; break;
     case IDC_COP0_10_EDIT: g_Reg->COMPARE_REGISTER = value; break;
     case IDC_COP0_11_EDIT: g_Reg->STATUS_REGISTER = value; break;
-    case IDC_COP0_12_EDIT: g_Reg->CAUSE_REGISTER = value; break;
+    case IDC_COP0_12_EDIT: g_Reg->CAUSE_REGISTER.Value = value; break;
     case IDC_COP0_13_EDIT: g_Reg->EPC_REGISTER = value; break;
     case IDC_COP0_14_EDIT: g_Reg->CONFIG_REGISTER = value; break;
     case IDC_COP0_15_EDIT: g_Reg->TAGLO_REGISTER = value; break;
     case IDC_COP0_16_EDIT: g_Reg->TAGHI_REGISTER = value; break;
     case IDC_COP0_17_EDIT: g_Reg->ERROREPC_REGISTER = value; break;
-    case IDC_COP0_18_EDIT: g_Reg->FAKE_CAUSE_REGISTER = value; break;
 
     case IDC_RDRAM00_EDIT: g_Reg->RDRAM_CONFIG_REG = value; break; // or device_type
     case IDC_RDRAM04_EDIT: g_Reg->RDRAM_DEVICE_ID_REG = value; break;
diff --git a/Source/Project64/UserInterface/Debugger/Debugger.cpp b/Source/Project64/UserInterface/Debugger/Debugger.cpp
index 6e51c8085..a2de06ec0 100644
--- a/Source/Project64/UserInterface/Debugger/Debugger.cpp
+++ b/Source/Project64/UserInterface/Debugger/Debugger.cpp
@@ -509,8 +509,8 @@ void CDebuggerUI::TLBChanged()
 // Exception handling - break on exception vector if exception breakpoint is set
 void CDebuggerUI::HandleCPUException(void)
 {
-    int exc = (g_Reg->CAUSE_REGISTER >> 2) & 0x1F;
-    int intr = (g_Reg->CAUSE_REGISTER >> 8) & 0xFF;
+    int exc = (g_Reg->CAUSE_REGISTER.Value >> 2) & 0x1F;
+    int intr = (g_Reg->CAUSE_REGISTER.Value >> 8) & 0xFF;
     int fpExc = (g_Reg->m_FPCR[31] >> 12) & 0x3F;
     int rcpIntr = g_Reg->MI_INTR_REG & 0x2F;
 
diff --git a/Source/Project64/UserInterface/Debugger/ScriptAPI/ScriptAPI_cpu.cpp b/Source/Project64/UserInterface/Debugger/ScriptAPI/ScriptAPI_cpu.cpp
index 55d6de95b..66389fb35 100644
--- a/Source/Project64/UserInterface/Debugger/ScriptAPI/ScriptAPI_cpu.cpp
+++ b/Source/Project64/UserInterface/Debugger/ScriptAPI/ScriptAPI_cpu.cpp
@@ -164,7 +164,7 @@ duk_ret_t ScriptAPI::js_cpu_cop0_get(duk_context * ctx)
 
     if (strcmp(name, "cause") == 0)
     {
-        duk_push_uint(ctx, (uint32_t)(g_Reg->FAKE_CAUSE_REGISTER | g_Reg->CAUSE_REGISTER));
+        duk_push_uint(ctx, (uint32_t)(g_Reg->CAUSE_REGISTER.Value));
         return 1;
     }
 
@@ -201,8 +201,7 @@ duk_ret_t ScriptAPI::js_cpu_cop0_set(duk_context * ctx)
     if (strcmp(name, "cause") == 0)
     {
         uint32_t value = duk_get_uint(ctx, 2);
-        g_Reg->FAKE_CAUSE_REGISTER = value;
-        g_Reg->CAUSE_REGISTER = value;
+        g_Reg->CAUSE_REGISTER.Value = value;
         g_Reg->CheckInterrupts();
 
         duk_push_true(ctx);
diff --git a/Source/Project64/UserInterface/UIResources.rc b/Source/Project64/UserInterface/UIResources.rc
index d288fa3ff..455f0e435 100644
--- a/Source/Project64/UserInterface/UIResources.rc
+++ b/Source/Project64/UserInterface/UIResources.rc
@@ -956,7 +956,6 @@ BEGIN
     LTEXT           "TagLo",IDC_COP0_15_LBL,3,180,33,8
     LTEXT           "TagHi",IDC_COP0_16_LBL,87,15,33,8
     LTEXT           "ErrorEPC",IDC_COP0_17_LBL,87,26,33,8
-    LTEXT           "FakeCause",IDC_COP0_18_LBL,87,37,37,8
     EDITTEXT        IDC_COP0_0_EDIT,37,15,39,10,ES_UPPERCASE | ES_AUTOHSCROLL,WS_EX_RIGHT
     EDITTEXT        IDC_COP0_1_EDIT,37,26,39,10,ES_UPPERCASE | ES_AUTOHSCROLL,WS_EX_RIGHT
     EDITTEXT        IDC_COP0_2_EDIT,37,37,39,10,ES_UPPERCASE | ES_AUTOHSCROLL,WS_EX_RIGHT
@@ -975,7 +974,6 @@ BEGIN
     EDITTEXT        IDC_COP0_15_EDIT,37,180,39,10,ES_UPPERCASE | ES_AUTOHSCROLL,WS_EX_RIGHT
     EDITTEXT        IDC_COP0_16_EDIT,123,15,39,10,ES_UPPERCASE | ES_AUTOHSCROLL,WS_EX_RIGHT
     EDITTEXT        IDC_COP0_17_EDIT,123,26,39,10,ES_UPPERCASE | ES_AUTOHSCROLL,WS_EX_RIGHT
-    EDITTEXT        IDC_COP0_18_EDIT,123,37,39,10,ES_UPPERCASE | ES_AUTOHSCROLL,WS_EX_RIGHT
     LTEXT           "...",IDC_CAUSE_TIP,80,149,70,8
     LTEXT           "CPU Coprocessor 0",-1,3,4,130,8
 END
diff --git a/Source/Project64/UserInterface/resource.h b/Source/Project64/UserInterface/resource.h
index cf1e135b2..913e1740c 100644
--- a/Source/Project64/UserInterface/resource.h
+++ b/Source/Project64/UserInterface/resource.h
@@ -474,7 +474,6 @@
 #define IDC_COP0_15_EDIT                1330
 #define IDC_COP0_16_EDIT                1331
 #define IDC_COP0_17_EDIT                1332
-#define IDC_COP0_18_EDIT                1333
 #define IDC_FILTER_STATIC               1339
 #define IDC_BLOCK_INFO                  1350
 #define IDC_BACK_BTN                    1352