Core: Start to add R4300iInstruction to do analysis of an opcode
This commit is contained in:
zilmar
parent
64c0e93cde
commit
7f3b8e3601
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@ -4,8 +4,8 @@
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#include <Project64-core/N64System/SystemGlobals.h>
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#include <Project64-core/N64System/N64System.h>
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#include <Project64-core/N64System/Mips/MemoryVirtualMem.h>
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#include <Project64-core/N64System/Mips/OpcodeName.h>
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#include <Project64-core/N64System/Interpreter/InterpreterOps32.h>
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#include <Project64-core/N64System/Mips/R4300iInstruction.h>
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#include <Project64-core/Plugins/Plugin.h>
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#include <Project64-core/Plugins/GFXPlugin.h>
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#include <Project64-core/ExceptionHandler.h>
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@ -20,9 +20,9 @@ void ExecuteInterpreterOps(uint32_t /*Cycles*/)
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bool DelaySlotEffectsCompare(uint32_t PC, uint32_t Reg1, uint32_t Reg2)
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{
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OPCODE Command;
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R4300iOpcode Command;
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if (!g_MMU->MemoryValue32(PC + 4, Command.Hex))
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if (!g_MMU->MemoryValue32(PC + 4, Command.Value))
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{
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//g_Notify->DisplayError("Failed to load word 2");
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//ExitThread(0);
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@ -88,7 +88,7 @@ bool DelaySlotEffectsCompare(uint32_t PC, uint32_t Reg1, uint32_t Reg2)
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default:
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if (CDebugSettings::HaveDebugger())
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{
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g_Notify->DisplayError(stdstr_f("Does %s effect delay slot at %X?", R4300iOpcodeName(Command.Hex, PC + 4), PC).c_str());
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g_Notify->DisplayError(stdstr_f("Does %s effect delay slot at %X?", R4300iInstruction(PC + 4, Command.Value).Name(), PC).c_str());
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}
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return true;
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}
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@ -119,7 +119,7 @@ bool DelaySlotEffectsCompare(uint32_t PC, uint32_t Reg1, uint32_t Reg2)
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default:
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if (CDebugSettings::HaveDebugger())
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{
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g_Notify->DisplayError(stdstr_f("Does %s effect delay slot at %X?\n6", R4300iOpcodeName(Command.Hex, PC + 4), PC).c_str());
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g_Notify->DisplayError(stdstr_f("Does %s effect delay slot at %X?\n6", R4300iInstruction(PC + 4, Command.Value).Name(), PC).c_str());
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}
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return true;
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}
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@ -128,7 +128,7 @@ bool DelaySlotEffectsCompare(uint32_t PC, uint32_t Reg1, uint32_t Reg2)
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{
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if (CDebugSettings::HaveDebugger())
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{
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g_Notify->DisplayError(stdstr_f("Does %s effect delay slot at %X?\n7", R4300iOpcodeName(Command.Hex, PC + 4), PC).c_str());
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g_Notify->DisplayError(stdstr_f("Does %s effect delay slot at %X?\n7", R4300iInstruction(PC + 4, Command.Value).Name(), PC).c_str());
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}
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return true;
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}
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@ -157,7 +157,7 @@ bool DelaySlotEffectsCompare(uint32_t PC, uint32_t Reg1, uint32_t Reg2)
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default:
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if (CDebugSettings::HaveDebugger())
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{
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g_Notify->DisplayError(stdstr_f("Does %s effect delay slot at %X?", R4300iOpcodeName(Command.Hex, PC + 4), PC).c_str());
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g_Notify->DisplayError(stdstr_f("Does %s effect delay slot at %X?", R4300iInstruction(PC + 4, Command.Value).Name(), PC).c_str());
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}
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return true;
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}
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@ -205,7 +205,7 @@ bool DelaySlotEffectsCompare(uint32_t PC, uint32_t Reg1, uint32_t Reg2)
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default:
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if (CDebugSettings::HaveDebugger())
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{
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g_Notify->DisplayError(stdstr_f("Does %s effect delay slot at %X?", R4300iOpcodeName(Command.Hex, PC + 4), PC).c_str());
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g_Notify->DisplayError(stdstr_f("Does %s effect delay slot at %X?", R4300iInstruction(PC + 4, Command.Value).Name(), PC).c_str());
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}
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return true;
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}
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@ -262,7 +262,7 @@ void CInterpreterCPU::ExecuteCPU()
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bool & Done = g_System->m_EndEmulation;
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PIPELINE_STAGE & PipelineStage = g_System->m_PipelineStage;
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uint32_t & PROGRAM_COUNTER = *_PROGRAM_COUNTER;
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OPCODE & Opcode = R4300iOp::m_Opcode;
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R4300iOpcode & Opcode = R4300iOp::m_Opcode;
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uint32_t & JumpToLocation = g_System->m_JumpToLocation;
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bool & TestTimer = R4300iOp::m_TestTimer;
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const int32_t & bDoSomething = g_SystemEvents->DoSomething();
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@ -274,7 +274,7 @@ void CInterpreterCPU::ExecuteCPU()
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{
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while (!Done)
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{
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if (!g_MMU->MemoryValue32(PROGRAM_COUNTER, Opcode.Hex))
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if (!g_MMU->MemoryValue32(PROGRAM_COUNTER, Opcode.Value))
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{
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g_Reg->DoTLBReadMiss(PipelineStage == PIPELINE_STAGE_JUMP, PROGRAM_COUNTER);
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PipelineStage = PIPELINE_STAGE_NORMAL;
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@ -308,8 +308,8 @@ void CInterpreterCPU::ExecuteCPU()
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/* if (PROGRAM_COUNTER > 0x80000300 && PROGRAM_COUNTER < 0x80380000)
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{
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WriteTraceF((TraceType)(TraceError | TraceNoHeader),"%X: %s",*_PROGRAM_COUNTER,R4300iOpcodeName(Opcode.Hex,*_PROGRAM_COUNTER));
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// WriteTraceF((TraceType)(TraceError | TraceNoHeader),"%X: %s t9: %08X v1: %08X",*_PROGRAM_COUNTER,R4300iOpcodeName(Opcode.Hex,*_PROGRAM_COUNTER),_GPR[0x19].UW[0],_GPR[0x03].UW[0]);
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WriteTraceF((TraceType)(TraceError | TraceNoHeader),"%X: %s",*_PROGRAM_COUNTER,R4300iInstruction(*_PROGRAM_COUNTER, Opcode.Value).NameAndParam().c_str());
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// WriteTraceF((TraceType)(TraceError | TraceNoHeader),"%X: %s t9: %08X v1: %08X",*_PROGRAM_COUNTER,R4300iInstruction(*_PROGRAM_COUNTER, Opcode.Value).NameAndParam().c_str(),_GPR[0x19].UW[0],_GPR[0x03].UW[0]);
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// WriteTraceF((TraceType)(TraceError | TraceNoHeader),"%X: %d %d",*_PROGRAM_COUNTER,*g_NextTimer,g_SystemTimer->CurrentType());
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} */
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@ -373,7 +373,7 @@ void CInterpreterCPU::ExecuteOps(int32_t Cycles)
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{
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bool & Done = g_System->m_EndEmulation;
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uint32_t & PROGRAM_COUNTER = *_PROGRAM_COUNTER;
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OPCODE & Opcode = R4300iOp::m_Opcode;
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R4300iOpcode & Opcode = R4300iOp::m_Opcode;
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PIPELINE_STAGE & PipelineStage = g_System->m_PipelineStage;
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uint32_t & JumpToLocation = g_System->m_JumpToLocation;
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bool & TestTimer = R4300iOp::m_TestTimer;
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@ -391,18 +391,18 @@ void CInterpreterCPU::ExecuteOps(int32_t Cycles)
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return;
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}
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if (g_MMU->MemoryValue32(PROGRAM_COUNTER, Opcode.Hex))
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if (g_MMU->MemoryValue32(PROGRAM_COUNTER, Opcode.Value))
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{
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/*if (PROGRAM_COUNTER > 0x80000300 && PROGRAM_COUNTER< 0x80380000)
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{
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WriteTraceF((TraceType)(TraceError | TraceNoHeader),"%X: %s",*_PROGRAM_COUNTER,R4300iOpcodeName(Opcode.Hex,*_PROGRAM_COUNTER));
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//WriteTraceF((TraceType)(TraceError | TraceNoHeader),"%X: %s t9: %08X v1: %08X",*_PROGRAM_COUNTER,R4300iOpcodeName(Opcode.Hex,*_PROGRAM_COUNTER),_GPR[0x19].UW[0],_GPR[0x03].UW[0]);
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WriteTraceF((TraceType)(TraceError | TraceNoHeader),"%X: %s",*_PROGRAM_COUNTER,R4300iInstruction(*_PROGRAM_COUNTER, Opcode.Value).NameAndParam().c_str());
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//WriteTraceF((TraceType)(TraceError | TraceNoHeader),"%X: %s t9: %08X v1: %08X",*_PROGRAM_COUNTER,R4300iInstruction(*_PROGRAM_COUNTER, Opcode.Value).NameAndParam().c_str(),_GPR[0x19].UW[0],_GPR[0x03].UW[0]);
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//WriteTraceF((TraceType)(TraceError | TraceNoHeader),"%X: %d %d",*_PROGRAM_COUNTER,*g_NextTimer,g_SystemTimer->CurrentType());
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}*/
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/*if (PROGRAM_COUNTER > 0x80323000 && PROGRAM_COUNTER< 0x80380000)
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{
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WriteTraceF((TraceType)(TraceError | TraceNoHeader),"%X: %s",*_PROGRAM_COUNTER,R4300iOpcodeName(Opcode.Hex,*_PROGRAM_COUNTER));
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//WriteTraceF((TraceType)(TraceError | TraceNoHeader),"%X: %s t9: %08X v1: %08X",*_PROGRAM_COUNTER,R4300iOpcodeName(Opcode.Hex,*_PROGRAM_COUNTER),_GPR[0x19].UW[0],_GPR[0x03].UW[0]);
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WriteTraceF((TraceType)(TraceError | TraceNoHeader),"%X: %s",*_PROGRAM_COUNTER,R4300iInstruction(*_PROGRAM_COUNTER, Opcode.Value).NameAndParam().c_str());
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//WriteTraceF((TraceType)(TraceError | TraceNoHeader),"%X: %s t9: %08X v1: %08X",*_PROGRAM_COUNTER,R4300iInstruction(*_PROGRAM_COUNTER, Opcode.Value).NameAndParam().c_str(),_GPR[0x19].UW[0],_GPR[0x03].UW[0]);
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//WriteTraceF((TraceType)(TraceError | TraceNoHeader),"%X: %d %d",*_PROGRAM_COUNTER,*g_NextTimer,g_SystemTimer->CurrentType());
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}*/
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m_R4300i_Opcode[Opcode.op]();
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@ -416,7 +416,7 @@ void CInterpreterCPU::ExecuteOps(int32_t Cycles)
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{
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if (TestValue != CurrentValue)
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{
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WriteTraceF(TraceError,"%X: %X changed (%s)",PROGRAM_COUNTER,TestAddress,R4300iOpcodeName(m_Opcode.Hex,PROGRAM_COUNTER) );
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WriteTraceF(TraceError,"%X: %X changed (%s)",PROGRAM_COUNTER,TestAddress,R4300iInstruction(PROGRAM_COUNTER, m_Opcode.Value).NameAndParam().c_str());
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CurrentValue = TestValue;
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}
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}*/
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@ -5,7 +5,7 @@
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#include <Project64-core/N64System/Mips/MemoryVirtualMem.h>
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#include <Project64-core/N64System/Mips/SystemTiming.h>
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#include <Project64-core/N64System/Mips/TLB.h>
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#include <Project64-core/N64System/Mips/OpcodeName.h>
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#include <Project64-core/N64System/Mips/R4300iInstruction.h>
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#include <Project64-core/N64System/Interpreter/InterpreterCPU.h>
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#include <Project64-core/Logging.h>
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#include <Project64-core/Debugger.h>
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@ -25,7 +25,7 @@ float truncf(float num)
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#endif
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bool R4300iOp::m_TestTimer = false;
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OPCODE R4300iOp::m_Opcode;
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R4300iOpcode R4300iOp::m_Opcode;
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R4300iOp::Func R4300iOp::Jump_Opcode[64];
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R4300iOp::Func R4300iOp::Jump_Special[64];
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@ -2612,8 +2612,8 @@ void R4300iOp::COP1_L_CVT_D()
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void R4300iOp::UnknownOpcode()
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{
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g_Notify->DisplayError(stdstr_f("%s: %08X\n%s\n\nStopping emulation", GS(MSG_UNHANDLED_OP), (*_PROGRAM_COUNTER),
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R4300iOpcodeName(m_Opcode.Hex, (*_PROGRAM_COUNTER))).c_str());
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R4300iInstruction Opcode(*_PROGRAM_COUNTER, m_Opcode.Value);
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g_Notify->DisplayError(stdstr_f("%s: %08X\n%s %s\n\nStopping emulation", GS(MSG_UNHANDLED_OP), (*_PROGRAM_COUNTER), Opcode.Name(), Opcode.Param()).c_str());
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g_System->m_EndEmulation = true;
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g_Notify->BreakPoint(__FILE__, __LINE__);
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@ -2,7 +2,7 @@
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#include <Project64-core/Settings/DebugSettings.h>
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#include <Project64-core/N64System/Mips/Register.h>
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#include <Project64-core/N64System/Mips/OpCode.h>
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#include <Project64-core/N64System/Mips/R4300iOpcode.h>
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class R4300iOp :
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public CLogging,
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@ -210,7 +210,7 @@ public:
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static Func* BuildInterpreter();
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static bool m_TestTimer;
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static OPCODE m_Opcode;
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static R4300iOpcode m_Opcode;
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static bool MemoryBreakpoint();
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@ -5,7 +5,6 @@
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#include <Project64-core\N64System\N64Rom.h>
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#include <Project64-core\N64System\N64System.h>
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#include <Project64-core\N64System\Recompiler\RecompilerCodeLog.h>
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#include <Project64-core\N64System\Mips\OpcodeName.h>
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#include <Project64-core\N64System\Mips\Disk.h>
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#include <Project64-core\Debugger.h>
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#include <Project64-core\ExceptionHandler.h>
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@ -1,148 +0,0 @@
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#pragma once
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#pragma warning(push)
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#pragma warning(disable : 4201) // warning C4201: nonstandard extension used : nameless struct/union
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union OPCODE
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{
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uint32_t Hex;
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uint8_t Ascii[4];
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struct
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{
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unsigned offset : 16;
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unsigned rt : 5;
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unsigned rs : 5;
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unsigned op : 6;
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};
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struct
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{
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unsigned immediate : 16;
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unsigned : 5;
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unsigned base : 5;
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unsigned : 6;
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};
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struct
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{
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unsigned target : 26;
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unsigned : 6;
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};
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struct
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{
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unsigned funct : 6;
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unsigned sa : 5;
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unsigned rd : 5;
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unsigned : 5;
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unsigned : 5;
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unsigned : 6;
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};
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struct
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{
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unsigned : 6;
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unsigned fd : 5;
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unsigned fs : 5;
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unsigned ft : 5;
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unsigned fmt : 5;
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unsigned : 6;
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};
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struct
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{
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unsigned : 6;
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unsigned code : 20;
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unsigned : 6;
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};
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};
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#pragma warning(pop)
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enum R4300iOpCodes
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{
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R4300i_SPECIAL = 0, R4300i_REGIMM = 1, R4300i_J = 2, R4300i_JAL = 3,
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R4300i_BEQ = 4, R4300i_BNE = 5, R4300i_BLEZ = 6, R4300i_BGTZ = 7,
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R4300i_ADDI = 8, R4300i_ADDIU = 9, R4300i_SLTI = 10, R4300i_SLTIU = 11,
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R4300i_ANDI = 12, R4300i_ORI = 13, R4300i_XORI = 14, R4300i_LUI = 15,
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R4300i_CP0 = 16, R4300i_CP1 = 17, R4300i_BEQL = 20, R4300i_BNEL = 21,
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R4300i_BLEZL = 22, R4300i_BGTZL = 23, R4300i_DADDI = 24, R4300i_DADDIU = 25,
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R4300i_LDL = 26, R4300i_LDR = 27, R4300i_LB = 32, R4300i_LH = 33,
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R4300i_LWL = 34, R4300i_LW = 35, R4300i_LBU = 36, R4300i_LHU = 37,
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R4300i_LWR = 38, R4300i_LWU = 39, R4300i_SB = 40, R4300i_SH = 41,
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R4300i_SWL = 42, R4300i_SW = 43, R4300i_SDL = 44, R4300i_SDR = 45,
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R4300i_SWR = 46, R4300i_CACHE = 47, R4300i_LL = 48, R4300i_LWC1 = 49,
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R4300i_LDC1 = 53, R4300i_LD = 55, R4300i_SC = 56, R4300i_SWC1 = 57,
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R4300i_SDC1 = 61, R4300i_SDC2 = 62, R4300i_SD = 63
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};
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enum R4300iSpecialOpCodes
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{
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R4300i_SPECIAL_SLL = 0, R4300i_SPECIAL_SRL = 2, R4300i_SPECIAL_SRA = 3,
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R4300i_SPECIAL_SLLV = 4, R4300i_SPECIAL_SRLV = 6, R4300i_SPECIAL_SRAV = 7,
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R4300i_SPECIAL_JR = 8, R4300i_SPECIAL_JALR = 9, R4300i_SPECIAL_SYSCALL = 12,
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R4300i_SPECIAL_BREAK = 13, R4300i_SPECIAL_SYNC = 15, R4300i_SPECIAL_MFHI = 16,
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R4300i_SPECIAL_MTHI = 17, R4300i_SPECIAL_MFLO = 18, R4300i_SPECIAL_MTLO = 19,
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R4300i_SPECIAL_DSLLV = 20, R4300i_SPECIAL_DSRLV = 22, R4300i_SPECIAL_DSRAV = 23,
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R4300i_SPECIAL_MULT = 24, R4300i_SPECIAL_MULTU = 25, R4300i_SPECIAL_DIV = 26,
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R4300i_SPECIAL_DIVU = 27, R4300i_SPECIAL_DMULT = 28, R4300i_SPECIAL_DMULTU = 29,
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R4300i_SPECIAL_DDIV = 30, R4300i_SPECIAL_DDIVU = 31, R4300i_SPECIAL_ADD = 32,
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R4300i_SPECIAL_ADDU = 33, R4300i_SPECIAL_SUB = 34, R4300i_SPECIAL_SUBU = 35,
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R4300i_SPECIAL_AND = 36, R4300i_SPECIAL_OR = 37, R4300i_SPECIAL_XOR = 38,
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R4300i_SPECIAL_NOR = 39, R4300i_SPECIAL_SLT = 42, R4300i_SPECIAL_SLTU = 43,
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R4300i_SPECIAL_DADD = 44, R4300i_SPECIAL_DADDU = 45, R4300i_SPECIAL_DSUB = 46,
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R4300i_SPECIAL_DSUBU = 47, R4300i_SPECIAL_TGE = 48, R4300i_SPECIAL_TGEU = 49,
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R4300i_SPECIAL_TLT = 50, R4300i_SPECIAL_TLTU = 51, R4300i_SPECIAL_TEQ = 52,
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R4300i_SPECIAL_TNE = 54, R4300i_SPECIAL_DSLL = 56, R4300i_SPECIAL_DSRL = 58,
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R4300i_SPECIAL_DSRA = 59, R4300i_SPECIAL_DSLL32 = 60, R4300i_SPECIAL_DSRL32 = 62,
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R4300i_SPECIAL_DSRA32 = 63
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};
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enum R4300iRegImmOpCodes
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{
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R4300i_REGIMM_BLTZ = 0, R4300i_REGIMM_BGEZ = 1, R4300i_REGIMM_BLTZL = 2,
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R4300i_REGIMM_BGEZL = 3, R4300i_REGIMM_TGEI = 8, R4300i_REGIMM_TGEIU = 9,
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R4300i_REGIMM_TLTI = 10, R4300i_REGIMM_TLTIU = 11, R4300i_REGIMM_TEQI = 12,
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R4300i_REGIMM_TNEI = 14, R4300i_REGIMM_BLTZAL = 16, R4300i_REGIMM_BGEZAL = 17,
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R4300i_REGIMM_BLTZALL = 18, R4300i_REGIMM_BGEZALL = 19,
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||||
};
|
||||
|
||||
enum R4300iCOP0OpCodes
|
||||
{
|
||||
R4300i_COP0_MF = 0, R4300i_COP0_MT = 4
|
||||
};
|
||||
|
||||
enum R4300iCOP0C0OpCodes
|
||||
{
|
||||
R4300i_COP0_CO_TLBR = 1, R4300i_COP0_CO_TLBWI = 2, R4300i_COP0_CO_TLBWR = 6,
|
||||
R4300i_COP0_CO_TLBP = 8, R4300i_COP0_CO_ERET = 24,
|
||||
};
|
||||
|
||||
enum R4300iCOP1OpCodes
|
||||
{
|
||||
R4300i_COP1_MF = 0, R4300i_COP1_DMF = 1, R4300i_COP1_CF = 2, R4300i_COP1_MT = 4,
|
||||
R4300i_COP1_DMT = 5, R4300i_COP1_CT = 6, R4300i_COP1_BC = 8, R4300i_COP1_S = 16,
|
||||
R4300i_COP1_D = 17, R4300i_COP1_W = 20, R4300i_COP1_L = 21,
|
||||
};
|
||||
|
||||
enum R4300iCOP1BcOpCodes
|
||||
{
|
||||
R4300i_COP1_BC_BCF = 0, R4300i_COP1_BC_BCT = 1, R4300i_COP1_BC_BCFL = 2,
|
||||
R4300i_COP1_BC_BCTL = 3,
|
||||
};
|
||||
|
||||
enum R4300iCOP1FuntOpCodes
|
||||
{
|
||||
R4300i_COP1_FUNCT_ADD = 0, R4300i_COP1_FUNCT_SUB = 1, R4300i_COP1_FUNCT_MUL = 2,
|
||||
R4300i_COP1_FUNCT_DIV = 3, R4300i_COP1_FUNCT_SQRT = 4, R4300i_COP1_FUNCT_ABS = 5,
|
||||
R4300i_COP1_FUNCT_MOV = 6, R4300i_COP1_FUNCT_NEG = 7, R4300i_COP1_FUNCT_ROUND_L = 8,
|
||||
R4300i_COP1_FUNCT_TRUNC_L = 9, R4300i_COP1_FUNCT_CEIL_L = 10, R4300i_COP1_FUNCT_FLOOR_L = 11,
|
||||
R4300i_COP1_FUNCT_ROUND_W = 12, R4300i_COP1_FUNCT_TRUNC_W = 13, R4300i_COP1_FUNCT_CEIL_W = 14,
|
||||
R4300i_COP1_FUNCT_FLOOR_W = 15, R4300i_COP1_FUNCT_CVT_S = 32, R4300i_COP1_FUNCT_CVT_D = 33,
|
||||
R4300i_COP1_FUNCT_CVT_W = 36, R4300i_COP1_FUNCT_CVT_L = 37, R4300i_COP1_FUNCT_C_F = 48,
|
||||
R4300i_COP1_FUNCT_C_UN = 49, R4300i_COP1_FUNCT_C_EQ = 50, R4300i_COP1_FUNCT_C_UEQ = 51,
|
||||
R4300i_COP1_FUNCT_C_OLT = 52, R4300i_COP1_FUNCT_C_ULT = 53, R4300i_COP1_FUNCT_C_OLE = 54,
|
||||
R4300i_COP1_FUNCT_C_ULE = 55, R4300i_COP1_FUNCT_C_SF = 56, R4300i_COP1_FUNCT_C_NGLE = 57,
|
||||
R4300i_COP1_FUNCT_C_SEQ = 58, R4300i_COP1_FUNCT_C_NGL = 59, R4300i_COP1_FUNCT_C_LT = 60,
|
||||
R4300i_COP1_FUNCT_C_NGE = 61, R4300i_COP1_FUNCT_C_LE = 62, R4300i_COP1_FUNCT_C_NGT = 63,
|
||||
};
|
||||
|
|
@ -1,747 +0,0 @@
|
|||
#include "stdafx.h"
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include "OpCode.h"
|
||||
#include <Project64-core/N64System/Mips/Register.h>
|
||||
|
||||
#define FPR_Type(Reg) (Reg) == R4300i_COP1_S ? "S" : (Reg) == R4300i_COP1_D ? "D" :\
|
||||
(Reg) == R4300i_COP1_W ? "W" : "L"
|
||||
|
||||
char CommandName[100];
|
||||
|
||||
static const char * LabelName(uint32_t Address)
|
||||
{
|
||||
static char strLabelName[100];
|
||||
sprintf(strLabelName, "0x%08X", Address);
|
||||
return strLabelName;
|
||||
}
|
||||
|
||||
static const char * R4300iSpecialName(uint32_t OpCode, uint32_t /*PC*/)
|
||||
{
|
||||
OPCODE command;
|
||||
command.Hex = OpCode;
|
||||
|
||||
switch (command.funct)
|
||||
{
|
||||
case R4300i_SPECIAL_SLL:
|
||||
if (command.Hex != 0)
|
||||
{
|
||||
sprintf(CommandName, "SLL\t%s, %s, %d", CRegName::GPR[command.rd],
|
||||
CRegName::GPR[command.rt], command.sa);
|
||||
}
|
||||
else
|
||||
{
|
||||
sprintf(CommandName, "NOP");
|
||||
}
|
||||
break;
|
||||
case R4300i_SPECIAL_SRL:
|
||||
sprintf(CommandName, "SRL\t%s, %s, %d", CRegName::GPR[command.rd], CRegName::GPR[command.rt],
|
||||
command.sa);
|
||||
break;
|
||||
case R4300i_SPECIAL_SRA:
|
||||
sprintf(CommandName, "SRA\t%s, %s, %d", CRegName::GPR[command.rd], CRegName::GPR[command.rt],
|
||||
command.sa);
|
||||
break;
|
||||
case R4300i_SPECIAL_SLLV:
|
||||
sprintf(CommandName, "SLLV\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rt],
|
||||
CRegName::GPR[command.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_SRLV:
|
||||
sprintf(CommandName, "SRLV\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rt],
|
||||
CRegName::GPR[command.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_SRAV:
|
||||
sprintf(CommandName, "SRAV\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rt],
|
||||
CRegName::GPR[command.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_JR:
|
||||
sprintf(CommandName, "JR\t%s", CRegName::GPR[command.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_JALR:
|
||||
sprintf(CommandName, "JALR\t%s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_SYSCALL:
|
||||
sprintf(CommandName, "SYSCALL\t0x%05X", command.code);
|
||||
break;
|
||||
case R4300i_SPECIAL_BREAK:
|
||||
sprintf(CommandName, "BREAK\t0x%05X", command.code);
|
||||
break;
|
||||
case R4300i_SPECIAL_SYNC:
|
||||
sprintf(CommandName, "SYNC");
|
||||
break;
|
||||
case R4300i_SPECIAL_MFHI:
|
||||
sprintf(CommandName, "MFHI\t%s", CRegName::GPR[command.rd]);
|
||||
break;
|
||||
case R4300i_SPECIAL_MTHI:
|
||||
sprintf(CommandName, "MTHI\t%s", CRegName::GPR[command.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_MFLO:
|
||||
sprintf(CommandName, "MFLO\t%s", CRegName::GPR[command.rd]);
|
||||
break;
|
||||
case R4300i_SPECIAL_MTLO:
|
||||
sprintf(CommandName, "MTLO\t%s", CRegName::GPR[command.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSLLV:
|
||||
sprintf(CommandName, "DSLLV\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rt],
|
||||
CRegName::GPR[command.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSRLV:
|
||||
sprintf(CommandName, "DSRLV\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rt],
|
||||
CRegName::GPR[command.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSRAV:
|
||||
sprintf(CommandName, "DSRAV\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rt],
|
||||
CRegName::GPR[command.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_MULT:
|
||||
sprintf(CommandName, "MULT\t%s, %s", CRegName::GPR[command.rs], CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_MULTU:
|
||||
sprintf(CommandName, "MULTU\t%s, %s", CRegName::GPR[command.rs], CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DIV:
|
||||
sprintf(CommandName, "DIV\t%s, %s", CRegName::GPR[command.rs], CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DIVU:
|
||||
sprintf(CommandName, "DIVU\t%s, %s", CRegName::GPR[command.rs], CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DMULT:
|
||||
sprintf(CommandName, "DMULT\t%s, %s", CRegName::GPR[command.rs], CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DMULTU:
|
||||
sprintf(CommandName, "DMULTU\t%s, %s", CRegName::GPR[command.rs], CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DDIV:
|
||||
sprintf(CommandName, "DDIV\t%s, %s", CRegName::GPR[command.rs], CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DDIVU:
|
||||
sprintf(CommandName, "DDIVU\t%s, %s", CRegName::GPR[command.rs], CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_ADD:
|
||||
sprintf(CommandName, "ADD\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rs],
|
||||
CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_ADDU:
|
||||
sprintf(CommandName, "ADDU\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rs],
|
||||
CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_SUB:
|
||||
sprintf(CommandName, "SUB\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rs],
|
||||
CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_SUBU:
|
||||
sprintf(CommandName, "SUBU\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rs],
|
||||
CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_AND:
|
||||
sprintf(CommandName, "AND\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rs],
|
||||
CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_OR:
|
||||
sprintf(CommandName, "OR\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rs],
|
||||
CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_XOR:
|
||||
sprintf(CommandName, "XOR\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rs],
|
||||
CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_NOR:
|
||||
sprintf(CommandName, "NOR\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rs],
|
||||
CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_SLT:
|
||||
sprintf(CommandName, "SLT\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rs],
|
||||
CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_SLTU:
|
||||
sprintf(CommandName, "SLTU\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rs],
|
||||
CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DADD:
|
||||
sprintf(CommandName, "DADD\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rs],
|
||||
CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DADDU:
|
||||
sprintf(CommandName, "DADDU\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rs],
|
||||
CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSUB:
|
||||
sprintf(CommandName, "DSUB\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rs],
|
||||
CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSUBU:
|
||||
sprintf(CommandName, "DSUBU\t%s, %s, %s", CRegName::GPR[command.rd], CRegName::GPR[command.rs],
|
||||
CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_TGE:
|
||||
sprintf(CommandName, "TGE\t%s, %s", CRegName::GPR[command.rs], CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_TGEU:
|
||||
sprintf(CommandName, "TGEU\t%s, %s", CRegName::GPR[command.rs], CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_TLT:
|
||||
sprintf(CommandName, "TLT\t%s, %s", CRegName::GPR[command.rs], CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_TLTU:
|
||||
sprintf(CommandName, "TLTU\t%s, %s", CRegName::GPR[command.rs], CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_TEQ:
|
||||
sprintf(CommandName, "TEQ\t%s, %s", CRegName::GPR[command.rs], CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_TNE:
|
||||
sprintf(CommandName, "TNE\t%s, %s", CRegName::GPR[command.rs], CRegName::GPR[command.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSLL:
|
||||
sprintf(CommandName, "DSLL\t%s, %s, %d", CRegName::GPR[command.rd],
|
||||
CRegName::GPR[command.rt], command.sa);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSRL:
|
||||
sprintf(CommandName, "DSRL\t%s, %s, %d", CRegName::GPR[command.rd], CRegName::GPR[command.rt],
|
||||
command.sa);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSRA:
|
||||
sprintf(CommandName, "DSRA\t%s, %s, %d", CRegName::GPR[command.rd], CRegName::GPR[command.rt],
|
||||
command.sa);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSLL32:
|
||||
sprintf(CommandName, "DSLL32\t%s, %s, %d", CRegName::GPR[command.rd], CRegName::GPR[command.rt], command.sa);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSRL32:
|
||||
sprintf(CommandName, "DSRL32\t%s, %s, %d", CRegName::GPR[command.rd], CRegName::GPR[command.rt], command.sa);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSRA32:
|
||||
sprintf(CommandName, "DSRA32\t%s, %s, %d", CRegName::GPR[command.rd], CRegName::GPR[command.rt], command.sa);
|
||||
break;
|
||||
default:
|
||||
sprintf(CommandName, "UNKNOWN\t%02X %02X %02X %02X",
|
||||
command.Ascii[3], command.Ascii[2], command.Ascii[1], command.Ascii[0]);
|
||||
}
|
||||
return CommandName;
|
||||
}
|
||||
|
||||
static const char * R4300iRegImmName(uint32_t OpCode, uint32_t PC)
|
||||
{
|
||||
OPCODE command;
|
||||
command.Hex = OpCode;
|
||||
|
||||
switch (command.rt)
|
||||
{
|
||||
case R4300i_REGIMM_BLTZ:
|
||||
sprintf(CommandName, "BLTZ\t%s, %s", CRegName::GPR[command.rs], LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
break;
|
||||
case R4300i_REGIMM_BGEZ:
|
||||
if (command.rs == 0)
|
||||
{
|
||||
sprintf(CommandName, "B\t%s", LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
}
|
||||
else
|
||||
{
|
||||
sprintf(CommandName, "BGEZ\t%s, %s", CRegName::GPR[command.rs], LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
}
|
||||
break;
|
||||
case R4300i_REGIMM_BLTZL:
|
||||
sprintf(CommandName, "BLTZL\t%s, %s", CRegName::GPR[command.rs], LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
break;
|
||||
case R4300i_REGIMM_BGEZL:
|
||||
sprintf(CommandName, "BGEZL\t%s, %s", CRegName::GPR[command.rs], LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
break;
|
||||
case R4300i_REGIMM_TGEI:
|
||||
sprintf(CommandName, "TGEI\t%s, 0x%04X", CRegName::GPR[command.rs], command.immediate);
|
||||
break;
|
||||
case R4300i_REGIMM_TGEIU:
|
||||
sprintf(CommandName, "TGEIU\t%s, 0x%04X", CRegName::GPR[command.rs], command.immediate);
|
||||
break;
|
||||
case R4300i_REGIMM_TLTI:
|
||||
sprintf(CommandName, "TLTI\t%s, 0x%04X", CRegName::GPR[command.rs], command.immediate);
|
||||
break;
|
||||
case R4300i_REGIMM_TLTIU:
|
||||
sprintf(CommandName, "TLTIU\t%s, 0x%04X", CRegName::GPR[command.rs], command.immediate);
|
||||
break;
|
||||
case R4300i_REGIMM_TEQI:
|
||||
sprintf(CommandName, "TEQI\t%s, 0x%04X", CRegName::GPR[command.rs], command.immediate);
|
||||
break;
|
||||
case R4300i_REGIMM_TNEI:
|
||||
sprintf(CommandName, "TNEI\t%s, 0x%04X", CRegName::GPR[command.rs], command.immediate);
|
||||
break;
|
||||
case R4300i_REGIMM_BLTZAL:
|
||||
sprintf(CommandName, "BLTZAL\t%s, %s", CRegName::GPR[command.rs], LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
break;
|
||||
case R4300i_REGIMM_BGEZAL:
|
||||
if (command.rs == 0)
|
||||
{
|
||||
sprintf(CommandName, "BAL\t%s", LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
}
|
||||
else
|
||||
{
|
||||
sprintf(CommandName, "BGEZAL\t%s, %s", CRegName::GPR[command.rs], LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
}
|
||||
break;
|
||||
case R4300i_REGIMM_BLTZALL:
|
||||
sprintf(CommandName, "BLTZALL\t%s, %s", CRegName::GPR[command.rs], LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
break;
|
||||
case R4300i_REGIMM_BGEZALL:
|
||||
sprintf(CommandName, "BGEZALL\t%s, %s", CRegName::GPR[command.rs], LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
break;
|
||||
default:
|
||||
sprintf(CommandName, "UNKNOWN\t%02X %02X %02X %02X",
|
||||
command.Ascii[3], command.Ascii[2], command.Ascii[1], command.Ascii[0]);
|
||||
}
|
||||
return CommandName;
|
||||
}
|
||||
|
||||
static const char * R4300iCop1Name(uint32_t OpCode, uint32_t PC)
|
||||
{
|
||||
OPCODE command;
|
||||
command.Hex = OpCode;
|
||||
|
||||
switch (command.fmt)
|
||||
{
|
||||
case R4300i_COP1_MF:
|
||||
sprintf(CommandName, "MFC1\t%s, %s", CRegName::GPR[command.rt], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_DMF:
|
||||
sprintf(CommandName, "DMFC1\t%s, %s", CRegName::GPR[command.rt], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_CF:
|
||||
sprintf(CommandName, "CFC1\t%s, %s", CRegName::GPR[command.rt], CRegName::FPR_Ctrl[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_MT:
|
||||
sprintf(CommandName, "MTC1\t%s, %s", CRegName::GPR[command.rt], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_DMT:
|
||||
sprintf(CommandName, "DMTC1\t%s, %s", CRegName::GPR[command.rt], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_CT:
|
||||
sprintf(CommandName, "CTC1\t%s, %s", CRegName::GPR[command.rt], CRegName::FPR_Ctrl[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_BC:
|
||||
switch (command.ft)
|
||||
{
|
||||
case R4300i_COP1_BC_BCF:
|
||||
sprintf(CommandName, "BC1F\t%s", LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
break;
|
||||
case R4300i_COP1_BC_BCT:
|
||||
sprintf(CommandName, "BC1T\t%s", LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
break;
|
||||
case R4300i_COP1_BC_BCFL:
|
||||
sprintf(CommandName, "BC1FL\t%s", LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
break;
|
||||
case R4300i_COP1_BC_BCTL:
|
||||
sprintf(CommandName, "BC1TL\t%s", LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
break;
|
||||
default:
|
||||
sprintf(CommandName, "UNKNOWN COP1\t%02X %02X %02X %02X",
|
||||
command.Ascii[3], command.Ascii[2], command.Ascii[1], command.Ascii[0]);
|
||||
}
|
||||
break;
|
||||
case R4300i_COP1_S:
|
||||
case R4300i_COP1_D:
|
||||
case R4300i_COP1_W:
|
||||
case R4300i_COP1_L:
|
||||
switch (command.funct)
|
||||
{
|
||||
case R4300i_COP1_FUNCT_ADD:
|
||||
sprintf(CommandName, "ADD.%s\t%s, %s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs],
|
||||
CRegName::FPR[command.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_SUB:
|
||||
sprintf(CommandName, "SUB.%s\t%s, %s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs],
|
||||
CRegName::FPR[command.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_MUL:
|
||||
sprintf(CommandName, "MUL.%s\t%s, %s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs],
|
||||
CRegName::FPR[command.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_DIV:
|
||||
sprintf(CommandName, "DIV.%s\t%s, %s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs],
|
||||
CRegName::FPR[command.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_SQRT:
|
||||
sprintf(CommandName, "SQRT.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_ABS:
|
||||
sprintf(CommandName, "ABS.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_MOV:
|
||||
sprintf(CommandName, "MOV.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_NEG:
|
||||
sprintf(CommandName, "NEG.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_ROUND_L:
|
||||
sprintf(CommandName, "ROUND.L.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_TRUNC_L:
|
||||
sprintf(CommandName, "TRUNC.L.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_CEIL_L:
|
||||
sprintf(CommandName, "CEIL.L.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_FLOOR_L:
|
||||
sprintf(CommandName, "FLOOR.L.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_ROUND_W:
|
||||
sprintf(CommandName, "ROUND.W.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_TRUNC_W:
|
||||
sprintf(CommandName, "TRUNC.W.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_CEIL_W:
|
||||
sprintf(CommandName, "CEIL.W.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_FLOOR_W:
|
||||
sprintf(CommandName, "FLOOR.W.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_CVT_S:
|
||||
sprintf(CommandName, "CVT.S.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_CVT_D:
|
||||
sprintf(CommandName, "CVT.D.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_CVT_W:
|
||||
sprintf(CommandName, "CVT.W.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_CVT_L:
|
||||
sprintf(CommandName, "CVT.L.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fd], CRegName::FPR[command.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_F:
|
||||
sprintf(CommandName, "C.F.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fs], CRegName::FPR[command.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_UN:
|
||||
sprintf(CommandName, "C.UN.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fs], CRegName::FPR[command.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_EQ:
|
||||
sprintf(CommandName, "C.EQ.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fs], CRegName::FPR[command.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_UEQ:
|
||||
sprintf(CommandName, "C.UEQ.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fs], CRegName::FPR[command.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_OLT:
|
||||
sprintf(CommandName, "C.OLT.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fs], CRegName::FPR[command.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_ULT:
|
||||
sprintf(CommandName, "C.ULT.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fs], CRegName::FPR[command.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_OLE:
|
||||
sprintf(CommandName, "C.OLE.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fs], CRegName::FPR[command.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_ULE:
|
||||
sprintf(CommandName, "C.ULE.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fs], CRegName::FPR[command.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_SF:
|
||||
sprintf(CommandName, "C.SF.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fs], CRegName::FPR[command.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_NGLE:
|
||||
sprintf(CommandName, "C.NGLE.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fs], CRegName::FPR[command.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_SEQ:
|
||||
sprintf(CommandName, "C.SEQ.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fs], CRegName::FPR[command.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_NGL:
|
||||
sprintf(CommandName, "C.NGL.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fs], CRegName::FPR[command.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_LT:
|
||||
sprintf(CommandName, "C.LT.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fs], CRegName::FPR[command.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_NGE:
|
||||
sprintf(CommandName, "C.NGE.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fs], CRegName::FPR[command.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_LE:
|
||||
sprintf(CommandName, "C.LE.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fs], CRegName::FPR[command.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_NGT:
|
||||
sprintf(CommandName, "C.NGT.%s\t%s, %s", FPR_Type(command.fmt),
|
||||
CRegName::FPR[command.fs], CRegName::FPR[command.ft]);
|
||||
break;
|
||||
default:
|
||||
sprintf(CommandName, "UNKNOWN COP1\t%02X %02X %02X %02X",
|
||||
command.Ascii[3], command.Ascii[2], command.Ascii[1], command.Ascii[0]);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
sprintf(CommandName, "UNKNOWN COP1\t%02X %02X %02X %02X",
|
||||
command.Ascii[3], command.Ascii[2], command.Ascii[1], command.Ascii[0]);
|
||||
}
|
||||
return CommandName;
|
||||
}
|
||||
|
||||
const char * R4300iOpcodeName(uint32_t OpCode, uint32_t PC)
|
||||
{
|
||||
OPCODE command;
|
||||
command.Hex = OpCode;
|
||||
|
||||
switch (command.op)
|
||||
{
|
||||
case R4300i_SPECIAL:
|
||||
return R4300iSpecialName(OpCode, PC);
|
||||
break;
|
||||
case R4300i_REGIMM:
|
||||
return R4300iRegImmName(OpCode, PC);
|
||||
break;
|
||||
case R4300i_J:
|
||||
sprintf(CommandName, "J\t%s", LabelName((PC & 0xF0000000) + (command.target << 2)));
|
||||
break;
|
||||
case R4300i_JAL:
|
||||
sprintf(CommandName, "JAL\t%s", LabelName((PC & 0xF0000000) + (command.target << 2)));
|
||||
break;
|
||||
case R4300i_BEQ:
|
||||
if (command.rs == 0 && command.rt == 0)
|
||||
{
|
||||
sprintf(CommandName, "B\t%s", LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
}
|
||||
else if (command.rs == 0 || command.rt == 0)
|
||||
{
|
||||
sprintf(CommandName, "BEQZ\t%s, %s", CRegName::GPR[command.rs == 0 ? command.rt : command.rs],
|
||||
LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
}
|
||||
else
|
||||
{
|
||||
sprintf(CommandName, "BEQ\t%s, %s, %s", CRegName::GPR[command.rs], CRegName::GPR[command.rt],
|
||||
LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
}
|
||||
break;
|
||||
case R4300i_BNE:
|
||||
if ((command.rs == 0) ^ (command.rt == 0))
|
||||
{
|
||||
sprintf(CommandName, "BNEZ\t%s, %s", CRegName::GPR[command.rs == 0 ? command.rt : command.rs],
|
||||
LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
}
|
||||
else
|
||||
{
|
||||
sprintf(CommandName, "BNE\t%s, %s, %s", CRegName::GPR[command.rs], CRegName::GPR[command.rt],
|
||||
LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
}
|
||||
break;
|
||||
case R4300i_BLEZ:
|
||||
sprintf(CommandName, "BLEZ\t%s, %s", CRegName::GPR[command.rs], LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
break;
|
||||
case R4300i_BGTZ:
|
||||
sprintf(CommandName, "BGTZ\t%s, %s", CRegName::GPR[command.rs], LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
break;
|
||||
case R4300i_ADDI:
|
||||
sprintf(CommandName, "ADDI\t%s, %s, 0x%04X", CRegName::GPR[command.rt], CRegName::GPR[command.rs], command.immediate);
|
||||
break;
|
||||
case R4300i_ADDIU:
|
||||
// Special case for stack
|
||||
if (command.rt == 29)
|
||||
{
|
||||
short imm = (short)command.immediate;
|
||||
sprintf(CommandName, "ADDIU\t%s, %s, %s0x%02X", CRegName::GPR[command.rt], CRegName::GPR[command.rs], imm < 0 ? "-" : "", abs(imm));
|
||||
}
|
||||
else
|
||||
{
|
||||
sprintf(CommandName, "ADDIU\t%s, %s, 0x%04X", CRegName::GPR[command.rt], CRegName::GPR[command.rs], command.immediate);
|
||||
}
|
||||
break;
|
||||
case R4300i_SLTI:
|
||||
sprintf(CommandName, "SLTI\t%s, %s, 0x%04X", CRegName::GPR[command.rt], CRegName::GPR[command.rs], command.immediate);
|
||||
break;
|
||||
case R4300i_SLTIU:
|
||||
sprintf(CommandName, "SLTIU\t%s, %s, 0x%04X", CRegName::GPR[command.rt], CRegName::GPR[command.rs], command.immediate);
|
||||
break;
|
||||
case R4300i_ANDI:
|
||||
sprintf(CommandName, "ANDI\t%s, %s, 0x%04X", CRegName::GPR[command.rt], CRegName::GPR[command.rs], command.immediate);
|
||||
break;
|
||||
case R4300i_ORI:
|
||||
sprintf(CommandName, "ORI\t%s, %s, 0x%04X", CRegName::GPR[command.rt], CRegName::GPR[command.rs], command.immediate);
|
||||
break;
|
||||
case R4300i_XORI:
|
||||
sprintf(CommandName, "XORI\t%s, %s, 0x%04X", CRegName::GPR[command.rt], CRegName::GPR[command.rs], command.immediate);
|
||||
break;
|
||||
case R4300i_LUI:
|
||||
sprintf(CommandName, "LUI\t%s, 0x%04X", CRegName::GPR[command.rt], command.immediate);
|
||||
break;
|
||||
case R4300i_CP0:
|
||||
switch (command.rs)
|
||||
{
|
||||
case R4300i_COP0_MF:
|
||||
sprintf(CommandName, "MFC0\t%s, %s", CRegName::GPR[command.rt], CRegName::Cop0[command.rd]);
|
||||
break;
|
||||
case R4300i_COP0_MT:
|
||||
sprintf(CommandName, "MTC0\t%s, %s", CRegName::GPR[command.rt], CRegName::Cop0[command.rd]);
|
||||
break;
|
||||
default:
|
||||
if ((command.rs & 0x10) != 0)
|
||||
{
|
||||
switch (command.funct)
|
||||
{
|
||||
case R4300i_COP0_CO_TLBR: sprintf(CommandName, "TLBR"); break;
|
||||
case R4300i_COP0_CO_TLBWI: sprintf(CommandName, "TLBWI"); break;
|
||||
case R4300i_COP0_CO_TLBWR: sprintf(CommandName, "TLBWR"); break;
|
||||
case R4300i_COP0_CO_TLBP: sprintf(CommandName, "TLBP"); break;
|
||||
case R4300i_COP0_CO_ERET: sprintf(CommandName, "ERET"); break;
|
||||
default:
|
||||
sprintf(CommandName, "UNKNOWN\t%02X %02X %02X %02X",
|
||||
command.Ascii[3], command.Ascii[2], command.Ascii[1], command.Ascii[0]);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
sprintf(CommandName, "UNKNOWN\t%02X %02X %02X %02X",
|
||||
command.Ascii[3], command.Ascii[2], command.Ascii[1], command.Ascii[0]);
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case R4300i_CP1:
|
||||
return R4300iCop1Name(OpCode, PC);
|
||||
case R4300i_BEQL:
|
||||
if (command.rs == command.rt)
|
||||
{
|
||||
sprintf(CommandName, "B\t%s", LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
}
|
||||
else if ((command.rs == 0) ^ (command.rt == 0))
|
||||
{
|
||||
sprintf(CommandName, "BEQZL\t%s, %s", CRegName::GPR[command.rs == 0 ? command.rt : command.rs],
|
||||
LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
}
|
||||
else
|
||||
{
|
||||
sprintf(CommandName, "BEQL\t%s, %s, %s", CRegName::GPR[command.rs], CRegName::GPR[command.rt],
|
||||
LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
}
|
||||
break;
|
||||
case R4300i_BNEL:
|
||||
if ((command.rs == 0) ^ (command.rt == 0))
|
||||
{
|
||||
sprintf(CommandName, "BNEZL\t%s, %s", CRegName::GPR[command.rs == 0 ? command.rt : command.rs],
|
||||
LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
}
|
||||
else
|
||||
{
|
||||
sprintf(CommandName, "BNEL\t%s, %s, %s", CRegName::GPR[command.rs], CRegName::GPR[command.rt],
|
||||
LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
}
|
||||
break;
|
||||
case R4300i_BLEZL:
|
||||
sprintf(CommandName, "BLEZL\t%s, %s", CRegName::GPR[command.rs], LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
break;
|
||||
case R4300i_BGTZL:
|
||||
sprintf(CommandName, "BGTZL\t%s, %s", CRegName::GPR[command.rs], LabelName(PC + ((int16_t)command.offset << 2) + 4));
|
||||
break;
|
||||
case R4300i_DADDI:
|
||||
sprintf(CommandName, "DADDI\t%s, %s, 0x%04X", CRegName::GPR[command.rt], CRegName::GPR[command.rs], command.immediate);
|
||||
break;
|
||||
case R4300i_DADDIU:
|
||||
sprintf(CommandName, "DADDIU\t%s, %s, 0x%04X", CRegName::GPR[command.rt], CRegName::GPR[command.rs], command.immediate);
|
||||
break;
|
||||
case R4300i_LDL:
|
||||
sprintf(CommandName, "LDL\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_LDR:
|
||||
sprintf(CommandName, "LDR\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_LB:
|
||||
sprintf(CommandName, "LB\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_LH:
|
||||
sprintf(CommandName, "LH\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_LWL:
|
||||
sprintf(CommandName, "LWL\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_LW:
|
||||
sprintf(CommandName, "LW\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_LBU:
|
||||
sprintf(CommandName, "LBU\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_LHU:
|
||||
sprintf(CommandName, "LHU\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_LWR:
|
||||
sprintf(CommandName, "LWR\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_LWU:
|
||||
sprintf(CommandName, "LWU\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_SB:
|
||||
sprintf(CommandName, "SB\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_SH:
|
||||
sprintf(CommandName, "SH\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_SWL:
|
||||
sprintf(CommandName, "SWL\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_SW:
|
||||
sprintf(CommandName, "SW\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_SDL:
|
||||
sprintf(CommandName, "SDL\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_SDR:
|
||||
sprintf(CommandName, "SDR\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_SWR:
|
||||
sprintf(CommandName, "SWR\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_CACHE:
|
||||
sprintf(CommandName, "CACHE\t%d, 0x%04X (%s)", command.rt, command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_LL:
|
||||
sprintf(CommandName, "LL\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_LWC1:
|
||||
sprintf(CommandName, "LWC1\t%s, 0x%04X (%s)", CRegName::FPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_LDC1:
|
||||
sprintf(CommandName, "LDC1\t%s, 0x%04X (%s)", CRegName::FPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_LD:
|
||||
sprintf(CommandName, "LD\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_SC:
|
||||
sprintf(CommandName, "SC\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_SWC1:
|
||||
sprintf(CommandName, "SWC1\t%s, 0x%04X (%s)", CRegName::FPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_SDC1:
|
||||
sprintf(CommandName, "SDC1\t%s, 0x%04X (%s)", CRegName::FPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
case R4300i_SD:
|
||||
sprintf(CommandName, "SD\t%s, 0x%04X (%s)", CRegName::GPR[command.rt], command.offset, CRegName::GPR[command.base]);
|
||||
break;
|
||||
default:
|
||||
sprintf(CommandName, "UNKNOWN\t%02X %02X %02X %02X",
|
||||
command.Ascii[3], command.Ascii[2], command.Ascii[1], command.Ascii[0]);
|
||||
}
|
||||
|
||||
return CommandName;
|
||||
}
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
#pragma once
|
||||
|
||||
const char * R4300iOpcodeName(uint32_t OpCode, uint32_t PC);
|
||||
|
|
@ -0,0 +1,860 @@
|
|||
#include "stdafx.h"
|
||||
#include <Project64-core/N64System/Mips/Register.h>
|
||||
#include "R4300iInstruction.h"
|
||||
|
||||
R4300iInstruction::R4300iInstruction(uint32_t Address, uint32_t Instruction) :
|
||||
m_Address(Address)
|
||||
{
|
||||
m_Name[0] = '\0';
|
||||
m_Param[0] = '\0';
|
||||
m_Instruction.Value = Instruction;
|
||||
}
|
||||
|
||||
const char * R4300iInstruction::Name()
|
||||
{
|
||||
if (m_Name[0] == '\0')
|
||||
{
|
||||
DecodeName();
|
||||
}
|
||||
return m_Name;
|
||||
}
|
||||
|
||||
const char * R4300iInstruction::Param()
|
||||
{
|
||||
if (m_Param[0] == '\0')
|
||||
{
|
||||
DecodeName();
|
||||
}
|
||||
return m_Param;
|
||||
}
|
||||
|
||||
std::string R4300iInstruction::NameAndParam()
|
||||
{
|
||||
return stdstr_f("%s %s", Name(), Param());
|
||||
}
|
||||
|
||||
const char * R4300iInstruction::FPR_Type(uint32_t COP1OpCode)
|
||||
{
|
||||
if (COP1OpCode == R4300i_COP1_S) { return "S"; };
|
||||
if (COP1OpCode == R4300i_COP1_D) { return "D"; };
|
||||
if (COP1OpCode == R4300i_COP1_W) { return "W"; };
|
||||
if (COP1OpCode == R4300i_COP1_L) { return "L"; };
|
||||
return "?";
|
||||
}
|
||||
|
||||
void R4300iInstruction::DecodeName(void)
|
||||
{
|
||||
switch (m_Instruction.op)
|
||||
{
|
||||
case R4300i_SPECIAL:
|
||||
DecodeSpecialName();
|
||||
break;
|
||||
case R4300i_REGIMM:
|
||||
DecodeRegImmName();
|
||||
break;
|
||||
case R4300i_J:
|
||||
strcpy(m_Name, "J");
|
||||
sprintf(m_Param, "0x%08X", (m_Address & 0xF0000000) + (m_Instruction.target << 2));
|
||||
break;
|
||||
case R4300i_JAL:
|
||||
strcpy(m_Name, "JAL");
|
||||
sprintf(m_Param, "0x%08X", (m_Address & 0xF0000000) + (m_Instruction.target << 2));
|
||||
break;
|
||||
case R4300i_BEQ:
|
||||
if (m_Instruction.rs == 0 && m_Instruction.rt == 0)
|
||||
{
|
||||
strcpy(m_Name, "B");
|
||||
sprintf(m_Param, "0x%08X", m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
}
|
||||
else if (m_Instruction.rs == 0 || m_Instruction.rt == 0)
|
||||
{
|
||||
strcpy(m_Name, "BEQZ");
|
||||
sprintf(m_Param, "%s, 0x%08X", CRegName::GPR[m_Instruction.rs == 0 ? m_Instruction.rt : m_Instruction.rs], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
strcpy(m_Name, "BEQ");
|
||||
sprintf(m_Param, "%s, %s, 0x%08X", CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
}
|
||||
break;
|
||||
case R4300i_BNE:
|
||||
if ((m_Instruction.rs == 0) ^ (m_Instruction.rt == 0))
|
||||
{
|
||||
strcpy(m_Name, "BNEZ");
|
||||
sprintf(m_Param, "%s, 0x%08X", CRegName::GPR[m_Instruction.rs == 0 ? m_Instruction.rt : m_Instruction.rs], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
strcpy(m_Name, "BNE");
|
||||
sprintf(m_Param, "%s, %s, 0x%08X", CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
}
|
||||
break;
|
||||
case R4300i_BLEZ:
|
||||
strcpy(m_Name, "BLEZ");
|
||||
sprintf(m_Param, "%s, 0x%08X", CRegName::GPR[m_Instruction.rs], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
break;
|
||||
case R4300i_BGTZ:
|
||||
strcpy(m_Name, "BGTZ");
|
||||
sprintf(m_Param, "%s, 0x%08X", CRegName::GPR[m_Instruction.rs], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
break;
|
||||
case R4300i_ADDI:
|
||||
strcpy(m_Name, "ADDI");
|
||||
sprintf(m_Param, "%s, %s, 0x%04X", CRegName::GPR[m_Instruction.rt], CRegName::GPR[m_Instruction.rs], m_Instruction.immediate);
|
||||
break;
|
||||
case R4300i_ADDIU:
|
||||
// Special case for stack
|
||||
strcpy(m_Name, "ADDIU");
|
||||
if (m_Instruction.rt == 29)
|
||||
{
|
||||
short imm = (short)m_Instruction.immediate;
|
||||
sprintf(m_Param, "%s, %s, %s0x%02X", CRegName::GPR[m_Instruction.rt], CRegName::GPR[m_Instruction.rs], imm < 0 ? "-" : "", abs(imm));
|
||||
}
|
||||
else
|
||||
{
|
||||
sprintf(m_Param, "%s, %s, 0x%04X", CRegName::GPR[m_Instruction.rt], CRegName::GPR[m_Instruction.rs], m_Instruction.immediate);
|
||||
}
|
||||
break;
|
||||
case R4300i_SLTI:
|
||||
strcpy(m_Name, "SLTI");
|
||||
sprintf(m_Param, "%s, %s, 0x%04X", CRegName::GPR[m_Instruction.rt], CRegName::GPR[m_Instruction.rs], m_Instruction.immediate);
|
||||
break;
|
||||
case R4300i_SLTIU:
|
||||
strcpy(m_Name, "SLTIU");
|
||||
sprintf(m_Param, "%s, %s, 0x%04X", CRegName::GPR[m_Instruction.rt], CRegName::GPR[m_Instruction.rs], m_Instruction.immediate);
|
||||
break;
|
||||
case R4300i_ANDI:
|
||||
strcpy(m_Name, "ANDI");
|
||||
sprintf(m_Param, "%s, %s, 0x%04X", CRegName::GPR[m_Instruction.rt], CRegName::GPR[m_Instruction.rs], m_Instruction.immediate);
|
||||
break;
|
||||
case R4300i_ORI:
|
||||
strcpy(m_Name, "ORI");
|
||||
sprintf(m_Param, "%s, %s, 0x%04X", CRegName::GPR[m_Instruction.rt], CRegName::GPR[m_Instruction.rs], m_Instruction.immediate);
|
||||
break;
|
||||
case R4300i_XORI:
|
||||
strcpy(m_Name, "XORI");
|
||||
sprintf(m_Param, "%s, %s, 0x%04X", CRegName::GPR[m_Instruction.rt], CRegName::GPR[m_Instruction.rs], m_Instruction.immediate);
|
||||
break;
|
||||
case R4300i_LUI:
|
||||
strcpy(m_Name, "LUI");
|
||||
sprintf(m_Param, "%s, 0x%04X", CRegName::GPR[m_Instruction.rt], m_Instruction.immediate);
|
||||
break;
|
||||
case R4300i_CP0:
|
||||
switch (m_Instruction.rs)
|
||||
{
|
||||
case R4300i_COP0_MF:
|
||||
strcpy(m_Name, "MFC0");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rt], CRegName::Cop0[m_Instruction.rd]);
|
||||
break;
|
||||
case R4300i_COP1_DMF:
|
||||
strcpy(m_Name, "DMFC0");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rt], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP0_MT:
|
||||
strcpy(m_Name, "MTC0");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rt], CRegName::Cop0[m_Instruction.rd]);
|
||||
break;
|
||||
case R4300i_COP0_DMT:
|
||||
strcpy(m_Name, "DMTC0");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rt], CRegName::Cop0[m_Instruction.rd]);
|
||||
break;
|
||||
default:
|
||||
if ((m_Instruction.rs & 0x10) != 0)
|
||||
{
|
||||
switch (m_Instruction.funct)
|
||||
{
|
||||
case R4300i_COP0_CO_TLBR: strcpy(m_Name, "TLBR"); break;
|
||||
case R4300i_COP0_CO_TLBWI: strcpy(m_Name, "TLBWI"); break;
|
||||
case R4300i_COP0_CO_TLBWR: strcpy(m_Name, "TLBWR"); break;
|
||||
case R4300i_COP0_CO_TLBP: strcpy(m_Name, "TLBP"); break;
|
||||
case R4300i_COP0_CO_ERET: strcpy(m_Name, "ERET"); break;
|
||||
default:
|
||||
strcpy(m_Name, "UNKNOWN");
|
||||
sprintf(m_Param, "0x%08X", m_Instruction.Value);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
strcpy(m_Name, "UNKNOWN");
|
||||
sprintf(m_Param, "0x%08X", m_Instruction.Value);
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case R4300i_CP1:
|
||||
DecodeCop1Name();
|
||||
break;
|
||||
case R4300i_BEQL:
|
||||
if (m_Instruction.rs == m_Instruction.rt)
|
||||
{
|
||||
strcpy(m_Name, "B");
|
||||
sprintf(m_Param, "0x%08X", m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
}
|
||||
else if ((m_Instruction.rs == 0) ^ (m_Instruction.rt == 0))
|
||||
{
|
||||
strcpy(m_Name, "BEQZL");
|
||||
sprintf(m_Param, "%s, 0x%08X", CRegName::GPR[m_Instruction.rs == 0 ? m_Instruction.rt : m_Instruction.rs], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
strcpy(m_Name, "BEQL");
|
||||
sprintf(m_Param, "%s, %s, 0x%08X", CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
}
|
||||
break;
|
||||
case R4300i_BNEL:
|
||||
if ((m_Instruction.rs == 0) ^ (m_Instruction.rt == 0))
|
||||
{
|
||||
strcpy(m_Name, "BNEZL");
|
||||
sprintf(m_Param, "%s, 0x%08X", CRegName::GPR[m_Instruction.rs == 0 ? m_Instruction.rt : m_Instruction.rs], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
strcpy(m_Name, "BNEL");
|
||||
sprintf(m_Param, "%s, %s, 0x%08X", CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
}
|
||||
break;
|
||||
case R4300i_BLEZL:
|
||||
strcpy(m_Name, "BLEZL");
|
||||
sprintf(m_Param, "%s, 0x%08X", CRegName::GPR[m_Instruction.rs], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
break;
|
||||
case R4300i_BGTZL:
|
||||
strcpy(m_Name, "BGTZL");
|
||||
sprintf(m_Param, "%s, 0x%08X", CRegName::GPR[m_Instruction.rs], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
break;
|
||||
case R4300i_DADDI:
|
||||
strcpy(m_Name, "DADDI");
|
||||
sprintf(m_Param, "%s, %s, 0x%04X", CRegName::GPR[m_Instruction.rt], CRegName::GPR[m_Instruction.rs], m_Instruction.immediate);
|
||||
break;
|
||||
case R4300i_DADDIU:
|
||||
strcpy(m_Name, "DADDIU");
|
||||
sprintf(m_Param, "%s, %s, 0x%04X", CRegName::GPR[m_Instruction.rt], CRegName::GPR[m_Instruction.rs], m_Instruction.immediate);
|
||||
break;
|
||||
case R4300i_LDL:
|
||||
strcpy(m_Name, "LDL");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_LDR:
|
||||
strcpy(m_Name, "LDR");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_LB:
|
||||
strcpy(m_Name, "LB");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_LH:
|
||||
strcpy(m_Name, "LH");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_LWL:
|
||||
strcpy(m_Name, "LWL");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_LW:
|
||||
strcpy(m_Name, "LW");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_LBU:
|
||||
strcpy(m_Name, "LBU");
|
||||
sprintf(m_Param, "t%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_LHU:
|
||||
strcpy(m_Name, "LHU");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_LWR:
|
||||
strcpy(m_Name, "LWR");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_LWU:
|
||||
strcpy(m_Name, "LWU");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_SB:
|
||||
strcpy(m_Name, "SB");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_SH:
|
||||
strcpy(m_Name, "SH");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_SWL:
|
||||
strcpy(m_Name, "SWL");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_SW:
|
||||
strcpy(m_Name, "SW");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_SDL:
|
||||
strcpy(m_Name, "SDL");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_SDR:
|
||||
strcpy(m_Name, "SDR");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_SWR:
|
||||
strcpy(m_Name, "SWR");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_CACHE:
|
||||
strcpy(m_Name, "CACHE");
|
||||
sprintf(m_Param, "%d, 0x%04X (%s)", m_Instruction.rt, m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_LL:
|
||||
strcpy(m_Name, "LL");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_LWC1:
|
||||
strcpy(m_Name, "LWC1");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::FPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_LDC1:
|
||||
strcpy(m_Name, "LDC1");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::FPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_LD:
|
||||
strcpy(m_Name, "LD");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_SC:
|
||||
strcpy(m_Name, "SC");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_SWC1:
|
||||
strcpy(m_Name, "SWC1");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::FPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_SDC1:
|
||||
strcpy(m_Name, "SDC1");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::FPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
case R4300i_SD:
|
||||
strcpy(m_Name, "SD");
|
||||
sprintf(m_Param, "%s, 0x%04X (%s)", CRegName::GPR[m_Instruction.rt], m_Instruction.offset, CRegName::GPR[m_Instruction.base]);
|
||||
break;
|
||||
default:
|
||||
strcpy(m_Name, "UNKNOWN");
|
||||
sprintf(m_Param, "0x%08X", m_Instruction.Value);
|
||||
}
|
||||
}
|
||||
|
||||
void R4300iInstruction::DecodeSpecialName(void)
|
||||
{
|
||||
switch (m_Instruction.funct)
|
||||
{
|
||||
case R4300i_SPECIAL_SLL:
|
||||
if (m_Instruction.Value != 0)
|
||||
{
|
||||
strcpy(m_Name, "SLL");
|
||||
sprintf(m_Param, "SLL\t%s, %s, %d", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rt], m_Instruction.sa);
|
||||
}
|
||||
else
|
||||
{
|
||||
strcpy(m_Name, "NOP");
|
||||
}
|
||||
break;
|
||||
case R4300i_SPECIAL_SRL:
|
||||
strcpy(m_Name, "SRL");
|
||||
sprintf(m_Param, "%s, %s, %d", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rt], m_Instruction.sa);
|
||||
break;
|
||||
case R4300i_SPECIAL_SRA:
|
||||
strcpy(m_Name, "SRA");
|
||||
sprintf(m_Param, "%s, %s, %d", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rt], m_Instruction.sa);
|
||||
break;
|
||||
case R4300i_SPECIAL_SLLV:
|
||||
strcpy(m_Name, "SLLV");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rt], CRegName::GPR[m_Instruction.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_SRLV:
|
||||
strcpy(m_Name, "SRLV");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rt], CRegName::GPR[m_Instruction.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_SRAV:
|
||||
strcpy(m_Name, "SRAV");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rt], CRegName::GPR[m_Instruction.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_JR:
|
||||
strcpy(m_Name, "JR");
|
||||
sprintf(m_Param, "%s", CRegName::GPR[m_Instruction.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_JALR:
|
||||
strcpy(m_Name, "JALR");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_SYSCALL:
|
||||
strcpy(m_Name, "SYSCALL");
|
||||
sprintf(m_Param, "0x%05X", m_Instruction.code);
|
||||
break;
|
||||
case R4300i_SPECIAL_BREAK:
|
||||
strcpy(m_Name, "BREAK");
|
||||
sprintf(m_Param, "0x%05X", m_Instruction.code);
|
||||
break;
|
||||
case R4300i_SPECIAL_SYNC:
|
||||
strcpy(m_Name, "SYNC");
|
||||
strcpy(m_Param, "");
|
||||
break;
|
||||
case R4300i_SPECIAL_MFHI:
|
||||
strcpy(m_Name, "MFHI");
|
||||
sprintf(m_Param, "%s", CRegName::GPR[m_Instruction.rd]);
|
||||
break;
|
||||
case R4300i_SPECIAL_MTHI:
|
||||
strcpy(m_Name, "MTHI");
|
||||
sprintf(m_Param, "%s", CRegName::GPR[m_Instruction.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_MFLO:
|
||||
strcpy(m_Name, "MFLO");
|
||||
sprintf(m_Param, "%s", CRegName::GPR[m_Instruction.rd]);
|
||||
break;
|
||||
case R4300i_SPECIAL_MTLO:
|
||||
strcpy(m_Name, "MTLO");
|
||||
sprintf(m_Param, "%s", CRegName::GPR[m_Instruction.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSLLV:
|
||||
strcpy(m_Name, "DSLLV");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rt], CRegName::GPR[m_Instruction.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSRLV:
|
||||
strcpy(m_Name, "DSRLV");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rt], CRegName::GPR[m_Instruction.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSRAV:
|
||||
strcpy(m_Name, "DSRAV");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rt], CRegName::GPR[m_Instruction.rs]);
|
||||
break;
|
||||
case R4300i_SPECIAL_MULT:
|
||||
strcpy(m_Name, "MULT");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_MULTU:
|
||||
strcpy(m_Name, "MULTU");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DIV:
|
||||
strcpy(m_Name, "DIV");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DIVU:
|
||||
strcpy(m_Name, "DIVU");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DMULT:
|
||||
strcpy(m_Name, "DMULT");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DMULTU:
|
||||
strcpy(m_Name, "DMULTU");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DDIV:
|
||||
strcpy(m_Name, "DIVU");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DDIVU:
|
||||
strcpy(m_Name, "DDIVU");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_ADD:
|
||||
strcpy(m_Name, "ADD");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_ADDU:
|
||||
strcpy(m_Name, "ADDU");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_SUB:
|
||||
strcpy(m_Name, "SUB");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_SUBU:
|
||||
strcpy(m_Name, "SUBU");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_AND:
|
||||
strcpy(m_Name, "AND");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_OR:
|
||||
strcpy(m_Name, "OR");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_XOR:
|
||||
strcpy(m_Name, "XOR");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_NOR:
|
||||
strcpy(m_Name, "NOR");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_SLT:
|
||||
strcpy(m_Name, "SLT");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_SLTU:
|
||||
strcpy(m_Name, "SLTU");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DADD:
|
||||
strcpy(m_Name, "DADD");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DADDU:
|
||||
strcpy(m_Name, "DADDU");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSUB:
|
||||
strcpy(m_Name, "DSUB");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSUBU:
|
||||
strcpy(m_Name, "DSUBU");
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_TGE:
|
||||
strcpy(m_Name, "TGE");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_TGEU:
|
||||
strcpy(m_Name, "TGEU");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_TLT:
|
||||
strcpy(m_Name, "TLT");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_TLTU:
|
||||
strcpy(m_Name, "TLTU");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_TEQ:
|
||||
strcpy(m_Name, "TEQ");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_TNE:
|
||||
strcpy(m_Name, "TNE");
|
||||
sprintf(m_Param, "t%s, %s", CRegName::GPR[m_Instruction.rs], CRegName::GPR[m_Instruction.rt]);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSLL:
|
||||
strcpy(m_Name, "DSLL");
|
||||
sprintf(m_Param, "%s, %s, %d", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rt], m_Instruction.sa);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSRL:
|
||||
strcpy(m_Name, "DSRL");
|
||||
sprintf(m_Param, "%s, %s, %d", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rt], m_Instruction.sa);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSRA:
|
||||
strcpy(m_Name, "DSRA");
|
||||
sprintf(m_Param, "%s, %s, %d", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rt], m_Instruction.sa);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSLL32:
|
||||
strcpy(m_Name, "DSLL32");
|
||||
sprintf(m_Param, "%s, %s, %d", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rt], m_Instruction.sa);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSRL32:
|
||||
strcpy(m_Name, "DSRL32");
|
||||
sprintf(m_Param, "%s, %s, %d", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rt], m_Instruction.sa);
|
||||
break;
|
||||
case R4300i_SPECIAL_DSRA32:
|
||||
strcpy(m_Name, "DSRA32");
|
||||
sprintf(m_Param, "%s, %s, %d", CRegName::GPR[m_Instruction.rd], CRegName::GPR[m_Instruction.rt], m_Instruction.sa);
|
||||
break;
|
||||
default:
|
||||
strcpy(m_Name, "UNKNOWN");
|
||||
sprintf(m_Param, "0x%08X", m_Instruction.Value);
|
||||
}
|
||||
}
|
||||
|
||||
void R4300iInstruction::DecodeRegImmName(void)
|
||||
{
|
||||
switch (m_Instruction.rt)
|
||||
{
|
||||
case R4300i_REGIMM_BLTZ:
|
||||
strcpy(m_Name, "BLTZ");
|
||||
sprintf(m_Param, "%s, 0x%08X", CRegName::GPR[m_Instruction.rs], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
break;
|
||||
case R4300i_REGIMM_BGEZ:
|
||||
if (m_Instruction.rs == 0)
|
||||
{
|
||||
strcpy(m_Name, "B");
|
||||
sprintf(m_Param, "0x%08X", m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
strcpy(m_Name, "BGEZ");
|
||||
sprintf(m_Param, "%s, 0x%08X", CRegName::GPR[m_Instruction.rs], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
}
|
||||
break;
|
||||
case R4300i_REGIMM_BLTZL:
|
||||
strcpy(m_Name, "BLTZL");
|
||||
sprintf(m_Param, "%s, 0x%08X", CRegName::GPR[m_Instruction.rs], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
break;
|
||||
case R4300i_REGIMM_BGEZL:
|
||||
strcpy(m_Name, "BGEZL");
|
||||
sprintf(m_Param, "%s, 0x%08X", CRegName::GPR[m_Instruction.rs], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
break;
|
||||
case R4300i_REGIMM_TGEI:
|
||||
strcpy(m_Name, "TGEI");
|
||||
sprintf(m_Param, "%s, 0x%04X", CRegName::GPR[m_Instruction.rs], m_Instruction.immediate);
|
||||
break;
|
||||
case R4300i_REGIMM_TGEIU:
|
||||
strcpy(m_Name, "TGEIU");
|
||||
sprintf(m_Param, "%s, 0x%04X", CRegName::GPR[m_Instruction.rs], m_Instruction.immediate);
|
||||
break;
|
||||
case R4300i_REGIMM_TLTI:
|
||||
strcpy(m_Name, "TLTI");
|
||||
sprintf(m_Param, "%s, 0x%04X", CRegName::GPR[m_Instruction.rs], m_Instruction.immediate);
|
||||
break;
|
||||
case R4300i_REGIMM_TLTIU:
|
||||
strcpy(m_Name, "TLTIU");
|
||||
sprintf(m_Param, "%s, 0x%04X", CRegName::GPR[m_Instruction.rs], m_Instruction.immediate);
|
||||
break;
|
||||
case R4300i_REGIMM_TEQI:
|
||||
strcpy(m_Name, "TEQI");
|
||||
sprintf(m_Param, "%s, 0x%04X", CRegName::GPR[m_Instruction.rs], m_Instruction.immediate);
|
||||
break;
|
||||
case R4300i_REGIMM_TNEI:
|
||||
strcpy(m_Name, "TNEI");
|
||||
sprintf(m_Param, "%s, 0x%04X", CRegName::GPR[m_Instruction.rs], m_Instruction.immediate);
|
||||
break;
|
||||
case R4300i_REGIMM_BLTZAL:
|
||||
strcpy(m_Name, "BLTZAL");
|
||||
sprintf(m_Param, "%s, 0x%08X", CRegName::GPR[m_Instruction.rs], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
break;
|
||||
case R4300i_REGIMM_BGEZAL:
|
||||
if (m_Instruction.rs == 0)
|
||||
{
|
||||
strcpy(m_Name, "BAL");
|
||||
sprintf(m_Param, "0x%08X", m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
strcpy(m_Name, "BGEZAL");
|
||||
sprintf(m_Param, "%s, 0x%08X", CRegName::GPR[m_Instruction.rs], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
}
|
||||
break;
|
||||
case R4300i_REGIMM_BLTZALL:
|
||||
strcpy(m_Name, "BLTZALL");
|
||||
sprintf(m_Param, "%s, 0x%08X", CRegName::GPR[m_Instruction.rs], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
break;
|
||||
case R4300i_REGIMM_BGEZALL:
|
||||
strcpy(m_Name, "BGEZALL");
|
||||
sprintf(m_Param, "%s, 0x%08X", CRegName::GPR[m_Instruction.rs], m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
break;
|
||||
default:
|
||||
strcpy(m_Name, "UNKNOWN");
|
||||
sprintf(m_Param, "0x%08X", m_Instruction.Value);
|
||||
}
|
||||
}
|
||||
|
||||
void R4300iInstruction::DecodeCop1Name(void)
|
||||
{
|
||||
switch (m_Instruction.fmt)
|
||||
{
|
||||
case R4300i_COP1_MF:
|
||||
strcpy(m_Name, "MFC1");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rt], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_DMF:
|
||||
strcpy(m_Name, "DMFC1");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rt], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_CF:
|
||||
strcpy(m_Name, "CFC1");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rt], CRegName::FPR_Ctrl[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_MT:
|
||||
strcpy(m_Name, "MTC1");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rt], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_DMT:
|
||||
strcpy(m_Name, "DMTC1");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rt], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_CT:
|
||||
strcpy(m_Name, "CTC1");
|
||||
sprintf(m_Param, "%s, %s", CRegName::GPR[m_Instruction.rt], CRegName::FPR_Ctrl[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_BC:
|
||||
switch (m_Instruction.ft)
|
||||
{
|
||||
case R4300i_COP1_BC_BCF:
|
||||
strcpy(m_Name, "BC1F");
|
||||
sprintf(m_Param, "0x%08X", m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
break;
|
||||
case R4300i_COP1_BC_BCT:
|
||||
strcpy(m_Name, "BC1T");
|
||||
sprintf(m_Param, "0x%08X", m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
break;
|
||||
case R4300i_COP1_BC_BCFL:
|
||||
strcpy(m_Name, "BC1FL");
|
||||
sprintf(m_Param, "0x%08X", m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
break;
|
||||
case R4300i_COP1_BC_BCTL:
|
||||
strcpy(m_Name, "BC1TL");
|
||||
sprintf(m_Param, "0x%08X", m_Address + ((int16_t)m_Instruction.offset << 2) + 4);
|
||||
break;
|
||||
default:
|
||||
strcpy(m_Name, "UNKNOWN COP1");
|
||||
sprintf(m_Param, "0x%08X", m_Instruction.Value);
|
||||
}
|
||||
break;
|
||||
case R4300i_COP1_S:
|
||||
case R4300i_COP1_D:
|
||||
case R4300i_COP1_W:
|
||||
case R4300i_COP1_L:
|
||||
switch (m_Instruction.funct)
|
||||
{
|
||||
case R4300i_COP1_FUNCT_ADD:
|
||||
sprintf(m_Name, "ADD.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_SUB:
|
||||
sprintf(m_Name, "SUB.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_MUL:
|
||||
sprintf(m_Name, "MUL.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_DIV:
|
||||
sprintf(m_Name, "DIV.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_SQRT:
|
||||
sprintf(m_Name, "SQRT.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_ABS:
|
||||
sprintf(m_Name, "ABS.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_MOV:
|
||||
sprintf(m_Name, "MOV.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_NEG:
|
||||
sprintf(m_Name, "NEG.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_ROUND_L:
|
||||
sprintf(m_Name, "ROUND.L.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_TRUNC_L:
|
||||
sprintf(m_Name, "TRUNC.L.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_CEIL_L:
|
||||
sprintf(m_Name, "CEIL.L.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_FLOOR_L:
|
||||
sprintf(m_Name, "FLOOR.L.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_ROUND_W:
|
||||
sprintf(m_Name, "ROUND.W.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_TRUNC_W:
|
||||
sprintf(m_Name, "TRUNC.W.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "t%s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_CEIL_W:
|
||||
sprintf(m_Name, "CEIL.W.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_FLOOR_W:
|
||||
sprintf(m_Name, "FLOOR.W.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_CVT_S:
|
||||
sprintf(m_Name, "CVT.S.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_CVT_D:
|
||||
sprintf(m_Name, "CVT.D.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_CVT_W:
|
||||
sprintf(m_Name, "CVT.W.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_CVT_L:
|
||||
sprintf(m_Name, "CVT.L.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fd], CRegName::FPR[m_Instruction.fs]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_F:
|
||||
sprintf(m_Name, "C.F.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_UN:
|
||||
sprintf(m_Name, "C.UN.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_EQ:
|
||||
sprintf(m_Name, "C.EQ.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_UEQ:
|
||||
sprintf(m_Name, "C.UEQ.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_OLT:
|
||||
sprintf(m_Name, "C.OLT.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_ULT:
|
||||
sprintf(m_Name, "C.ULT.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_OLE:
|
||||
sprintf(m_Name, "C.OLE.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_ULE:
|
||||
sprintf(m_Name, "C.ULE.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_SF:
|
||||
sprintf(m_Name, "C.SF.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_NGLE:
|
||||
sprintf(m_Name, "C.NGLE.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_SEQ:
|
||||
sprintf(m_Name, "C.SEQ.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_NGL:
|
||||
sprintf(m_Name, "C.NGL.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_LT:
|
||||
sprintf(m_Name, "C.LT.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_NGE:
|
||||
sprintf(m_Name, "C.NGE.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_LE:
|
||||
sprintf(m_Name, "C.LE.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
case R4300i_COP1_FUNCT_C_NGT:
|
||||
sprintf(m_Name, "C.NGT.%s", FPR_Type(m_Instruction.fmt));
|
||||
sprintf(m_Param, "%s, %s", CRegName::FPR[m_Instruction.fs], CRegName::FPR[m_Instruction.ft]);
|
||||
break;
|
||||
default:
|
||||
strcpy(m_Name, "UNKNOWN COP1");
|
||||
sprintf(m_Param, "0x%08X", m_Instruction.Value);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
strcpy(m_Name, "UNKNOWN COP1");
|
||||
sprintf(m_Param, "0x%08X", m_Instruction.Value);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
#pragma once
|
||||
#include "R4300iOpcode.h"
|
||||
#include <string>
|
||||
|
||||
class R4300iInstruction
|
||||
{
|
||||
public:
|
||||
R4300iInstruction(uint32_t Address, uint32_t Instruction);
|
||||
|
||||
const char * Name();
|
||||
const char * Param();
|
||||
std::string NameAndParam();
|
||||
|
||||
private:
|
||||
R4300iInstruction(void);
|
||||
R4300iInstruction(const R4300iInstruction&);
|
||||
R4300iInstruction& operator=(const R4300iInstruction&);
|
||||
|
||||
static const char * FPR_Type(uint32_t COP1OpCode);
|
||||
|
||||
void DecodeName(void);
|
||||
void DecodeSpecialName(void);
|
||||
void DecodeRegImmName(void);
|
||||
void DecodeCop1Name(void);
|
||||
|
||||
uint32_t m_Address;
|
||||
R4300iOpcode m_Instruction;
|
||||
char m_Name[40];
|
||||
char m_Param[200];
|
||||
};
|
||||
|
|
@ -0,0 +1,269 @@
|
|||
#pragma once
|
||||
#include <stdint.h>
|
||||
|
||||
#pragma warning(push)
|
||||
#pragma warning(disable : 4201) // warning C4201: nonstandard extension used : nameless struct/union
|
||||
|
||||
union R4300iOpcode
|
||||
{
|
||||
uint32_t Value;
|
||||
|
||||
struct
|
||||
{
|
||||
unsigned offset : 16;
|
||||
unsigned rt : 5;
|
||||
unsigned rs : 5;
|
||||
unsigned op : 6;
|
||||
};
|
||||
|
||||
struct
|
||||
{
|
||||
unsigned immediate : 16;
|
||||
unsigned : 5;
|
||||
unsigned base : 5;
|
||||
unsigned : 6;
|
||||
};
|
||||
|
||||
struct
|
||||
{
|
||||
unsigned target : 26;
|
||||
unsigned : 6;
|
||||
};
|
||||
|
||||
struct
|
||||
{
|
||||
unsigned funct : 6;
|
||||
unsigned sa : 5;
|
||||
unsigned rd : 5;
|
||||
unsigned : 5;
|
||||
unsigned : 5;
|
||||
unsigned : 6;
|
||||
};
|
||||
|
||||
struct
|
||||
{
|
||||
unsigned : 6;
|
||||
unsigned fd : 5;
|
||||
unsigned fs : 5;
|
||||
unsigned ft : 5;
|
||||
unsigned fmt : 5;
|
||||
unsigned : 6;
|
||||
};
|
||||
|
||||
struct
|
||||
{
|
||||
unsigned : 6;
|
||||
unsigned code : 20;
|
||||
unsigned : 6;
|
||||
};
|
||||
};
|
||||
#pragma warning(pop)
|
||||
|
||||
enum R4300iOpCodes
|
||||
{
|
||||
R4300i_SPECIAL = 0,
|
||||
R4300i_REGIMM = 1,
|
||||
R4300i_J = 2,
|
||||
R4300i_JAL = 3,
|
||||
R4300i_BEQ = 4,
|
||||
R4300i_BNE = 5,
|
||||
R4300i_BLEZ = 6,
|
||||
R4300i_BGTZ = 7,
|
||||
R4300i_ADDI = 8,
|
||||
R4300i_ADDIU = 9,
|
||||
R4300i_SLTI = 10,
|
||||
R4300i_SLTIU = 11,
|
||||
R4300i_ANDI = 12,
|
||||
R4300i_ORI = 13,
|
||||
R4300i_XORI = 14,
|
||||
R4300i_LUI = 15,
|
||||
R4300i_CP0 = 16,
|
||||
R4300i_CP1 = 17,
|
||||
R4300i_BEQL = 20,
|
||||
R4300i_BNEL = 21,
|
||||
R4300i_BLEZL = 22,
|
||||
R4300i_BGTZL = 23,
|
||||
R4300i_DADDI = 24,
|
||||
R4300i_DADDIU = 25,
|
||||
R4300i_LDL = 26,
|
||||
R4300i_LDR = 27,
|
||||
R4300i_LB = 32,
|
||||
R4300i_LH = 33,
|
||||
R4300i_LWL = 34,
|
||||
R4300i_LW = 35,
|
||||
R4300i_LBU = 36,
|
||||
R4300i_LHU = 37,
|
||||
R4300i_LWR = 38,
|
||||
R4300i_LWU = 39,
|
||||
R4300i_SB = 40,
|
||||
R4300i_SH = 41,
|
||||
R4300i_SWL = 42,
|
||||
R4300i_SW = 43,
|
||||
R4300i_SDL = 44,
|
||||
R4300i_SDR = 45,
|
||||
R4300i_SWR = 46,
|
||||
R4300i_CACHE = 47,
|
||||
R4300i_LL = 48,
|
||||
R4300i_LWC1 = 49,
|
||||
R4300i_LDC1 = 53,
|
||||
R4300i_LD = 55,
|
||||
R4300i_SC = 56,
|
||||
R4300i_SWC1 = 57,
|
||||
R4300i_SDC1 = 61,
|
||||
R4300i_SDC2 = 62,
|
||||
R4300i_SD = 63
|
||||
};
|
||||
|
||||
enum R4300iSpecialOpCodes
|
||||
{
|
||||
R4300i_SPECIAL_SLL = 0,
|
||||
R4300i_SPECIAL_SRL = 2,
|
||||
R4300i_SPECIAL_SRA = 3,
|
||||
R4300i_SPECIAL_SLLV = 4,
|
||||
R4300i_SPECIAL_SRLV = 6,
|
||||
R4300i_SPECIAL_SRAV = 7,
|
||||
R4300i_SPECIAL_JR = 8,
|
||||
R4300i_SPECIAL_JALR = 9,
|
||||
R4300i_SPECIAL_SYSCALL = 12,
|
||||
R4300i_SPECIAL_BREAK = 13,
|
||||
R4300i_SPECIAL_SYNC = 15,
|
||||
R4300i_SPECIAL_MFHI = 16,
|
||||
R4300i_SPECIAL_MTHI = 17,
|
||||
R4300i_SPECIAL_MFLO = 18,
|
||||
R4300i_SPECIAL_MTLO = 19,
|
||||
R4300i_SPECIAL_DSLLV = 20,
|
||||
R4300i_SPECIAL_DSRLV = 22,
|
||||
R4300i_SPECIAL_DSRAV = 23,
|
||||
R4300i_SPECIAL_MULT = 24,
|
||||
R4300i_SPECIAL_MULTU = 25,
|
||||
R4300i_SPECIAL_DIV = 26,
|
||||
R4300i_SPECIAL_DIVU = 27,
|
||||
R4300i_SPECIAL_DMULT = 28,
|
||||
R4300i_SPECIAL_DMULTU = 29,
|
||||
R4300i_SPECIAL_DDIV = 30,
|
||||
R4300i_SPECIAL_DDIVU = 31,
|
||||
R4300i_SPECIAL_ADD = 32,
|
||||
R4300i_SPECIAL_ADDU = 33,
|
||||
R4300i_SPECIAL_SUB = 34,
|
||||
R4300i_SPECIAL_SUBU = 35,
|
||||
R4300i_SPECIAL_AND = 36,
|
||||
R4300i_SPECIAL_OR = 37,
|
||||
R4300i_SPECIAL_XOR = 38,
|
||||
R4300i_SPECIAL_NOR = 39,
|
||||
R4300i_SPECIAL_SLT = 42,
|
||||
R4300i_SPECIAL_SLTU = 43,
|
||||
R4300i_SPECIAL_DADD = 44,
|
||||
R4300i_SPECIAL_DADDU = 45,
|
||||
R4300i_SPECIAL_DSUB = 46,
|
||||
R4300i_SPECIAL_DSUBU = 47,
|
||||
R4300i_SPECIAL_TGE = 48,
|
||||
R4300i_SPECIAL_TGEU = 49,
|
||||
R4300i_SPECIAL_TLT = 50,
|
||||
R4300i_SPECIAL_TLTU = 51,
|
||||
R4300i_SPECIAL_TEQ = 52,
|
||||
R4300i_SPECIAL_TNE = 54,
|
||||
R4300i_SPECIAL_DSLL = 56,
|
||||
R4300i_SPECIAL_DSRL = 58,
|
||||
R4300i_SPECIAL_DSRA = 59,
|
||||
R4300i_SPECIAL_DSLL32 = 60,
|
||||
R4300i_SPECIAL_DSRL32 = 62,
|
||||
R4300i_SPECIAL_DSRA32 = 63
|
||||
};
|
||||
|
||||
enum R4300iRegImmOpCodes
|
||||
{
|
||||
R4300i_REGIMM_BLTZ = 0,
|
||||
R4300i_REGIMM_BGEZ = 1,
|
||||
R4300i_REGIMM_BLTZL = 2,
|
||||
R4300i_REGIMM_BGEZL = 3,
|
||||
R4300i_REGIMM_TGEI = 8,
|
||||
R4300i_REGIMM_TGEIU = 9,
|
||||
R4300i_REGIMM_TLTI = 10,
|
||||
R4300i_REGIMM_TLTIU = 11,
|
||||
R4300i_REGIMM_TEQI = 12,
|
||||
R4300i_REGIMM_TNEI = 14,
|
||||
R4300i_REGIMM_BLTZAL = 16,
|
||||
R4300i_REGIMM_BGEZAL = 17,
|
||||
R4300i_REGIMM_BLTZALL = 18,
|
||||
R4300i_REGIMM_BGEZALL = 19,
|
||||
};
|
||||
|
||||
enum R4300iCOP0OpCodes
|
||||
{
|
||||
R4300i_COP0_MF = 0,
|
||||
R4300i_COP0_DMF = 1,
|
||||
R4300i_COP0_MT = 4,
|
||||
R4300i_COP0_DMT = 5,
|
||||
};
|
||||
|
||||
enum R4300iCOP0C0OpCodes
|
||||
{
|
||||
R4300i_COP0_CO_TLBR = 1,
|
||||
R4300i_COP0_CO_TLBWI = 2,
|
||||
R4300i_COP0_CO_TLBWR = 6,
|
||||
R4300i_COP0_CO_TLBP = 8,
|
||||
R4300i_COP0_CO_ERET = 24,
|
||||
};
|
||||
|
||||
enum R4300iCOP1OpCodes
|
||||
{
|
||||
R4300i_COP1_MF = 0,
|
||||
R4300i_COP1_DMF = 1,
|
||||
R4300i_COP1_CF = 2,
|
||||
R4300i_COP1_MT = 4,
|
||||
R4300i_COP1_DMT = 5,
|
||||
R4300i_COP1_CT = 6,
|
||||
R4300i_COP1_BC = 8,
|
||||
R4300i_COP1_S = 16,
|
||||
R4300i_COP1_D = 17,
|
||||
R4300i_COP1_W = 20,
|
||||
R4300i_COP1_L = 21,
|
||||
};
|
||||
|
||||
enum R4300iCOP1BcOpCodes
|
||||
{
|
||||
R4300i_COP1_BC_BCF = 0,
|
||||
R4300i_COP1_BC_BCT = 1,
|
||||
R4300i_COP1_BC_BCFL = 2,
|
||||
R4300i_COP1_BC_BCTL = 3,
|
||||
};
|
||||
|
||||
enum R4300iCOP1FuntOpCodes
|
||||
{
|
||||
R4300i_COP1_FUNCT_ADD = 0,
|
||||
R4300i_COP1_FUNCT_SUB = 1,
|
||||
R4300i_COP1_FUNCT_MUL = 2,
|
||||
R4300i_COP1_FUNCT_DIV = 3,
|
||||
R4300i_COP1_FUNCT_SQRT = 4,
|
||||
R4300i_COP1_FUNCT_ABS = 5,
|
||||
R4300i_COP1_FUNCT_MOV = 6,
|
||||
R4300i_COP1_FUNCT_NEG = 7,
|
||||
R4300i_COP1_FUNCT_ROUND_L = 8,
|
||||
R4300i_COP1_FUNCT_TRUNC_L = 9,
|
||||
R4300i_COP1_FUNCT_CEIL_L = 10,
|
||||
R4300i_COP1_FUNCT_FLOOR_L = 11,
|
||||
R4300i_COP1_FUNCT_ROUND_W = 12,
|
||||
R4300i_COP1_FUNCT_TRUNC_W = 13,
|
||||
R4300i_COP1_FUNCT_CEIL_W = 14,
|
||||
R4300i_COP1_FUNCT_FLOOR_W = 15,
|
||||
R4300i_COP1_FUNCT_CVT_S = 32,
|
||||
R4300i_COP1_FUNCT_CVT_D = 33,
|
||||
R4300i_COP1_FUNCT_CVT_W = 36,
|
||||
R4300i_COP1_FUNCT_CVT_L = 37,
|
||||
R4300i_COP1_FUNCT_C_F = 48,
|
||||
R4300i_COP1_FUNCT_C_UN = 49,
|
||||
R4300i_COP1_FUNCT_C_EQ = 50,
|
||||
R4300i_COP1_FUNCT_C_UEQ = 51,
|
||||
R4300i_COP1_FUNCT_C_OLT = 52,
|
||||
R4300i_COP1_FUNCT_C_ULT = 53,
|
||||
R4300i_COP1_FUNCT_C_OLE = 54,
|
||||
R4300i_COP1_FUNCT_C_ULE = 55,
|
||||
R4300i_COP1_FUNCT_C_SF = 56,
|
||||
R4300i_COP1_FUNCT_C_NGLE = 57,
|
||||
R4300i_COP1_FUNCT_C_SEQ = 58,
|
||||
R4300i_COP1_FUNCT_C_NGL = 59,
|
||||
R4300i_COP1_FUNCT_C_LT = 60,
|
||||
R4300i_COP1_FUNCT_C_NGE = 61,
|
||||
R4300i_COP1_FUNCT_C_LE = 62,
|
||||
R4300i_COP1_FUNCT_C_NGT = 63,
|
||||
};
|
||||
|
|
@ -6,7 +6,7 @@
|
|||
#include <Project64-core/N64System/Mips/Mempak.h>
|
||||
#include <Project64-core/N64System/Mips/Transferpak.h>
|
||||
#include <Project64-core/N64System/Interpreter/InterpreterCPU.h>
|
||||
#include <Project64-core/N64System/Mips/OpcodeName.h>
|
||||
#include <Project64-core/N64System/Mips/R4300iInstruction.h>
|
||||
#include <Project64-core/N64System/Mips/Disk.h>
|
||||
#include <Project64-core/N64System/N64Disk.h>
|
||||
#include <Project64-core/N64System/Enhancement/Enhancements.h>
|
||||
|
|
@ -1738,7 +1738,7 @@ void CN64System::DumpSyncErrors(CN64System * SecondCPU)
|
|||
uint32_t OpcodeValue, Addr = m_Reg.m_PROGRAM_COUNTER + (count << 2);
|
||||
if (g_MMU->MemoryValue32(Addr, OpcodeValue))
|
||||
{
|
||||
Error.LogF("%X: %s\r\n", Addr, R4300iOpcodeName(OpcodeValue, Addr));
|
||||
Error.LogF("%X: %s\r\n", Addr, R4300iInstruction(Addr, OpcodeValue).NameAndParam().c_str());
|
||||
}
|
||||
}
|
||||
Error.Log("\r\n");
|
||||
|
|
@ -1748,7 +1748,7 @@ void CN64System::DumpSyncErrors(CN64System * SecondCPU)
|
|||
uint32_t OpcodeValue, Addr = m_LastSuccessSyncPC[0] + (count << 2);
|
||||
if (g_MMU->MemoryValue32(Addr, OpcodeValue))
|
||||
{
|
||||
Error.LogF("%X: %s\r\n", Addr, R4300iOpcodeName(OpcodeValue, Addr));
|
||||
Error.LogF("%X: %s\r\n", Addr, R4300iInstruction(Addr, OpcodeValue).NameAndParam().c_str());
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@ void CArmRecompilerOps::PreCompileOpcode(void)
|
|||
{
|
||||
if (m_PipelineStage != PIPELINE_STAGE_DELAY_SLOT_DONE)
|
||||
{
|
||||
CPU_Message(" %X %s", m_CompilePC, R4300iOpcodeName(m_Opcode.Hex, m_CompilePC));
|
||||
CPU_Message(" %X %s", m_CompilePC, R4300iInstruction(m_CompilePC, m_Opcode.Value).NameAndParam().c_str());
|
||||
}
|
||||
|
||||
/*FlushPopArmReg();
|
||||
|
|
@ -195,7 +195,7 @@ void CArmRecompilerOps::Compile_Branch(BRANCH_COMPARE CompareType, BRANCH_TYPE B
|
|||
{
|
||||
static CRegInfo RegBeforeDelay;
|
||||
static bool EffectDelaySlot;
|
||||
OPCODE Command = { 0 };
|
||||
R4300iOpcode Command = { 0 };
|
||||
|
||||
if (m_PipelineStage == PIPELINE_STAGE_NORMAL)
|
||||
{
|
||||
|
|
@ -216,7 +216,7 @@ void CArmRecompilerOps::Compile_Branch(BRANCH_COMPARE CompareType, BRANCH_TYPE B
|
|||
case BranchTypeRsRt: EffectDelaySlot = DelaySlotEffectsCompare(m_CompilePC, m_Opcode.rs, m_Opcode.rt); break;
|
||||
case BranchTypeCop1:
|
||||
|
||||
if (!g_MMU->MemoryValue32(m_CompilePC + 4, Command.Hex))
|
||||
if (!g_MMU->MemoryValue32(m_CompilePC + 4, Command.Value))
|
||||
{
|
||||
g_Notify->FatalError(GS(MSG_FAIL_LOAD_WORD));
|
||||
}
|
||||
|
|
@ -4695,7 +4695,7 @@ void CArmRecompilerOps::UnknownOpcode()
|
|||
CallFunction(AddressOf(&CN64System::SyncSystem), "CN64System::SyncSystem");
|
||||
}
|
||||
|
||||
MoveConstToVariable(m_Opcode.Hex, &R4300iOp::m_Opcode.Hex, "R4300iOp::m_Opcode.Hex");
|
||||
MoveConstToVariable(m_Opcode.Value, &R4300iOp::m_Opcode.Value, "R4300iOp::m_Opcode.Value");
|
||||
CallFunction((void *)R4300iOp::UnknownOpcode, "R4300iOp::UnknownOpcode");
|
||||
ExitCodeBlock();
|
||||
if (m_PipelineStage == PIPELINE_STAGE_NORMAL) { m_PipelineStage = PIPELINE_STAGE_END_BLOCK; }
|
||||
|
|
@ -5852,7 +5852,7 @@ void CArmRecompilerOps::SetCurrentPC(uint32_t ProgramCounter)
|
|||
m_CompilePC = ProgramCounter;
|
||||
__except_try()
|
||||
{
|
||||
if (!g_MMU->MemoryValue32(m_CompilePC, m_Opcode.Hex))
|
||||
if (!g_MMU->MemoryValue32(m_CompilePC, m_Opcode.Value))
|
||||
{
|
||||
g_Notify->FatalError(GS(MSG_FAIL_LOAD_WORD));
|
||||
}
|
||||
|
|
@ -5883,7 +5883,7 @@ PIPELINE_STAGE CArmRecompilerOps::GetNextStepType(void)
|
|||
return m_PipelineStage;
|
||||
}
|
||||
|
||||
const OPCODE &CArmRecompilerOps::GetOpcode(void) const
|
||||
const R4300iOpcode &CArmRecompilerOps::GetOpcode(void) const
|
||||
{
|
||||
return m_Opcode;
|
||||
g_Notify->BreakPoint(__FILE__, __LINE__);
|
||||
|
|
@ -5956,8 +5956,8 @@ void CArmRecompilerOps::UpdateCounters(CRegInfo & RegSet, bool CheckTimer, bool
|
|||
void CArmRecompilerOps::CompileInterpterCall(void * Function, const char * FunctionName)
|
||||
{
|
||||
m_RegWorkingSet.BeforeCallDirect();
|
||||
MoveConstToArmReg(Arm_R1, m_Opcode.Hex);
|
||||
MoveConstToArmReg(Arm_R2, (uint32_t)(void *)&R4300iOp::m_Opcode.Hex, "&R4300iOp::m_Opcode.Hex");
|
||||
MoveConstToArmReg(Arm_R1, m_Opcode.Value);
|
||||
MoveConstToArmReg(Arm_R2, (uint32_t)(void *)&R4300iOp::m_Opcode.Value, "&R4300iOp::m_Opcode.Value");
|
||||
StoreArmRegToArmRegPointer(Arm_R1, Arm_R2, 0);
|
||||
CallFunction(Function, FunctionName);
|
||||
m_RegWorkingSet.AfterCallDirect();
|
||||
|
|
|
|||
|
|
@ -210,7 +210,7 @@ private:
|
|||
void SetCurrentSection(CCodeSection * section);
|
||||
void SetNextStepType(PIPELINE_STAGE StepType);
|
||||
PIPELINE_STAGE GetNextStepType( void );
|
||||
const OPCODE & GetOpcode ( void ) const;
|
||||
const R4300iOpcode & GetOpcode ( void ) const;
|
||||
void PreCompileOpcode(void);
|
||||
void PostCompileOpcode ( void );
|
||||
void CompileExit(uint32_t JumpPC, uint32_t TargetPC, CRegInfo &ExitRegSet, CExitInfo::EXIT_REASON reason);
|
||||
|
|
@ -272,7 +272,7 @@ private:
|
|||
CMipsMemoryVM & m_MMU;
|
||||
PIPELINE_STAGE m_PipelineStage;
|
||||
uint32_t m_CompilePC;
|
||||
OPCODE m_Opcode;
|
||||
R4300iOpcode m_Opcode;
|
||||
CCodeSection * m_Section;
|
||||
|
||||
static uint32_t m_TempValue;
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
#include <Project64-core/N64System/Recompiler/Arm/ArmRecompilerOps.h>
|
||||
#include <Project64-core/N64System/SystemGlobals.h>
|
||||
#include <Project64-core/N64System/N64System.h>
|
||||
#include <Project64-core/N64System/Mips/OpcodeName.h>
|
||||
#include <Project64-core/N64System/Mips/R4300iInstruction.h>
|
||||
|
||||
bool DelaySlotEffectsCompare(uint32_t PC, uint32_t Reg1, uint32_t Reg2);
|
||||
|
||||
|
|
@ -434,16 +434,16 @@ bool CCodeBlock::AnalyzeInstruction(uint32_t PC, uint32_t & TargetPC, uint32_t &
|
|||
EndBlock = false;
|
||||
PermLoop = false;
|
||||
|
||||
OPCODE Command;
|
||||
if (!g_MMU->MemoryValue32(PC, Command.Hex))
|
||||
R4300iOpcode Command;
|
||||
if (!g_MMU->MemoryValue32(PC, Command.Value))
|
||||
{
|
||||
g_Notify->BreakPoint(__FILE__, __LINE__);
|
||||
return false;
|
||||
}
|
||||
|
||||
#ifdef _DEBUG
|
||||
const char * Name = R4300iOpcodeName(Command.Hex, PC);
|
||||
CPU_Message(" 0x%08X %s", PC, Name);
|
||||
R4300iInstruction Instruction(PC, Command.Value);
|
||||
CPU_Message(" 0x%08X %s %s", PC, Instruction.Name(), Instruction.Param());
|
||||
#endif
|
||||
switch (Command.op)
|
||||
{
|
||||
|
|
@ -550,7 +550,7 @@ bool CCodeBlock::AnalyzeInstruction(uint32_t PC, uint32_t & TargetPC, uint32_t &
|
|||
case R4300i_REGIMM_TGEIU: case R4300i_REGIMM_TLTI: case R4300i_REGIMM_TLTIU:
|
||||
break;
|
||||
default:
|
||||
if (Command.Hex == 0x0407000D)
|
||||
if (Command.Value == 0x0407000D)
|
||||
{
|
||||
EndBlock = true;
|
||||
break;
|
||||
|
|
@ -729,8 +729,8 @@ bool CCodeBlock::AnalyzeInstruction(uint32_t PC, uint32_t & TargetPC, uint32_t &
|
|||
IncludeDelaySlot = true;
|
||||
break;
|
||||
default:
|
||||
if (Command.Hex == 0x7C1C97C0 ||
|
||||
Command.Hex == 0xF1F3F5F7)
|
||||
if (Command.Value == 0x7C1C97C0 ||
|
||||
Command.Value == 0xF1F3F5F7)
|
||||
{
|
||||
EndBlock = true;
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#include "stdafx.h"
|
||||
#include <Project64-core/N64System/Recompiler/CodeSection.h>
|
||||
#include <Project64-core/N64System/Mips/OpCode.h>
|
||||
#include <Project64-core/N64System/Mips/R4300iOpcode.h>
|
||||
#include <Project64-core/N64System/SystemGlobals.h>
|
||||
#include <Project64-core/N64System/Mips/MemoryVirtualMem.h>
|
||||
#include <Project64-core/N64System/Recompiler/RecompilerCodeLog.h>
|
||||
|
|
@ -16,7 +16,7 @@ void InPermLoop();
|
|||
|
||||
bool DelaySlotEffectsCompare(uint32_t PC, uint32_t Reg1, uint32_t Reg2);
|
||||
|
||||
static bool OpHasDelaySlot(const OPCODE & Opcode)
|
||||
static bool OpHasDelaySlot(const R4300iOpcode & Opcode)
|
||||
{
|
||||
if (Opcode.op == R4300i_J ||
|
||||
Opcode.op == R4300i_JAL ||
|
||||
|
|
@ -62,9 +62,9 @@ static bool OpHasDelaySlot(const OPCODE & Opcode)
|
|||
|
||||
static bool DelaySlotEffectsJump(uint32_t JumpPC)
|
||||
{
|
||||
OPCODE Command;
|
||||
R4300iOpcode Command;
|
||||
|
||||
if (!g_MMU->MemoryValue32(JumpPC, Command.Hex))
|
||||
if (!g_MMU->MemoryValue32(JumpPC, Command.Value))
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
|
@ -110,9 +110,9 @@ static bool DelaySlotEffectsJump(uint32_t JumpPC)
|
|||
case R4300i_COP1_BC_BCTL:
|
||||
{
|
||||
bool EffectDelaySlot = false;
|
||||
OPCODE NewCommand;
|
||||
R4300iOpcode NewCommand;
|
||||
|
||||
if (!g_MMU->MemoryValue32(JumpPC + 4, NewCommand.Hex))
|
||||
if (!g_MMU->MemoryValue32(JumpPC + 4, NewCommand.Value))
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
|
@ -437,7 +437,7 @@ bool CCodeSection::GenerateNativeCode(uint32_t Test)
|
|||
}
|
||||
|
||||
uint32_t ContinueSectionPC = m_ContinueSection ? m_ContinueSection->m_EnterPC : (uint32_t)-1;
|
||||
const OPCODE & Opcode = m_RecompilerOps->GetOpcode();
|
||||
const R4300iOpcode & Opcode = m_RecompilerOps->GetOpcode();
|
||||
do
|
||||
{
|
||||
if (m_RecompilerOps->GetCurrentPC() > m_BlockInfo->VAddrLast())
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
#include <Project64-core/N64System/Recompiler/RecompilerCodeLog.h>
|
||||
#include <Project64-core/N64System/SystemGlobals.h>
|
||||
#include <Project64-core/N64System/Mips/MemoryVirtualMem.h>
|
||||
#include <Project64-core/N64System/Mips/OpcodeName.h>
|
||||
#include <Project64-core/N64System/Mips/R4300iInstruction.h>
|
||||
|
||||
#ifdef _DEBUG
|
||||
#define CHECKED_BUILD 1
|
||||
|
|
@ -172,12 +172,12 @@ bool LoopAnalysis::CheckLoopRegisterUsage(CCodeSection * Section)
|
|||
|
||||
do
|
||||
{
|
||||
if (!g_MMU->MemoryValue32(m_PC, m_Command.Hex))
|
||||
if (!g_MMU->MemoryValue32(m_PC, m_Command.Value))
|
||||
{
|
||||
g_Notify->BreakPoint(__FILE__, __LINE__);
|
||||
return false;
|
||||
}
|
||||
CPU_Message(" %08X: %s", m_PC, R4300iOpcodeName(m_Command.Hex, m_PC));
|
||||
CPU_Message(" %08X: %s", m_PC, R4300iInstruction(m_PC, m_Command.Value).NameAndParam().c_str());
|
||||
switch (m_Command.op)
|
||||
{
|
||||
case R4300i_SPECIAL:
|
||||
|
|
@ -464,14 +464,14 @@ bool LoopAnalysis::CheckLoopRegisterUsage(CCodeSection * Section)
|
|||
case R4300i_COP0_CO_TLBP: break;
|
||||
case R4300i_COP0_CO_ERET: m_PipelineStage = PIPELINE_STAGE_END_BLOCK; break;
|
||||
default:
|
||||
g_Notify->DisplayError(stdstr_f("Unhandled R4300i opcode in FillSectionInfo\n%s", R4300iOpcodeName(m_Command.Hex, m_PC)).c_str());
|
||||
g_Notify->DisplayError(stdstr_f("Unhandled R4300i opcode in FillSectionInfo\n%s", R4300iInstruction(m_PC, m_Command.Value).NameAndParam().c_str()).c_str());
|
||||
m_PipelineStage = PIPELINE_STAGE_END_BLOCK;
|
||||
m_PC -= 4;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
g_Notify->DisplayError(stdstr_f("Unhandled R4300i opcode in FillSectionInfo 3\n%s", R4300iOpcodeName(m_Command.Hex, m_PC)).c_str());
|
||||
g_Notify->DisplayError(stdstr_f("Unhandled R4300i opcode in FillSectionInfo 3\n%s", R4300iInstruction(m_PC, m_Command.Value).NameAndParam().c_str()).c_str());
|
||||
m_PipelineStage = PIPELINE_STAGE_END_BLOCK;
|
||||
m_PC -= 4;
|
||||
}
|
||||
|
|
@ -535,7 +535,7 @@ bool LoopAnalysis::CheckLoopRegisterUsage(CCodeSection * Section)
|
|||
case R4300i_COP1_W: break;
|
||||
case R4300i_COP1_L: break;
|
||||
default:
|
||||
g_Notify->DisplayError(stdstr_f("Unhandled R4300i opcode in FillSectionInfo 2\n%s", R4300iOpcodeName(m_Command.Hex, m_PC)).c_str());
|
||||
g_Notify->DisplayError(stdstr_f("Unhandled R4300i opcode in FillSectionInfo 2\n%s", R4300iInstruction(m_PC, m_Command.Value).NameAndParam().c_str()).c_str());
|
||||
m_PipelineStage = PIPELINE_STAGE_END_BLOCK;
|
||||
m_PC -= 4;
|
||||
}
|
||||
|
|
@ -630,12 +630,12 @@ bool LoopAnalysis::CheckLoopRegisterUsage(CCodeSection * Section)
|
|||
default:
|
||||
m_PipelineStage = PIPELINE_STAGE_END_BLOCK;
|
||||
m_PC -= 4;
|
||||
if (m_Command.Hex == 0x7C1C97C0) { break; }
|
||||
if (m_Command.Hex == 0x7FFFFFFF) { break; }
|
||||
if (m_Command.Hex == 0xF1F3F5F7) { break; }
|
||||
if (m_Command.Hex == 0xC1200000) { break; }
|
||||
if (m_Command.Hex == 0x4C5A5353) { break; }
|
||||
g_Notify->DisplayError(stdstr_f("Unhandled R4300i opcode in FillSectionInfo 1\n%s\n%X", R4300iOpcodeName(m_Command.Hex, m_PC), m_Command.Hex).c_str());
|
||||
if (m_Command.Value == 0x7C1C97C0) { break; }
|
||||
if (m_Command.Value == 0x7FFFFFFF) { break; }
|
||||
if (m_Command.Value == 0xF1F3F5F7) { break; }
|
||||
if (m_Command.Value == 0xC1200000) { break; }
|
||||
if (m_Command.Value == 0x4C5A5353) { break; }
|
||||
g_Notify->DisplayError(stdstr_f("Unhandled R4300i opcode in FillSectionInfo 1\n%s\n%X", R4300iInstruction(m_PC, m_Command.Value).NameAndParam().c_str(), m_Command.Value).c_str());
|
||||
}
|
||||
|
||||
CPU_Message(" %s state: %X value: %X", CRegName::GPR[5], m_Reg.GetMipsRegState(5), m_Reg.GetMipsRegLo(5));
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#pragma once
|
||||
#include <Project64-core/N64System/Recompiler/RegInfo.h>
|
||||
#include <Project64-core/N64System/Mips/OpCode.h>
|
||||
#include <Project64-core/N64System/Mips/R4300iOpcode.h>
|
||||
#include <Project64-core/N64System/N64Types.h>
|
||||
#include <map>
|
||||
|
||||
|
|
@ -75,6 +75,6 @@ private:
|
|||
uint32_t m_PC;
|
||||
CRegInfo m_Reg;
|
||||
PIPELINE_STAGE m_PipelineStage;
|
||||
OPCODE m_Command;
|
||||
R4300iOpcode m_Command;
|
||||
uint32_t m_Test;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#pragma once
|
||||
#include <Project64-core/N64System/Recompiler/RegInfo.h>
|
||||
#include <Project64-core/N64System/Recompiler/JumpInfo.h>
|
||||
#include <Project64-core/N64System/Mips/OpCode.h>
|
||||
#include <Project64-core/N64System/Mips/R4300iOpcode.h>
|
||||
|
||||
class CCodeSection;
|
||||
|
||||
|
|
@ -226,7 +226,7 @@ public:
|
|||
virtual void SetCurrentSection(CCodeSection * section) = 0;
|
||||
virtual void SetNextStepType(PIPELINE_STAGE StepType) = 0;
|
||||
virtual PIPELINE_STAGE GetNextStepType(void) = 0;
|
||||
virtual const OPCODE & GetOpcode(void) const = 0;
|
||||
virtual const R4300iOpcode & GetOpcode(void) const = 0;
|
||||
virtual void PreCompileOpcode(void) = 0;
|
||||
virtual void PostCompileOpcode(void) = 0;
|
||||
virtual void UpdateCounters(CRegInfo & RegSet, bool CheckTimer, bool ClearValues = false, bool UpdateTimer = true) = 0;
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
|
||||
#include <Project64-core/N64System/SystemGlobals.h>
|
||||
#include <Project64-core/N64System/Mips/Disk.h>
|
||||
#include <Project64-core/N64System/Mips/OpcodeName.h>
|
||||
#include <Project64-core/N64System/Mips/R4300iInstruction.h>
|
||||
#include <Project64-core/N64System/Mips/MemoryVirtualMem.h>
|
||||
#include <Project64-core/N64System/Interpreter/InterpreterOps.h>
|
||||
#include <Project64-core/N64System/Interpreter/InterpreterCPU.h>
|
||||
|
|
@ -24,7 +24,7 @@ CCodeSection * CX86RecompilerOps::m_Section = nullptr;
|
|||
CRegInfo CX86RecompilerOps::m_RegWorkingSet;
|
||||
PIPELINE_STAGE CX86RecompilerOps::m_PipelineStage;
|
||||
uint32_t CX86RecompilerOps::m_CompilePC;
|
||||
OPCODE CX86RecompilerOps::m_Opcode;
|
||||
R4300iOpcode CX86RecompilerOps::m_Opcode;
|
||||
uint32_t CX86RecompilerOps::m_BranchCompare = 0;
|
||||
uint32_t CX86RecompilerOps::m_TempValue32 = 0;
|
||||
|
||||
|
|
@ -194,7 +194,7 @@ void CX86RecompilerOps::PreCompileOpcode(void)
|
|||
{
|
||||
if (m_PipelineStage != PIPELINE_STAGE_DELAY_SLOT_DONE)
|
||||
{
|
||||
CPU_Message(" %X %s", m_CompilePC, R4300iOpcodeName(m_Opcode.Hex, m_CompilePC));
|
||||
CPU_Message(" %X %s", m_CompilePC, R4300iInstruction(m_CompilePC, m_Opcode.Value).NameAndParam().c_str());
|
||||
}
|
||||
/*if (m_CompilePC == 0x803275F4 && m_PipelineStage == PIPELINE_STAGE_NORMAL)
|
||||
{
|
||||
|
|
@ -434,7 +434,7 @@ void CX86RecompilerOps::Compile_TrapCompare(TRAP_COMPARE CompareType)
|
|||
UnMap_GPR(m_Opcode.rt, true);
|
||||
}
|
||||
m_RegWorkingSet.BeforeCallDirect();
|
||||
MoveConstToVariable(m_Opcode.Hex, &R4300iOp::m_Opcode.Hex, "R4300iOp::m_Opcode.Hex");
|
||||
MoveConstToVariable(m_Opcode.Value, &R4300iOp::m_Opcode.Value, "R4300iOp::m_Opcode.Value");
|
||||
Call_Direct(FunctAddress, FunctName);
|
||||
m_RegWorkingSet.AfterCallDirect();
|
||||
}
|
||||
|
|
@ -486,9 +486,9 @@ void CX86RecompilerOps::Compile_Branch(BRANCH_COMPARE CompareType, BRANCH_TYPE B
|
|||
case BranchTypeRsRt: EffectDelaySlot = DelaySlotEffectsCompare(m_CompilePC, m_Opcode.rs, m_Opcode.rt); break;
|
||||
case BranchTypeCop1:
|
||||
{
|
||||
OPCODE Command;
|
||||
R4300iOpcode Command;
|
||||
|
||||
if (!g_MMU->MemoryValue32(m_CompilePC + 4, Command.Hex))
|
||||
if (!g_MMU->MemoryValue32(m_CompilePC + 4, Command.Value))
|
||||
{
|
||||
g_Notify->FatalError(GS(MSG_FAIL_LOAD_WORD));
|
||||
}
|
||||
|
|
@ -2652,7 +2652,7 @@ void CX86RecompilerOps::DADDIU()
|
|||
}
|
||||
|
||||
m_RegWorkingSet.BeforeCallDirect();
|
||||
MoveConstToVariable(m_Opcode.Hex, &R4300iOp::m_Opcode.Hex, "R4300iOp::m_Opcode.Hex");
|
||||
MoveConstToVariable(m_Opcode.Value, &R4300iOp::m_Opcode.Value, "R4300iOp::m_Opcode.Value");
|
||||
Call_Direct((void *)R4300iOp::DADDIU, "R4300iOp::DADDIU");
|
||||
m_RegWorkingSet.AfterCallDirect();
|
||||
}
|
||||
|
|
@ -2728,7 +2728,7 @@ void CX86RecompilerOps::LDL()
|
|||
}
|
||||
|
||||
m_RegWorkingSet.BeforeCallDirect();
|
||||
MoveConstToVariable(m_Opcode.Hex, &R4300iOp::m_Opcode.Hex, "R4300iOp::m_Opcode.Hex");
|
||||
MoveConstToVariable(m_Opcode.Value, &R4300iOp::m_Opcode.Value, "R4300iOp::m_Opcode.Value");
|
||||
Call_Direct((void *)R4300iOp::LDL, "R4300iOp::LDL");
|
||||
m_RegWorkingSet.AfterCallDirect();
|
||||
}
|
||||
|
|
@ -2746,7 +2746,7 @@ void CX86RecompilerOps::LDR()
|
|||
}
|
||||
|
||||
m_RegWorkingSet.BeforeCallDirect();
|
||||
MoveConstToVariable(m_Opcode.Hex, &R4300iOp::m_Opcode.Hex, "R4300iOp::m_Opcode.Hex");
|
||||
MoveConstToVariable(m_Opcode.Value, &R4300iOp::m_Opcode.Value, "R4300iOp::m_Opcode.Value");
|
||||
Call_Direct((void *)R4300iOp::LDR, "R4300iOp::LDR");
|
||||
m_RegWorkingSet.AfterCallDirect();
|
||||
}
|
||||
|
|
@ -3803,7 +3803,7 @@ void CX86RecompilerOps::SDL()
|
|||
}
|
||||
|
||||
m_RegWorkingSet.BeforeCallDirect();
|
||||
MoveConstToVariable(m_Opcode.Hex, &R4300iOp::m_Opcode.Hex, "R4300iOp::m_Opcode.Hex");
|
||||
MoveConstToVariable(m_Opcode.Value, &R4300iOp::m_Opcode.Value, "R4300iOp::m_Opcode.Value");
|
||||
Call_Direct((void *)R4300iOp::SDL, "R4300iOp::SDL");
|
||||
m_RegWorkingSet.AfterCallDirect();
|
||||
}
|
||||
|
|
@ -3821,7 +3821,7 @@ void CX86RecompilerOps::SDR()
|
|||
}
|
||||
|
||||
m_RegWorkingSet.BeforeCallDirect();
|
||||
MoveConstToVariable(m_Opcode.Hex, &R4300iOp::m_Opcode.Hex, "R4300iOp::m_Opcode.Hex");
|
||||
MoveConstToVariable(m_Opcode.Value, &R4300iOp::m_Opcode.Value, "R4300iOp::m_Opcode.Value");
|
||||
Call_Direct((void *)R4300iOp::SDR, "R4300iOp::SDR");
|
||||
m_RegWorkingSet.AfterCallDirect();
|
||||
}
|
||||
|
|
@ -4908,7 +4908,7 @@ void CX86RecompilerOps::SPECIAL_DMULT()
|
|||
}
|
||||
|
||||
m_RegWorkingSet.BeforeCallDirect();
|
||||
MoveConstToVariable(m_Opcode.Hex, &R4300iOp::m_Opcode.Hex, "R4300iOp::m_Opcode.Hex");
|
||||
MoveConstToVariable(m_Opcode.Value, &R4300iOp::m_Opcode.Value, "R4300iOp::m_Opcode.Value");
|
||||
Call_Direct((void *)R4300iOp::SPECIAL_DMULT, "R4300iOp::SPECIAL_DMULT");
|
||||
m_RegWorkingSet.AfterCallDirect();
|
||||
}
|
||||
|
|
@ -4918,7 +4918,7 @@ void CX86RecompilerOps::SPECIAL_DMULTU()
|
|||
UnMap_GPR(m_Opcode.rs, true);
|
||||
UnMap_GPR(m_Opcode.rt, true);
|
||||
m_RegWorkingSet.BeforeCallDirect();
|
||||
MoveConstToVariable(m_Opcode.Hex, &R4300iOp::m_Opcode.Hex, "R4300iOp::m_Opcode.Hex");
|
||||
MoveConstToVariable(m_Opcode.Value, &R4300iOp::m_Opcode.Value, "R4300iOp::m_Opcode.Value");
|
||||
Call_Direct((void *)R4300iOp::SPECIAL_DMULTU, "R4300iOp::SPECIAL_DMULTU");
|
||||
m_RegWorkingSet.AfterCallDirect();
|
||||
|
||||
|
|
@ -4995,7 +4995,7 @@ void CX86RecompilerOps::SPECIAL_DDIV()
|
|||
UnMap_GPR(m_Opcode.rs, true);
|
||||
UnMap_GPR(m_Opcode.rt, true);
|
||||
m_RegWorkingSet.BeforeCallDirect();
|
||||
MoveConstToVariable(m_Opcode.Hex, &R4300iOp::m_Opcode.Hex, "R4300iOp::m_Opcode.Hex");
|
||||
MoveConstToVariable(m_Opcode.Value, &R4300iOp::m_Opcode.Value, "R4300iOp::m_Opcode.Value");
|
||||
Call_Direct((void *)R4300iOp::SPECIAL_DDIV, "R4300iOp::SPECIAL_DDIV");
|
||||
m_RegWorkingSet.AfterCallDirect();
|
||||
}
|
||||
|
|
@ -5005,7 +5005,7 @@ void CX86RecompilerOps::SPECIAL_DDIVU()
|
|||
UnMap_GPR(m_Opcode.rs, true);
|
||||
UnMap_GPR(m_Opcode.rt, true);
|
||||
m_RegWorkingSet.BeforeCallDirect();
|
||||
MoveConstToVariable(m_Opcode.Hex, &R4300iOp::m_Opcode.Hex, "R4300iOp::m_Opcode.Hex");
|
||||
MoveConstToVariable(m_Opcode.Value, &R4300iOp::m_Opcode.Value, "R4300iOp::m_Opcode.Value");
|
||||
Call_Direct((void *)R4300iOp::SPECIAL_DDIVU, "R4300iOp::SPECIAL_DDIVU");
|
||||
m_RegWorkingSet.AfterCallDirect();
|
||||
}
|
||||
|
|
@ -8252,7 +8252,7 @@ void CX86RecompilerOps::COP1_L_CVT_D()
|
|||
// Other functions
|
||||
void CX86RecompilerOps::UnknownOpcode()
|
||||
{
|
||||
CPU_Message(" %X Unhandled opcode: %s", m_CompilePC, R4300iOpcodeName(m_Opcode.Hex, m_CompilePC));
|
||||
CPU_Message(" %X Unhandled opcode: %s", m_CompilePC, R4300iInstruction(m_CompilePC, m_Opcode.Value).NameAndParam().c_str());
|
||||
|
||||
m_RegWorkingSet.WriteBackRegisters();
|
||||
UpdateCounters(m_RegWorkingSet, false, true);
|
||||
|
|
@ -8270,7 +8270,7 @@ void CX86RecompilerOps::UnknownOpcode()
|
|||
}
|
||||
m_RegWorkingSet.SetBlockCycleCount(m_RegWorkingSet.GetBlockCycleCount() - g_System->CountPerOp());
|
||||
|
||||
MoveConstToVariable(m_Opcode.Hex, &R4300iOp::m_Opcode.Hex, "R4300iOp::m_Opcode.Hex");
|
||||
MoveConstToVariable(m_Opcode.Value, &R4300iOp::m_Opcode.Value, "R4300iOp::m_Opcode.Value");
|
||||
Call_Direct((void *)R4300iOp::UnknownOpcode, "R4300iOp::UnknownOpcode");
|
||||
Ret();
|
||||
if (m_PipelineStage == PIPELINE_STAGE_NORMAL) { m_PipelineStage = PIPELINE_STAGE_END_BLOCK; }
|
||||
|
|
@ -9144,7 +9144,7 @@ void CX86RecompilerOps::SetCurrentPC(uint32_t ProgramCounter)
|
|||
m_CompilePC = ProgramCounter;
|
||||
__except_try()
|
||||
{
|
||||
if (!g_MMU->MemoryValue32(m_CompilePC, m_Opcode.Hex))
|
||||
if (!g_MMU->MemoryValue32(m_CompilePC, m_Opcode.Value))
|
||||
{
|
||||
g_Notify->FatalError(GS(MSG_FAIL_LOAD_WORD));
|
||||
}
|
||||
|
|
@ -9175,7 +9175,7 @@ PIPELINE_STAGE CX86RecompilerOps::GetNextStepType(void)
|
|||
return m_PipelineStage;
|
||||
}
|
||||
|
||||
const OPCODE & CX86RecompilerOps::GetOpcode(void) const
|
||||
const R4300iOpcode & CX86RecompilerOps::GetOpcode(void) const
|
||||
{
|
||||
return m_Opcode;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
#if defined(__i386__) || defined(_M_IX86)
|
||||
|
||||
#include <Project64-core/N64System/Mips/Register.h>
|
||||
#include <Project64-core/N64System/Mips/OpCode.h>
|
||||
#include <Project64-core/N64System/Mips/R4300iOpcode.h>
|
||||
#include <Project64-core/N64System/Recompiler/ExitInfo.h>
|
||||
#include <Project64-core/N64System/Recompiler/RegInfo.h>
|
||||
#include <Project64-core/N64System/Recompiler/RecompilerOps.h>
|
||||
|
|
@ -228,7 +228,7 @@ public:
|
|||
void SetCurrentSection(CCodeSection * section);
|
||||
void SetNextStepType(PIPELINE_STAGE StepType);
|
||||
PIPELINE_STAGE GetNextStepType(void);
|
||||
const OPCODE & GetOpcode(void) const;
|
||||
const R4300iOpcode & GetOpcode(void) const;
|
||||
void PreCompileOpcode(void);
|
||||
void PostCompileOpcode(void);
|
||||
void CompileExit(uint32_t JumpPC, uint32_t TargetPC, CRegInfo &ExitRegSet, CExitInfo::EXIT_REASON reason);
|
||||
|
|
@ -379,7 +379,7 @@ private:
|
|||
CMipsMemoryVM & m_MMU;
|
||||
static PIPELINE_STAGE m_PipelineStage;
|
||||
static uint32_t m_CompilePC;
|
||||
static OPCODE m_Opcode;
|
||||
static R4300iOpcode m_Opcode;
|
||||
static CX86RegInfo m_RegWorkingSet;
|
||||
static uint32_t m_BranchCompare;
|
||||
static CCodeSection * m_Section;
|
||||
|
|
|
|||
|
|
@ -72,8 +72,8 @@
|
|||
<ClCompile Include="N64System\Mips\GBCart.cpp" />
|
||||
<ClCompile Include="N64System\Mips\MemoryVirtualMem.cpp" />
|
||||
<ClCompile Include="N64System\Mips\Mempak.cpp" />
|
||||
<ClCompile Include="N64System\Mips\OpcodeName.cpp" />
|
||||
<ClCompile Include="N64System\Mips\PifRam.cpp" />
|
||||
<ClCompile Include="N64System\Mips\R4300iInstruction.cpp" />
|
||||
<ClCompile Include="N64System\Mips\Register.cpp" />
|
||||
<ClCompile Include="N64System\Mips\Rumblepak.cpp" />
|
||||
<ClCompile Include="N64System\Mips\SystemEvents.cpp" />
|
||||
|
|
@ -188,9 +188,9 @@
|
|||
<ClInclude Include="N64System\Mips\GBCart.h" />
|
||||
<ClInclude Include="N64System\Mips\MemoryVirtualMem.h" />
|
||||
<ClInclude Include="N64System\Mips\Mempak.h" />
|
||||
<ClInclude Include="N64System\Mips\OpCode.h" />
|
||||
<ClInclude Include="N64System\Mips\OpcodeName.h" />
|
||||
<ClInclude Include="N64System\Mips\PifRam.h" />
|
||||
<ClInclude Include="N64System\Mips\R4300iInstruction.h" />
|
||||
<ClInclude Include="N64System\Mips\R4300iOpcode.h" />
|
||||
<ClInclude Include="N64System\Mips\Register.h" />
|
||||
<ClInclude Include="N64System\Mips\Rumblepak.h" />
|
||||
<ClInclude Include="N64System\Mips\Sram.h" />
|
||||
|
|
|
|||
|
|
@ -258,9 +258,6 @@
|
|||
<ClCompile Include="N64System\Mips\Mempak.cpp">
|
||||
<Filter>Source Files\N64 System\Mips</Filter>
|
||||
</ClCompile>
|
||||
<ClCompile Include="N64System\Mips\OpcodeName.cpp">
|
||||
<Filter>Source Files\N64 System\Mips</Filter>
|
||||
</ClCompile>
|
||||
<ClCompile Include="N64System\Mips\PifRam.cpp">
|
||||
<Filter>Source Files\N64 System\Mips</Filter>
|
||||
</ClCompile>
|
||||
|
|
@ -405,6 +402,9 @@
|
|||
<ClCompile Include="N64System\MemoryHandler\CartridgeDomain2Address2Handler.cpp">
|
||||
<Filter>Source Files\N64 System\MemoryHandler</Filter>
|
||||
</ClCompile>
|
||||
<ClCompile Include="N64System\Mips\R4300iInstruction.cpp">
|
||||
<Filter>Source Files\N64 System\Mips</Filter>
|
||||
</ClCompile>
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClInclude Include="stdafx.h">
|
||||
|
|
@ -602,12 +602,6 @@
|
|||
<ClInclude Include="N64System\Mips\Mempak.H">
|
||||
<Filter>Header Files\N64 System\Mips</Filter>
|
||||
</ClInclude>
|
||||
<ClInclude Include="N64System\Mips\OpCode.h">
|
||||
<Filter>Header Files\N64 System\Mips</Filter>
|
||||
</ClInclude>
|
||||
<ClInclude Include="N64System\Mips\OpcodeName.h">
|
||||
<Filter>Header Files\N64 System\Mips</Filter>
|
||||
</ClInclude>
|
||||
<ClInclude Include="N64System\Mips\PifRam.h">
|
||||
<Filter>Header Files\N64 System\Mips</Filter>
|
||||
</ClInclude>
|
||||
|
|
@ -791,6 +785,12 @@
|
|||
<ClInclude Include="..\Project64-plugin-spec\Rsp.h">
|
||||
<Filter>Header Files\Plugin Spec</Filter>
|
||||
</ClInclude>
|
||||
<ClInclude Include="N64System\Mips\R4300iInstruction.h">
|
||||
<Filter>Header Files\N64 System\Mips</Filter>
|
||||
</ClInclude>
|
||||
<ClInclude Include="N64System\Mips\R4300iOpcode.h">
|
||||
<Filter>Header Files\N64 System\Mips</Filter>
|
||||
</ClInclude>
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<None Include="Version.h.in">
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
|
||||
#include <Project64-core/N64System/N64Rom.h>
|
||||
#include <Project64-core/N64System/SpeedLimiter.h>
|
||||
#include <Project64-core/N64System/Mips/OpCode.h>
|
||||
#include <Project64-core/N64System/Mips/R4300iOpcode.h>
|
||||
#include <Project64-core/N64System/Recompiler/x86/x86ops.h>
|
||||
#include <Project64-core/N64System/N64System.h>
|
||||
#include <Project64-core/N64System/SystemGlobals.h>
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
#include "stdafx.h"
|
||||
|
||||
#include "Assembler.h"
|
||||
#include "Project64-core/N64System/Mips/OpCode.h"
|
||||
#include "Project64-core/N64System/Mips/R4300iOpcode.h"
|
||||
|
||||
ASM_PARSE_ERROR CAssembler::m_ParseError = ERR_NONE;
|
||||
uint32_t CAssembler::m_Address = 0;
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
|
||||
#include <Project64-core/N64System/Mips/Register.h>
|
||||
#include <Project64-core/N64System/SystemGlobals.h>
|
||||
#include <Project64-core/N64System/Mips/OpcodeName.h>
|
||||
#include <Project64-core/N64System/Mips/R4300iInstruction.h>
|
||||
#include <Project64-core/N64System/N64System.h>
|
||||
|
||||
CBreakpoints::CBreakpoints() :
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#include "stdafx.h"
|
||||
#include "CPULog.h"
|
||||
#include <Project64-core/N64System/Mips/OpCodeName.h>
|
||||
#include <Project64-core/N64System/Mips/R4300iInstruction.h>
|
||||
|
||||
CCPULog::CCPULog(size_t size) :
|
||||
m_bMaxed(false),
|
||||
|
|
@ -166,19 +166,8 @@ void CCPULog::DumpToFile(const char* path)
|
|||
for (size_t i = 0; i < count; i++)
|
||||
{
|
||||
CPUState* state = GetEntry(i);
|
||||
|
||||
char *tokctx;
|
||||
|
||||
char* szCommand = (char*)R4300iOpcodeName(state->opcode.Hex, state->pc);
|
||||
char* szCmdName = strtok_s((char*)szCommand, "\t", &tokctx);
|
||||
char* szCmdArgs = strtok_s(nullptr, "\t", &tokctx);
|
||||
|
||||
if (szCmdArgs == nullptr)
|
||||
{
|
||||
szCmdArgs = "";
|
||||
}
|
||||
|
||||
fprintf(fp, "%08X: %08X %s %s\n", state->pc, state->opcode.Hex, szCmdName, szCmdArgs);
|
||||
R4300iInstruction Instruction(state->pc, state->opcode.Value);
|
||||
fprintf(fp, "%08X: %08X %s %s\n", state->pc, state->opcode.Value, Instruction.Name(), Instruction.Param());
|
||||
}
|
||||
|
||||
fclose(fp);
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
typedef struct
|
||||
{
|
||||
uint32_t pc;
|
||||
OPCODE opcode;
|
||||
R4300iOpcode opcode;
|
||||
MIPS_DWORD gpr[32];
|
||||
MIPS_DWORD gprHi;
|
||||
MIPS_DWORD gprLo;
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
#include "CPULog.h"
|
||||
|
||||
#include "Debugger-CPULogView.h"
|
||||
#include <Project64-core/N64System/Mips/OpCodeName.h>
|
||||
#include <Project64-core/N64System/Mips/R4300iInstruction.h>
|
||||
|
||||
CDebugCPULogView* CDebugCPULogView::_this = nullptr;
|
||||
HHOOK CDebugCPULogView::hWinMessageHook = nullptr;
|
||||
|
|
@ -327,17 +327,11 @@ void CDebugCPULogView::RefreshList(bool bUpdateBuffer)
|
|||
|
||||
char szPC[9];
|
||||
sprintf(szPC, "%08X", state->pc);
|
||||
|
||||
char *tokctx;
|
||||
|
||||
char* szCommand = (char*)R4300iOpcodeName(state->opcode.Hex, state->pc);
|
||||
char* szCmdName = strtok_s((char*)szCommand, "\t", &tokctx);
|
||||
char* szCmdArgs = strtok_s(nullptr, "\t", &tokctx);
|
||||
R4300iInstruction Instruction(state->pc, state->opcode.Value);
|
||||
|
||||
m_CPUListView.AddItem(nItem, 0, stdstr(szPC).ToUTF16().c_str());
|
||||
m_CPUListView.AddItem(nItem, 1, stdstr(szCmdName).ToUTF16().c_str());
|
||||
m_CPUListView.AddItem(nItem, 2, stdstr(szCmdArgs).ToUTF16().c_str());
|
||||
|
||||
m_CPUListView.AddItem(nItem, 1, stdstr(Instruction.Name()).ToUTF16().c_str());
|
||||
m_CPUListView.AddItem(nItem, 2, stdstr(Instruction.Param()).ToUTF16().c_str());
|
||||
nItem++;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
#include "Assembler.h"
|
||||
#include "OpInfo.h"
|
||||
|
||||
#include <Project64-core/N64System/Mips/OpCodeName.h>
|
||||
#include <Project64-core/N64System/Mips/R4300iInstruction.h>
|
||||
|
||||
void CCommandList::Attach(HWND hWndNew)
|
||||
{
|
||||
|
|
@ -531,18 +531,17 @@ void CDebugCommandsView::ShowAddress(uint32_t address, bool top, bool bUserInput
|
|||
m_CommandList.AddItem(i, CCommandList::COL_ADDRESS, stdstr(addrStr).ToUTF16().c_str());
|
||||
|
||||
COpInfo OpInfo;
|
||||
OPCODE& OpCode = OpInfo.m_OpCode;
|
||||
R4300iOpcode& OpCode = OpInfo.m_OpCode;
|
||||
|
||||
if (!m_Debugger->DebugLoad_VAddr(opAddr, OpCode.Hex))
|
||||
if (!m_Debugger->DebugLoad_VAddr(opAddr, OpCode.Value))
|
||||
{
|
||||
m_CommandList.AddItem(i, CCommandList::COL_COMMAND, L"***");
|
||||
m_bvAnnotatedLines.push_back(false);
|
||||
continue;
|
||||
}
|
||||
|
||||
char* command = (char*)R4300iOpcodeName(OpCode.Hex, opAddr);
|
||||
char* cmdName = strtok((char*)command, "\t");
|
||||
char* cmdArgs = strtok(nullptr, "\t");
|
||||
R4300iInstruction Instruction(opAddr, OpCode.Value);
|
||||
std::string cmdArgs = Instruction.Param();
|
||||
|
||||
CSymbol jalSymbol;
|
||||
|
||||
|
|
@ -553,7 +552,7 @@ void CDebugCommandsView::ShowAddress(uint32_t address, bool top, bool bUserInput
|
|||
|
||||
if (m_Debugger->SymbolTable()->GetSymbolByAddress(targetAddr, &jalSymbol))
|
||||
{
|
||||
cmdArgs = (char*)jalSymbol.m_Name;
|
||||
cmdArgs = jalSymbol.m_Name;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -567,9 +566,9 @@ void CDebugCommandsView::ShowAddress(uint32_t address, bool top, bool bUserInput
|
|||
{
|
||||
for (int offset = -4; offset > -24; offset -= 4)
|
||||
{
|
||||
OPCODE OpCodeTest;
|
||||
R4300iOpcode OpCodeTest;
|
||||
|
||||
if (!m_Debugger->DebugLoad_VAddr(opAddr + offset, OpCodeTest.Hex))
|
||||
if (!m_Debugger->DebugLoad_VAddr(opAddr + offset, OpCodeTest.Value))
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
|
@ -607,7 +606,7 @@ void CDebugCommandsView::ShowAddress(uint32_t address, bool top, bool bUserInput
|
|||
bLoadStoreAnnotation = true;
|
||||
}
|
||||
|
||||
m_CommandList.AddItem(i, CCommandList::COL_COMMAND, stdstr(cmdName).ToUTF16().c_str());
|
||||
m_CommandList.AddItem(i, CCommandList::COL_COMMAND, stdstr(Instruction.Name()).ToUTF16().c_str());
|
||||
m_CommandList.AddItem(i, CCommandList::COL_PARAMETERS, stdstr(cmdArgs).ToUTF16().c_str());
|
||||
|
||||
// Show routine symbol name for this address
|
||||
|
|
@ -685,10 +684,10 @@ LRESULT CDebugCommandsView::OnCustomDrawList(NMHDR* pNMHDR)
|
|||
uint32_t address = m_StartAddress + (nItem * 4);
|
||||
uint32_t pc = (g_Reg != nullptr) ? g_Reg->m_PROGRAM_COUNTER : 0;
|
||||
|
||||
OPCODE pcOpcode;
|
||||
if (!m_Debugger->DebugLoad_VAddr(pc, pcOpcode.Hex))
|
||||
R4300iOpcode pcOpcode;
|
||||
if (!m_Debugger->DebugLoad_VAddr(pc, pcOpcode.Value))
|
||||
{
|
||||
pcOpcode.Hex = 0;
|
||||
pcOpcode.Value = 0;
|
||||
}
|
||||
|
||||
if (nSubItem == CCommandList::COL_ARROWS)
|
||||
|
|
@ -735,8 +734,8 @@ LRESULT CDebugCommandsView::OnCustomDrawList(NMHDR* pNMHDR)
|
|||
|
||||
// Command and arguments
|
||||
COpInfo OpInfo;
|
||||
OPCODE& OpCode = OpInfo.m_OpCode;
|
||||
bool bAddrOkay = m_Debugger->DebugLoad_VAddr(address, OpCode.Hex);
|
||||
R4300iOpcode& OpCode = OpInfo.m_OpCode;
|
||||
bool bAddrOkay = m_Debugger->DebugLoad_VAddr(address, OpCode.Value);
|
||||
|
||||
struct {
|
||||
COLORREF bg;
|
||||
|
|
@ -1057,7 +1056,7 @@ void CDebugCommandsView::CPUResume()
|
|||
void CDebugCommandsView::CPUStepOver()
|
||||
{
|
||||
COpInfo opInfo;
|
||||
if (!m_Debugger->DebugLoad_VAddr(g_Reg->m_PROGRAM_COUNTER, opInfo.m_OpCode.Hex))
|
||||
if (!m_Debugger->DebugLoad_VAddr(g_Reg->m_PROGRAM_COUNTER, opInfo.m_OpCode.Value))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
|
@ -1282,12 +1281,10 @@ void CDebugCommandsView::BeginOpEdit(uint32_t address)
|
|||
itemRect.left += listRect.left + 3;
|
||||
itemRect.right += 100;
|
||||
|
||||
char* command = (char*)R4300iOpcodeName(opcode, address);
|
||||
|
||||
m_OpEdit.ShowWindow(SW_SHOW);
|
||||
m_OpEdit.MoveWindow(&itemRect);
|
||||
m_OpEdit.BringWindowToTop();
|
||||
m_OpEdit.SetWindowText(stdstr(command).ToUTF16().c_str());
|
||||
m_OpEdit.SetWindowText(stdstr(R4300iInstruction(address, opcode).NameAndParam()).ToUTF16().c_str());
|
||||
m_OpEdit.SetFocus();
|
||||
m_OpEdit.SetSelAll();
|
||||
|
||||
|
|
@ -1376,7 +1373,7 @@ LRESULT CDebugCommandsView::OnCommandListRightClicked(NMHDR* pNMHDR)
|
|||
uint32_t address = m_StartAddress + nItem * 4;
|
||||
m_SelectedAddress = address;
|
||||
|
||||
if (!m_Debugger->DebugLoad_VAddr(m_SelectedAddress, m_SelectedOpCode.Hex))
|
||||
if (!m_Debugger->DebugLoad_VAddr(m_SelectedAddress, m_SelectedOpCode.Value))
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -282,7 +282,7 @@ private:
|
|||
|
||||
uint32_t m_SelectedAddress;
|
||||
COpInfo m_SelectedOpInfo;
|
||||
OPCODE& m_SelectedOpCode = m_SelectedOpInfo.m_OpCode;
|
||||
R4300iOpcode& m_SelectedOpCode = m_SelectedOpInfo.m_OpCode;
|
||||
|
||||
uint32_t m_FollowAddress;
|
||||
uint32_t m_RowHeight;
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
#include "DebuggerUI.h"
|
||||
|
||||
#include <Project64-core/N64System/Mips/OpCodeName.h>
|
||||
#include <Project64-core/N64System/Mips/R4300iInstruction.h>
|
||||
|
||||
CDumpMemory::CDumpMemory(CDebuggerUI * debugger) :
|
||||
CDebugDialog<CDumpMemory>(debugger)
|
||||
|
|
@ -152,16 +152,11 @@ bool CDumpMemory::DumpMemory(LPCTSTR FileName, DumpFormat Format, DWORD StartPC,
|
|||
|
||||
for (uint32_t pc = StartPC; pc < EndPC; pc += 4, DumpPC += 4)
|
||||
{
|
||||
OPCODE opcode;
|
||||
m_Debugger->DebugLoad_VAddr(pc, opcode.Hex);
|
||||
R4300iOpcode opcode;
|
||||
m_Debugger->DebugLoad_VAddr(pc, opcode.Value);
|
||||
|
||||
const char* command = R4300iOpcodeName(opcode.Hex, DumpPC);
|
||||
|
||||
char* cmdName = strtok((char*)command, "\t");
|
||||
char* cmdArgs = strtok(nullptr, "\t");
|
||||
cmdArgs = cmdArgs ? cmdArgs : "";
|
||||
|
||||
LogFile.LogF("%X: %-15s%s\r\n", DumpPC, cmdName, cmdArgs);
|
||||
R4300iInstruction Instruction(DumpPC, opcode.Value);
|
||||
LogFile.LogF("%X: %-15s%s\r\n", DumpPC, Instruction.Name(), Instruction.Param());
|
||||
}
|
||||
|
||||
m_StartAddress.SetValue(StartPC, DisplayMode::AllHex);
|
||||
|
|
|
|||
|
|
@ -484,7 +484,7 @@ INT_PTR CALLBACK CRegisterTabs::TabProcGPR(HWND hDlg, UINT msg, WPARAM wParam, L
|
|||
WORD ctrlId = (WORD) ::GetWindowLong(hWnd, GWL_ID);
|
||||
|
||||
COpInfo opInfo;
|
||||
m_Debugger->DebugLoad_VAddr(g_Reg->m_PROGRAM_COUNTER, opInfo.m_OpCode.Hex);
|
||||
m_Debugger->DebugLoad_VAddr(g_Reg->m_PROGRAM_COUNTER, opInfo.m_OpCode.Value);
|
||||
|
||||
bool bOpReads = false;
|
||||
bool bOpWrites = false;
|
||||
|
|
|
|||
|
|
@ -692,7 +692,7 @@ void CDebuggerUI::CPUStepEnded()
|
|||
return;
|
||||
}
|
||||
|
||||
OPCODE Opcode = R4300iOp::m_Opcode;
|
||||
R4300iOpcode Opcode = R4300iOp::m_Opcode;
|
||||
uint32_t op = Opcode.op;
|
||||
uint32_t funct = Opcode.funct;
|
||||
|
||||
|
|
|
|||
|
|
@ -2,19 +2,19 @@
|
|||
|
||||
#include <stdafx.h>
|
||||
|
||||
#include <Project64-core/N64System/Mips/OpCode.h>
|
||||
#include <Project64-core/N64System/Mips/R4300iOpcode.h>
|
||||
|
||||
class COpInfo
|
||||
{
|
||||
public:
|
||||
|
||||
OPCODE m_OpCode;
|
||||
R4300iOpcode m_OpCode;
|
||||
|
||||
COpInfo()
|
||||
{
|
||||
}
|
||||
|
||||
inline COpInfo(OPCODE opcode):
|
||||
inline COpInfo(R4300iOpcode opcode):
|
||||
m_OpCode(opcode)
|
||||
{
|
||||
}
|
||||
|
|
@ -123,7 +123,7 @@ public:
|
|||
|
||||
bool IsNOP()
|
||||
{
|
||||
if (m_OpCode.Hex == 0)
|
||||
if (m_OpCode.Value == 0)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#include <stdafx.h>
|
||||
#include "ScriptAPI.h"
|
||||
#include "../Assembler.h"
|
||||
#include <Project64-core/N64System/Mips/OpCodeName.h>
|
||||
#include <Project64-core/N64System/Mips/R4300iInstruction.h>
|
||||
|
||||
void ScriptAPI::Define_asm(duk_context *ctx)
|
||||
{
|
||||
|
|
@ -67,16 +67,6 @@ duk_ret_t ScriptAPI::js_asm_decode(duk_context* ctx)
|
|||
|
||||
uint32_t opcode = duk_get_uint(ctx, 0);
|
||||
uint32_t address = duk_get_uint_default(ctx, 1, 0);
|
||||
|
||||
// TODO: Thread safe version of R4300iOpcodeName
|
||||
|
||||
char* code = (char*)R4300iOpcodeName(opcode, address);
|
||||
char* ptab = strchr(code, '\t');
|
||||
if (ptab != nullptr)
|
||||
{
|
||||
*ptab = ' ';
|
||||
}
|
||||
|
||||
duk_push_string(ctx, code);
|
||||
duk_push_string(ctx, R4300iInstruction(address, opcode).NameAndParam().c_str());
|
||||
return 1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -299,7 +299,7 @@ bool CbCond_PcBetween_OpcodeEquals(JSAppCallback* cb, void* _env)
|
|||
}
|
||||
|
||||
JSHookCpuStepEnv* env = (JSHookCpuStepEnv*)_env;
|
||||
return cb->m_Params.opcode == (env->opInfo.m_OpCode.Hex & cb->m_Params.opcodeMask);
|
||||
return cb->m_Params.opcode == (env->opInfo.m_OpCode.Value & cb->m_Params.opcodeMask);
|
||||
}
|
||||
|
||||
static bool CbCond_PcBetween_GprValueEquals(JSAppCallback* cb, void* _env)
|
||||
|
|
@ -654,7 +654,7 @@ duk_idx_t CbArgs_OpcodeEventObject(duk_context* ctx, void* _env)
|
|||
const DukPropListEntry props[] = {
|
||||
{ "callbackId", DukUInt(inst->CallbackId()) },
|
||||
{ "pc", DukUInt(env->pc) },
|
||||
{ "opcode", DukUInt(env->opInfo.m_OpCode.Hex) },
|
||||
{ "opcode", DukUInt(env->opInfo.m_OpCode.Value) },
|
||||
{ nullptr }
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue