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RSP: Remove some unused functions and turn Reordering and Sections off by default

This commit is contained in:
zilmar 2024-07-20 17:08:20 +09:30
parent 6816ff4435
commit 7c2655c544
2 changed files with 2 additions and 278 deletions
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4
Source/Project64-rsp-core/RSPInfo.cpp
View File

@ -104,8 +104,8 @@ void RspPluginLoaded(void)
Compiler.bDest = true; Compiler.bDest = true;
Compiler.bAlignVector = false; Compiler.bAlignVector = false;
Compiler.bFlags = true; Compiler.bFlags = true;
Compiler.bReOrdering = true; Compiler.bReOrdering = false;
Compiler.bSections = true; Compiler.bSections = false;
Compiler.bAccum = true; Compiler.bAccum = true;
Compiler.bGPRConstants = true; Compiler.bGPRConstants = true;
DetectCpuSpecs(); DetectCpuSpecs();

276
Source/Project64-rsp-core/Recompiler/RspRecompilerSections.cpp
View File

@ -196,282 +196,6 @@ void RSP_Sections_VMUDL(RSPOpcode RspOp, uint32_t AccumStyle)
} }
} }
void RSP_Sections_VMADL(RSPOpcode RspOp, uint32_t AccumStyle)
{
char Reg[256];
// VMADL - affects the lower 16-bits
if (AccumStyle != Low16BitAccum)
{
return;
}
RSPOpC = RspOp;
// Load source registers
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM0 + 2, &RSP_Vect[RspOp.rd].s16(0), Reg);
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM1 + 2, &RSP_Vect[RspOp.rd].s16(4), Reg);
// VMADL
if ((RspOp.rs & 0x0f) < 2)
{
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rt);
MmxMoveQwordVariableToReg(x86_MM2 + 2, &RSP_Vect[RspOp.rt].s16(0), Reg);
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rt);
MmxMoveQwordVariableToReg(x86_MM3 + 2, &RSP_Vect[RspOp.rt].s16(4), Reg);
MmxPmullwRegToReg(x86_MM0 + 2, x86_MM2 + 2);
MmxPmullwRegToReg(x86_MM1 + 2, x86_MM3 + 2);
}
else if ((RspOp.rs & 0x0f) >= 8)
{
RSP_Element2Mmx(x86_MM2);
MmxPmullwRegToReg(x86_MM0 + 2, x86_MM2 + 2);
MmxPmullwRegToReg(x86_MM1 + 2, x86_MM2 + 2);
}
else
{
RSP_MultiElement2Mmx(x86_MM2 + 2, x86_MM3 + 2);
MmxPmullwRegToReg(x86_MM0 + 2, x86_MM2 + 2);
MmxPmullwRegToReg(x86_MM1 + 2, x86_MM3 + 2);
}
MmxPaddswRegToReg(x86_MM0, x86_MM0 + 2);
MmxPaddswRegToReg(x86_MM1, x86_MM1 + 2);
}
void RSP_Sections_VMUDM(RSPOpcode RspOp, uint32_t AccumStyle)
{
char Reg[256];
// VMUDM - affects the middle 32-bits, s16*u16
if (AccumStyle == High16BitAccum)
{
MmxXorRegToReg(x86_MM0, x86_MM0);
MmxXorRegToReg(x86_MM1, x86_MM1);
return;
}
RSPOpC = RspOp;
// Load source registers
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM0, &RSP_Vect[RspOp.rd].s16(0), Reg);
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM1, &RSP_Vect[RspOp.rd].s16(4), Reg);
// VMUDM
if (AccumStyle != Middle16BitAccum)
{
if ((RspOp.rs & 0x0f) < 2)
{
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rt);
MmxMoveQwordVariableToReg(x86_MM2, &RSP_Vect[RspOp.rt].s16(0), Reg);
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rt);
MmxMoveQwordVariableToReg(x86_MM3, &RSP_Vect[RspOp.rt].s16(4), Reg);
MmxPmullwRegToReg(x86_MM0, x86_MM2);
MmxPmullwRegToReg(x86_MM1, x86_MM3);
}
else if ((RspOp.rs & 0x0f) >= 8)
{
RSP_Element2Mmx(x86_MM2);
MmxPmullwRegToReg(x86_MM0, x86_MM2);
MmxPmullwRegToReg(x86_MM1, x86_MM2);
}
else
{
RSP_MultiElement2Mmx(x86_MM2, x86_MM3);
MmxPmullwRegToReg(x86_MM0, x86_MM2);
MmxPmullwRegToReg(x86_MM1, x86_MM3);
}
}
else
{
if ((RSPOpC.rs & 0xF) < 2)
{
sprintf(Reg, "RSP_Vect[%i].UHW[0]", RSPOpC.rt);
MmxMoveQwordVariableToReg(x86_MM4, &RSP_Vect[RSPOpC.vt].u16(0), Reg);
sprintf(Reg, "RSP_Vect[%i].UHW[4]", RSPOpC.rt);
MmxMoveQwordVariableToReg(x86_MM5, &RSP_Vect[RSPOpC.vt].u16(4), Reg);
// Copy the signed portion
MmxMoveRegToReg(x86_MM2, x86_MM0);
MmxMoveRegToReg(x86_MM3, x86_MM1);
// high((u16)a * b)
MmxPmulhuwRegToReg(x86_MM0, x86_MM4);
MmxPmulhuwRegToReg(x86_MM1, x86_MM5);
// low((a >> 15) * b)
MmxPsrawImmed(x86_MM2, 15);
MmxPsrawImmed(x86_MM3, 15);
MmxPmullwRegToReg(x86_MM2, x86_MM4);
MmxPmullwRegToReg(x86_MM3, x86_MM5);
}
else if ((RSPOpC.rs & 0xF) >= 8)
{
RSP_Element2Mmx(x86_MM4);
// Copy the signed portion
MmxMoveRegToReg(x86_MM2, x86_MM0);
MmxMoveRegToReg(x86_MM3, x86_MM1);
// high((u16)a * b)
MmxPmulhuwRegToReg(x86_MM0, x86_MM4);
MmxPmulhuwRegToReg(x86_MM1, x86_MM4);
// low((a >> 15) * b)
MmxPsrawImmed(x86_MM2, 15);
MmxPsrawImmed(x86_MM3, 15);
MmxPmullwRegToReg(x86_MM2, x86_MM4);
MmxPmullwRegToReg(x86_MM3, x86_MM4);
}
else
{
RSP_MultiElement2Mmx(x86_MM4, x86_MM5);
// Copy the signed portion
MmxMoveRegToReg(x86_MM2, x86_MM0);
MmxMoveRegToReg(x86_MM3, x86_MM1);
// high((u16)a * b)
MmxPmulhuwRegToReg(x86_MM0, x86_MM4);
MmxPmulhuwRegToReg(x86_MM1, x86_MM5);
// low((a >> 15) * b)
MmxPsrawImmed(x86_MM2, 15);
MmxPsrawImmed(x86_MM3, 15);
MmxPmullwRegToReg(x86_MM2, x86_MM4);
MmxPmullwRegToReg(x86_MM3, x86_MM5);
}
// Add them up
MmxPaddwRegToReg(x86_MM0, x86_MM2);
MmxPaddwRegToReg(x86_MM1, x86_MM3);
}
}
void RSP_Sections_VMADM(RSPOpcode RspOp, uint32_t AccumStyle)
{
char Reg[256];
// VMADM - affects the middle 32-bits, s16*u16
if (AccumStyle == High16BitAccum)
{
MmxXorRegToReg(x86_MM0, x86_MM0);
MmxXorRegToReg(x86_MM1, x86_MM1);
return;
}
RSPOpC = RspOp;
// Load source registers
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM0 + 2, &RSP_Vect[RspOp.rd].s16(0), Reg);
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rd);
MmxMoveQwordVariableToReg(x86_MM1 + 2, &RSP_Vect[RspOp.rd].s16(4), Reg);
// VMADM
if (AccumStyle != Middle16BitAccum)
{
if ((RspOp.rs & 0x0f) < 2)
{
sprintf(Reg, "RSP_Vect[%i].HW[0]", RspOp.rt);
MmxMoveQwordVariableToReg(x86_MM2 + 2, &RSP_Vect[RspOp.rt].s16(0), Reg);
sprintf(Reg, "RSP_Vect[%i].HW[4]", RspOp.rt);
MmxMoveQwordVariableToReg(x86_MM3 + 2, &RSP_Vect[RspOp.rt].s16(4), Reg);
MmxPmullwRegToReg(x86_MM0 + 2, x86_MM2 + 2);
MmxPmullwRegToReg(x86_MM1 + 2, x86_MM3 + 2);
}
else if ((RspOp.rs & 0x0f) >= 8)
{
RSP_Element2Mmx(x86_MM2 + 2);
MmxPmullwRegToReg(x86_MM0 + 2, x86_MM2 + 2);
MmxPmullwRegToReg(x86_MM1 + 2, x86_MM2 + 2);
}
else
{
RSP_MultiElement2Mmx(x86_MM2 + 2, x86_MM3 + 2);
MmxPmullwRegToReg(x86_MM0 + 2, x86_MM2 + 2);
MmxPmullwRegToReg(x86_MM1 + 2, x86_MM3 + 2);
}
}
else
{
if ((RSPOpC.rs & 0xF) < 2)
{
sprintf(Reg, "RSP_Vect[%i].UHW[0]", RSPOpC.rt);
MmxMoveQwordVariableToReg(x86_MM4 + 2, &RSP_Vect[RSPOpC.vt].u16(0), Reg);
sprintf(Reg, "RSP_Vect[%i].UHW[4]", RSPOpC.rt);
MmxMoveQwordVariableToReg(x86_MM5 + 2, &RSP_Vect[RSPOpC.vt].u16(4), Reg);
// Copy the signed portion
MmxMoveRegToReg(x86_MM2 + 2, x86_MM0 + 2);
MmxMoveRegToReg(x86_MM3 + 2, x86_MM1 + 2);
// high((u16)a * b)
MmxPmulhuwRegToReg(x86_MM0 + 2, x86_MM4 + 2);
MmxPmulhuwRegToReg(x86_MM1 + 2, x86_MM5 + 2);
// low((a >> 15) * b)
MmxPsrawImmed(x86_MM2 + 2, 15);
MmxPsrawImmed(x86_MM3 + 2, 15);
MmxPmullwRegToReg(x86_MM2 + 2, x86_MM4 + 2);
MmxPmullwRegToReg(x86_MM3 + 2, x86_MM5 + 2);
}
else if ((RSPOpC.rs & 0xF) >= 8)
{
RSP_Element2Mmx(x86_MM4 + 2);
// Copy the signed portion
MmxMoveRegToReg(x86_MM2 + 2, x86_MM0 + 2);
MmxMoveRegToReg(x86_MM3 + 2, x86_MM1 + 2);
// high((u16)a * b)
MmxPmulhuwRegToReg(x86_MM0 + 2, x86_MM4 + 2);
MmxPmulhuwRegToReg(x86_MM1 + 2, x86_MM4 + 2);
// low((a >> 15) * b)
MmxPsrawImmed(x86_MM2 + 2, 15);
MmxPsrawImmed(x86_MM3 + 2, 15);
MmxPmullwRegToReg(x86_MM2 + 2, x86_MM4 + 2);
MmxPmullwRegToReg(x86_MM3 + 2, x86_MM4 + 2);
}
else
{
RSP_MultiElement2Mmx(x86_MM4 + 2, x86_MM5 + 2);
// Copy the signed portion
MmxMoveRegToReg(x86_MM2 + 2, x86_MM0 + 2);
MmxMoveRegToReg(x86_MM3 + 2, x86_MM1 + 2);
// high((u16)a * b)
MmxPmulhuwRegToReg(x86_MM0 + 2, x86_MM4 + 2);
MmxPmulhuwRegToReg(x86_MM1 + 2, x86_MM5 + 2);
// low((a >> 15) * b)
MmxPsrawImmed(x86_MM2 + 2, 15);
MmxPsrawImmed(x86_MM3 + 2, 15);
MmxPmullwRegToReg(x86_MM2 + 2, x86_MM4 + 2);
MmxPmullwRegToReg(x86_MM3 + 2, x86_MM5 + 2);
}
// Add them up
MmxPaddwRegToReg(x86_MM0 + 2, x86_MM2 + 2);
MmxPaddwRegToReg(x86_MM1 + 2, x86_MM3 + 2);
}
MmxPaddswRegToReg(x86_MM0, x86_MM0 + 2);
MmxPaddswRegToReg(x86_MM1, x86_MM1 + 2);
}
void RSP_Sections_VMUDN(RSPOpcode RspOp, uint32_t AccumStyle) void RSP_Sections_VMUDN(RSPOpcode RspOp, uint32_t AccumStyle)
{ {
char Reg[256]; char Reg[256];