ShuriZma
/
project64
mirror of https://github.com/project64/project64.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Core: Add BGEZALL to interrupter

This commit is contained in:
zilmar 2022-08-15 10:18:51 +09:30
parent e724595ac2
commit 71ddfd885d
2 changed files with 17 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
Source/Project64-core/N64System/Interpreter/InterpreterOps.cpp
View File

@ -259,7 +259,7 @@ R4300iOp::Func * R4300iOp::BuildInterpreter()
Jump_Regimm[16] = REGIMM_BLTZAL;
Jump_Regimm[17] = REGIMM_BGEZAL;
Jump_Regimm[18] = UnknownOpcode;
Jump_Regimm[19] = UnknownOpcode;
Jump_Regimm[19] = REGIMM_BGEZALL;
Jump_Regimm[20] = UnknownOpcode;
Jump_Regimm[21] = UnknownOpcode;
Jump_Regimm[22] = UnknownOpcode;
@ -1813,6 +1813,21 @@ void R4300iOp::REGIMM_BGEZAL()
_GPR[31].DW = (int32_t)((*_PROGRAM_COUNTER) + 8);
}
void R4300iOp::REGIMM_BGEZALL()
{
g_System->m_PipelineStage = PIPELINE_STAGE_DELAY_SLOT;
if (_GPR[m_Opcode.rs].DW >= 0)
{
g_System->m_JumpToLocation = (*_PROGRAM_COUNTER) + ((int16_t)m_Opcode.offset << 2) + 4;
}
else
{
g_System->m_PipelineStage = PIPELINE_STAGE_JUMP;
g_System->m_JumpToLocation = (*_PROGRAM_COUNTER) + 8;
}
_GPR[31].DW = (int32_t)((*_PROGRAM_COUNTER) + 8);
}
void R4300iOp::REGIMM_TEQI()
{
if (_GPR[m_Opcode.rs].DW == (int64_t)((int16_t)m_Opcode.immediate))

1
Source/Project64-core/N64System/Interpreter/InterpreterOps.h
View File

@ -121,6 +121,7 @@ public:
static void REGIMM_BGEZL();
static void REGIMM_BLTZAL();
static void REGIMM_BGEZAL();
static void REGIMM_BGEZALL();
static void REGIMM_TEQI();
static void REGIMM_TGEI();
static void REGIMM_TGEIU();