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Merge pull request #122 from death-droid/NrageChanges 

NRage GBCart, use actual address ranges rather than hacky method. No rea...
This commit is contained in:
zilmar 2015-02-24 05:26:27 +11:00
parent 2d09e15b50 1340e6fea5
commit 67deab4699
1 changed files with 208 additions and 138 deletions
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346
Source/nragev20/GBCart.cpp
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@ -535,8 +535,10 @@ bool WriteCartNorm(LPGBCART Cart, WORD dwAddress, BYTE *Data)
return true;
}
if (Cart->RomData[0x149] == 1) { // Whoops... Only 1/4 of the RAM space is used.
if ((dwAddress >= 0xA000) && (dwAddress <= 0xA7FF)) { // Write to RAM
if (Cart->RomData[0x149] == 1)
{ // Whoops... Only 1/4 of the RAM space is used.
if ((dwAddress >= 0xA000) && (dwAddress <= 0xA7FF))
{ // Write to RAM
DebugWriteA("RAM write: Unbanked\n");
CopyMemory(&Cart->RamData[dwAddress - 0xA000], Data, 32);
}
@ -544,8 +546,11 @@ bool WriteCartNorm(LPGBCART Cart, WORD dwAddress, BYTE *Data)
{
DebugWriteA("RAM write: Unbanked (out of range!)\n");
}
} else {
if ((dwAddress >= 0xA000) && (dwAddress <= 0xBFFF)) { // Write to RAM
}
else
{
if ((dwAddress >= 0xA000) && (dwAddress <= 0xBFFF))
{ // Write to RAM
DebugWriteA("RAM write: Unbanked\n");
CopyMemory(&Cart->RamData[dwAddress - 0xA000], Data, 32);
}
@ -556,15 +561,13 @@ bool WriteCartNorm(LPGBCART Cart, WORD dwAddress, BYTE *Data)
// Done
bool ReadCartMBC1(LPGBCART Cart, WORD dwAddress, BYTE *Data)
{
switch (dwAddress >> 13)
if ((dwAddress >= 0) && (dwAddress <= 0x3FFF))
{
case 0:
case 1: // if ((dwAddress >= 0) && (dwAddress <= 0x3FFF))
CopyMemory(Data, &Cart->RomData[dwAddress], 32);
DebugWriteA("Nonbanked ROM read - MBC1\n");
break;
case 2:
case 3: // else if ((dwAddress >= 0x4000) && (dwAddress <= 0x7FFF))
}
else if ((dwAddress >= 0x4000) && (dwAddress <= 0x7FFF))
{
if (Cart->iCurrentRomBankNo >= Cart->iNumRomBanks)
{
ZeroMemory(Data, 32);
@ -576,22 +579,30 @@ bool ReadCartMBC1(LPGBCART Cart, WORD dwAddress, BYTE *Data)
CopyMemory(Data, &Cart->RomData[dwAddress - 0x4000 + (Cart->iCurrentRomBankNo << 14)], 32);
DebugWriteA("Banked ROM read: Bank %02X\n", Cart->iCurrentRomBankNo);
}
break;
case 5: // else if ((dwAddress >= 0xA000) && (dwAddress <= 0xBFFF))
if (Cart->bHasRam){ // && Cart->bRamEnableState) {
if (Cart->iCurrentRamBankNo >= Cart->iNumRamBanks) {
}
else if ((dwAddress >= 0xA000) && (dwAddress <= 0xBFFF))
{
if (Cart->bHasRam)
{ // && Cart->bRamEnableState) {
if (Cart->iCurrentRamBankNo >= Cart->iNumRamBanks)
{
ZeroMemory(Data, 32);
DebugWriteA("Failed RAM read: (Banking Error) %02X\n", Cart->iCurrentRamBankNo);
} else {
}
else
{
CopyMemory(Data, &Cart->RamData[dwAddress - 0xA000 + (Cart->iCurrentRamBankNo << 13)], 32);
DebugWriteA("RAM read: Bank %02X\n", Cart->iCurrentRamBankNo);
}
} else {
}
else
{
ZeroMemory(Data, 32);
DebugWriteA("Failed RAM read: (RAM not present)\n");
}
break;
default:
}
else
{
DebugWriteA("Bad read from MBC1 cart, address %04X\n", dwAddress);
}
@ -601,37 +612,43 @@ bool ReadCartMBC1(LPGBCART Cart, WORD dwAddress, BYTE *Data)
// Done
bool WriteCartMBC1(LPGBCART Cart, WORD dwAddress, BYTE *Data)
{
switch (dwAddress >> 13)
if ((dwAddress >= 0x0000) && (dwAddress <= 0x1FFF)) // RAM enable
{
case 0: // if ((dwAddress >= 0) && (dwAddress <= 0x1FFF)) // RAM enable
Cart->bRamEnableState = (Data[0] == 0x0A);
DebugWriteA("Set RAM enable: %d\n", Cart->bRamEnableState);
break;
case 1: // else if ((dwAddress >= 0x2000) && (dwAddress <= 0x3FFF)) // ROM bank select
}
else if ((dwAddress >= 0x2000) && (dwAddress <= 0x3FFF)) // ROM bank select
{
Cart->iCurrentRomBankNo &= 0x60; // keep MSB
Cart->iCurrentRomBankNo |= Data[0] & 0x1F;
// emulate quirk: 0x00 -> 0x01, 0x20 -> 0x21, 0x40->0x41, 0x60 -> 0x61
if ((Cart->iCurrentRomBankNo & 0x1F) == 0) {
if ((Cart->iCurrentRomBankNo & 0x1F) == 0)
{
Cart->iCurrentRomBankNo |= 0x01;
}
DebugWriteA("Set ROM Bank: %02X\n", Cart->iCurrentRomBankNo);
break;
case 2: // else if ((dwAddress >= 0x4000) && (dwAddress <= 0x5FFF)) // RAM bank select
if (Cart->bMBC1RAMbanking) {
}
else if ((dwAddress >= 0x4000) && (dwAddress <= 0x5FFF)) // RAM bank select
{
if (Cart->bMBC1RAMbanking)
{
Cart->iCurrentRamBankNo = Data[0] & 0x03;
DebugWriteA("Set RAM Bank: %02X\n", Cart->iCurrentRamBankNo);
}
else {
else
{
Cart->iCurrentRomBankNo &= 0x1F;
Cart->iCurrentRomBankNo |= ((Data[0] & 0x03) << 5); // set bits 5 and 6 of ROM bank
DebugWriteA("Set ROM Bank MSB, ROM bank now: %02X\n", Cart->iCurrentRomBankNo);
}
break;
case 3: // else if ((dwAddress >= 0x6000) && (dwAddress <= 0x7FFF)) // MBC1 mode select
}
else if ((dwAddress >= 0x6000) && (dwAddress <= 0x7FFF)) // MBC1 mode select
{
// this is overly complicated, but it keeps us from having to do bitwise math later
// Basically we shuffle the 2 "magic bits" between iCurrentRomBankNo and iCurrentRamBankNo as necessary.
if (Cart->bMBC1RAMbanking != (Data[0] & 0x01)) {
if (Cart->bMBC1RAMbanking != (Data[0] & 0x01))
{
// we should only alter the ROM and RAM bank numbers if we have changed modes
Cart->bMBC1RAMbanking = Data[0] & 0x01;
if (Cart->bMBC1RAMbanking)
@ -645,15 +662,15 @@ bool WriteCartMBC1(LPGBCART Cart, WORD dwAddress, BYTE *Data)
Cart->iCurrentRomBankNo |= (Cart->iCurrentRamBankNo << 5);
Cart->iCurrentRamBankNo = 0x00; // we can only reach RAM page 0
}
DebugWriteA("Set MBC1 mode: %s\n", Cart->bMBC1RAMbanking ? "ROMbanking" : "RAMbanking" );
DebugWriteA("Set MBC1 mode: %s\n", Cart->bMBC1RAMbanking ? "ROMbanking" : "RAMbanking");
}
else
{
DebugWriteA("Already in MBC1 mode: %s\n", Cart->bMBC1RAMbanking ? "ROMbanking" : "RAMbanking" );
DebugWriteA("Already in MBC1 mode: %s\n", Cart->bMBC1RAMbanking ? "ROMbanking" : "RAMbanking");
}
break;
case 5: // else if ((dwAddress >= 0xA000) && (dwAddress <= 0xBFFF)) // Write to RAM
}
else if ((dwAddress >= 0xA000) && (dwAddress <= 0xBFFF)) // Write to RAM
{
if (Cart->bHasRam) // && Cart->bRamEnableState)
{
DebugWriteA("RAM write: Bank %02X\n", Cart->iCurrentRamBankNo);
@ -663,8 +680,9 @@ bool WriteCartMBC1(LPGBCART Cart, WORD dwAddress, BYTE *Data)
{
DebugWriteA("Failed RAM write: (RAM not present)\n");
}
break;
default:
}
else
{
DebugWriteA("Bad write to MBC1 cart, address %04X\n", dwAddress);
}
@ -674,33 +692,39 @@ bool WriteCartMBC1(LPGBCART Cart, WORD dwAddress, BYTE *Data)
// Done
bool ReadCartMBC2(LPGBCART Cart, WORD dwAddress, BYTE *Data)
{
switch (dwAddress >> 13)
if ((dwAddress <= 0x3FFF))
{
case 0:
case 1: // if ((dwAddress <= 0x3FFF))
CopyMemory(Data, &Cart->RomData[dwAddress], 32);
DebugWriteA("Nonbanked ROM read - MBC2\n");
break;
case 2:
case 3: // else if ((dwAddress >= 0x4000) && (dwAddress <= 0x7FFF))
if (Cart->iCurrentRomBankNo >= Cart->iNumRomBanks) {
}
else if ((dwAddress >= 0x4000) && (dwAddress <= 0x7FFF))
{
if (Cart->iCurrentRomBankNo >= Cart->iNumRomBanks)
{
ZeroMemory(Data, 32);
DebugWriteA("Banked ROM read: (Banking Error) %02X\n", Cart->iCurrentRomBankNo);
} else {
}
else
{
CopyMemory(Data, &Cart->RomData[dwAddress - 0x4000 + (Cart->iCurrentRomBankNo << 14)], 32);
DebugWriteA("Banked ROM read: Bank %02X\n", Cart->iCurrentRomBankNo);
}
break;
case 5: // else if ((dwAddress >= 0xA000) && (dwAddress <= 0xBFFF))
if (Cart->bHasRam && Cart->bRamEnableState) {
}
else if ((dwAddress >= 0xA000) && (dwAddress <= 0xBFFF))
{
if (Cart->bHasRam && Cart->bRamEnableState)
{
CopyMemory(Data, &Cart->RamData[dwAddress - 0xA000], 32);
DebugWriteA("RAM read: Unbanked\n");
} else {
}
else
{
ZeroMemory(Data, 32);
DebugWriteA("Failed RAM read: (RAM not present or not active)\n");
}
break;
default:
}
else
{
DebugWriteA("Bad read from MBC2 cart, address %04X\n", dwAddress);
}
@ -710,32 +734,37 @@ bool ReadCartMBC2(LPGBCART Cart, WORD dwAddress, BYTE *Data)
// Done
bool WriteCartMBC2(LPGBCART Cart, WORD dwAddress, BYTE *Data)
{
switch (dwAddress >> 13)
if ((dwAddress >= 0x0000) && (dwAddress <= 0x1FFF)) // We shouldn't be able to read/write to RAM unless this is toggled on
{
case 0: // if ((dwAddress <= 0x1FFF)) // We shouldn't be able to read/write to RAM unless this is toggled on
Cart->bRamEnableState = (Data[0] == 0x0A);
DebugWriteA("Set RAM enable: %d\n", Cart->bRamEnableState);
break;
case 1: // else if ((dwAddress >= 0x2000) && (dwAddress <= 0x3FFF)) // ROM bank select
}
else if ((dwAddress >= 0x2000) && (dwAddress <= 0x3FFF)) // ROM bank select
{
Cart->iCurrentRomBankNo = Data[0] & 0x0F;
if (Cart->iCurrentRomBankNo == 0) {
Cart->iCurrentRomBankNo = 1;
}
DebugWriteA("Set ROM Bank: %02X\n", Cart->iCurrentRomBankNo);
break;
case 2: // if ((dwAddress >= 0x4000) && (dwAddress <= 0x5FFF)) // RAM bank select
if (Cart->bHasRam) {
}
else if ((dwAddress >= 0x4000) && (dwAddress <= 0x5FFF)) // RAM bank select
{
if (Cart->bHasRam)
{
Cart->iCurrentRamBankNo = Data[0] & 0x07;
DebugWriteA("Set RAM Bank: %02X\n", Cart->iCurrentRamBankNo);
}
break;
case 5: // else if ((dwAddress >= 0xA000) && (dwAddress <= 0xBFFF) && Cart->bRamEnableState) // Write to RAM
if (Cart->bHasRam) {
}
else if ((dwAddress >= 0xA000) && (dwAddress <= 0xBFFF) && Cart->bRamEnableState) // Write to RAM
{
if (Cart->bHasRam)
{
DebugWriteA("RAM write: Bank %02X\n", Cart->iCurrentRamBankNo);
CopyMemory(&Cart->RamData[dwAddress - 0xA000 + (Cart->iCurrentRamBankNo << 13)], Data, 32);
}
break;
default:
}
else
{
DebugWriteA("Bad write to MBC2 cart, address %04X\n", dwAddress);
}
@ -745,43 +774,50 @@ bool WriteCartMBC2(LPGBCART Cart, WORD dwAddress, BYTE *Data)
// Done
bool ReadCartMBC3(LPGBCART Cart, WORD dwAddress, BYTE *Data)
{
int i;
switch (dwAddress >> 13)
if ((dwAddress < 0x4000)) //Rom Bank 0
{
case 0:
case 1: // if ((dwAddress <= 0x3FFF))
CopyMemory(Data, &Cart->RomData[dwAddress], 32);
DebugWriteA("Nonbanked ROM read - MBC3\n");
break;
case 2:
case 3: // else if ((dwAddress >= 0x4000) && (dwAddress <= 0x7FFF))
if (Cart->iCurrentRomBankNo >= Cart->iNumRomBanks) {
}
else if ((dwAddress >= 0x4000) && (dwAddress < 0x8000)) //Switchable Rom Bank
{
if (Cart->iCurrentRomBankNo >= Cart->iNumRomBanks)
{
ZeroMemory(Data, 32);
DebugWriteA("Banked ROM read: (Banking Error) %02X\n", Cart->iCurrentRomBankNo);
} else {
}
else
{
CopyMemory(Data, &Cart->RomData[dwAddress - 0x4000 + (Cart->iCurrentRomBankNo * 0x4000)], 32);
DebugWriteA("Banked ROM read: Bank %02X\n", Cart->iCurrentRomBankNo);
}
break;
case 5: // else if ((dwAddress >= 0xA000) && (dwAddress <= 0xBFFF))
if (Cart->bHasTimer && (Cart->iCurrentRamBankNo >= 0x08 && Cart->iCurrentRamBankNo <= 0x0c)) {
}
else if ((dwAddress >= 0xA000) && (dwAddress <= 0xC000)) //Upper Bounds of memory map
{
if (Cart->bHasTimer && (Cart->iCurrentRamBankNo >= 0x08 && Cart->iCurrentRamBankNo <= 0x0c))
{
// w00t! the Timer was just read!!
if (Cart->TimerDataLatched) {
for (i=0; i<32; i++)
if (Cart->TimerDataLatched)
{
for (int i = 0; i < 32; i++)
Data[i] = Cart->LatchedTimerData[Cart->iCurrentRamBankNo - 0x08];
} else {
}
else
{
UpdateRTC(Cart);
for (i=0; i<32; i++)
for (int i = 0; i < 32; i++)
Data[i] = Cart->TimerData[Cart->iCurrentRamBankNo - 0x08];
}
}
else if (Cart->bHasRam) {
if (Cart->iCurrentRamBankNo >= Cart->iNumRamBanks) {
else if (Cart->bHasRam)
{
if (Cart->iCurrentRamBankNo >= Cart->iNumRamBanks)
{
ZeroMemory(Data, 32);
DebugWriteA("Failed RAM read: (Banking Error) %02X\n", Cart->iCurrentRamBankNo);
}
else {
else
{
CopyMemory(Data, &Cart->RamData[dwAddress - 0xA000 + (Cart->iCurrentRamBankNo * 0x2000)], 32);
DebugWriteA("RAM read: Bank %02X\n", Cart->iCurrentRamBankNo);
}
@ -790,12 +826,15 @@ bool ReadCartMBC3(LPGBCART Cart, WORD dwAddress, BYTE *Data)
// //for (i=0; i<32; i++) Data[i] = 0;
// DebugWriteA("Failed RAM read: (RAM not active)\n");
//}
} else {
}
else
{
ZeroMemory(Data, 32);
DebugWriteA("Failed RAM read: (RAM not present)\n");
}
break;
default:
}
else
{
DebugWriteA("Bad read from MBC3 cart, address %04X\n", dwAddress);
}
@ -807,56 +846,69 @@ bool WriteCartMBC3(LPGBCART Cart, WORD dwAddress, BYTE *Data)
{
int i;
switch (dwAddress >> 13)
if ((dwAddress >= 0x0000) && (dwAddress <= 0x1FFF)) // We shouldn't be able to read/write to RAM unless this is toggled on
{
case 0: // if ((dwAddress <= 0x1FFF)) // We shouldn't be able to read/write to RAM unless this is toggled on
Cart->bRamEnableState = (Data[0] == 0x0A);
DebugWriteA("Set RAM enable: %d\n", Cart->bRamEnableState);
break;
case 1: // else if ((dwAddress >= 0x2000) && (dwAddress <= 0x3FFF)) // ROM bank select
}
else if ((dwAddress >= 0x2000) && (dwAddress <= 0x3FFF)) // ROM bank select
{
Cart->iCurrentRomBankNo = Data[0] & 0x7F;
if (Cart->iCurrentRomBankNo == 0) {
Cart->iCurrentRomBankNo = 1;
}
DebugWriteA("Set Rom Bank: %02X\n", Cart->iCurrentRomBankNo);
break;
case 2: // if ((dwAddress >= 0x4000) && (dwAddress <= 0x5FFF)) // RAM/Clock bank select
if (Cart->bHasRam) {
}
else if ((dwAddress >= 0x4000) && (dwAddress <= 0x5FFF)) // RAM/Clock bank select
{
if (Cart->bHasRam)
{
Cart->iCurrentRamBankNo = Data[0] & 0x03;
DebugWriteA("Set RAM Bank: %02X\n", Cart->iCurrentRamBankNo);
if (Cart->bHasTimer && (Data[0] >= 0x08 && Data[0] <= 0x0c)) {
if (Cart->bHasTimer && (Data[0] >= 0x08 && Data[0] <= 0x0c))
{
// Set the bank for the timer
Cart->iCurrentRamBankNo = Data[0];
}
}
break;
case 3: // else if ((dwAddress >= 0x6000) && (dwAddress <= 0x7FFF)) // Latch timer data
}
else if ((dwAddress >= 0x6000) && (dwAddress <= 0x7FFF)) // Latch timer data
{
CopyMemory(Cart->LatchedTimerData, Cart->TimerData, 5 * sizeof(Cart->TimerData[0]));
if (Data[0] & 1) {
if (Data[0] & 1)
{
// Update timer, save latch values, and set latch state
UpdateRTC(Cart);
for (i=0; i<4; i++)
for (i = 0; i < 4; i++)
Cart->LatchedTimerData[i] = Cart->TimerData[i];
Cart->TimerDataLatched = true;
DebugWriteA("Timer Data Latch: Enable\n");
} else {
}
else
{
Cart->TimerDataLatched = false;
DebugWriteA("Timer Data Latch: Disable\n");
}
break;
case 5: // else if ((dwAddress >= 0xA000) && (dwAddress <= 0xBFFF)) // Write to RAM
if (Cart->bHasRam) {
if (Cart->iCurrentRamBankNo >= 0x08 && Cart->iCurrentRamBankNo <= 0x0c) {
}
else if ((dwAddress >= 0xA000) && (dwAddress <= 0xBFFF)) // Write to RAM
{
if (Cart->bHasRam)
{
if (Cart->iCurrentRamBankNo >= 0x08 && Cart->iCurrentRamBankNo <= 0x0c)
{
// Write to the timer
DebugWriteA("Timer write: Bank %02X\n", Cart->iCurrentRamBankNo);
Cart->TimerData[Cart->iCurrentRamBankNo - 0x08] = Data[0];
} else {
}
else
{
DebugWriteA("RAM write: Bank %02X%s\n", Cart->iCurrentRamBankNo, Cart->bRamEnableState ? "" : " -- NOT ENABLED (but wrote anyway)");
CopyMemory(&Cart->RamData[dwAddress - 0xA000 + (Cart->iCurrentRamBankNo * 0x2000)], Data, 32);
}
}
break;
default:
}
else
{
DebugWriteA("Bad write to MBC3 cart, address %04X\n", dwAddress);
}
@ -866,42 +918,51 @@ bool WriteCartMBC3(LPGBCART Cart, WORD dwAddress, BYTE *Data)
// Done
bool ReadCartMBC5(LPGBCART Cart, WORD dwAddress, BYTE *Data)
{
switch (dwAddress >> 13)
if ((dwAddress < 0x4000)) //Rom Bank 0
{
case 0:
case 1: // if ((dwAddress <= 0x3FFF))
CopyMemory(Data, &Cart->RomData[dwAddress], 32);
DebugWriteA("Nonbanked ROM read - MBC5\n");
break;
case 2:
case 3: // else if ((dwAddress >= 0x4000) && (dwAddress <= 0x7FFF))
if (Cart->iCurrentRomBankNo >= Cart->iNumRomBanks) {
}
else if ((dwAddress >= 0x4000) && (dwAddress < 0x8000)) //Switchable ROM BANK
{
if (Cart->iCurrentRomBankNo >= Cart->iNumRomBanks)
{
ZeroMemory(Data, 32);
DebugWriteA("Banked ROM read: (Banking Error)");
DebugWriteByteA(Cart->iCurrentRomBankNo);
DebugWriteA("\n");
} else {
}
else {
CopyMemory(Data, &Cart->RomData[dwAddress - 0x4000 + (Cart->iCurrentRomBankNo << 14)], 32);
DebugWriteA("Banked ROM read: Bank=");
DebugWriteByteA(Cart->iCurrentRomBankNo);
DebugWriteA("\n");
}
break;
case 5: // else if ((dwAddress >= 0xA000) && (dwAddress <= 0xBFFF))
if (Cart->bHasRam) {
if (Cart->iCurrentRamBankNo >= Cart->iNumRamBanks) {
}
else if ((dwAddress >= 0xA000) && (dwAddress <= 0xC000)) //Upper bounds of memory map
{
if (Cart->bHasRam)
{
if (Cart->iCurrentRamBankNo >= Cart->iNumRamBanks)
{
ZeroMemory(Data, 32);
DebugWriteA("Failed RAM read: (Banking Error) %02X\n", Cart->iCurrentRamBankNo);
} else {
}
else
{
CopyMemory(Data, &Cart->RamData[dwAddress - 0xA000 + (Cart->iCurrentRamBankNo << 13)], 32);
DebugWriteA("RAM read: Bank %02X\n", Cart->iCurrentRamBankNo);
}
} else {
}
else
{
ZeroMemory(Data, 32);
DebugWriteA("Failed RAM read: (RAM Not Present)\n");
}
break;
default:
}
else
{
DebugWriteA("Bad read from MBC5 cart, address %04X\n", dwAddress);
}
@ -911,43 +972,52 @@ bool ReadCartMBC5(LPGBCART Cart, WORD dwAddress, BYTE *Data)
// Done
bool WriteCartMBC5(LPGBCART Cart, WORD dwAddress, BYTE *Data)
{
switch (dwAddress >> 13)
if ((dwAddress >= 0x0000) && (dwAddress <= 0x1FFF)) // We shouldn't be able to read/write to RAM unless this is toggled on
{
case 0: // if ((dwAddress <= 0x1FFF)) // We shouldn't be able to read/write to RAM unless this is toggled on
Cart->bRamEnableState = (Data[0] == 0x0A);
DebugWriteA("Set RAM enable: %d\n", Cart->bRamEnableState);
break;
case 1: // else if ((dwAddress >= 0x2000) && (dwAddress <= 0x2FFF)) // ROM bank select, low bits
}
else if ((dwAddress >= 0x2000) && (dwAddress <= 0x2FFF)) // ROM bank select, low bits
{
Cart->iCurrentRomBankNo &= 0xFF00;
Cart->iCurrentRomBankNo |= Data[0];
// Cart->iCurrentRomBankNo = ((int) Data[0]) | (Cart->iCurrentRomBankNo & 0x100);
DebugWriteA("Set ROM Bank: %02X\n", Cart->iCurrentRomBankNo);
break;
case 2: // else if ((dwAddress >= 0x3000) && (dwAddress <= 0x3FFF)) // ROM bank select, high bit
}
else if ((dwAddress >= 0x3000) && (dwAddress <= 0x3FFF)) // ROM bank select, high bit
{
Cart->iCurrentRomBankNo &= 0x00FF;
Cart->iCurrentRomBankNo |= (Data[0] & 0x01) << 8;
// Cart->iCurrentRomBankNo = (Cart->iCurrentRomBankNo & 0xFF) | ((((int) Data[0]) & 1) * 0x100);
DebugWriteA("Set ROM Bank: %02X\n", Cart->iCurrentRomBankNo);
break;
case 3: // if ((dwAddress >= 0x4000) && (dwAddress <= 0x5FFF)) // RAM bank select
if (Cart->bHasRam) {
}
else if ((dwAddress >= 0x4000) && (dwAddress <= 0x5FFF)) // RAM bank select
{
if (Cart->bHasRam)
{
Cart->iCurrentRamBankNo = Data[0] & 0x0F;
DebugWriteA("Set RAM Bank: %02X\n", Cart->iCurrentRamBankNo);
}
break;
case 5: // else if ((dwAddress >= 0xA000) && (dwAddress <= 0xBFFF)) // Write to RAM
if (Cart->bHasRam) {
if (Cart->iCurrentRamBankNo >= Cart->iNumRamBanks) {
}
else if ((dwAddress >= 0xA000) && (dwAddress <= 0xBFFF)) // Write to RAM
{
if (Cart->bHasRam)
{
if (Cart->iCurrentRamBankNo >= Cart->iNumRamBanks)
{
DebugWriteA("RAM write: Buffer error on ");
DebugWriteByteA(Cart->iCurrentRamBankNo);
DebugWriteA("\n");
} else {
}
else
{
DebugWriteA("RAM write: Bank %02X\n", Cart->iCurrentRamBankNo);
CopyMemory(&Cart->RamData[dwAddress - 0xA000 + (Cart->iCurrentRamBankNo << 13)], Data, 32);
}
}
break;
default:
}
else
{
DebugWriteA("Bad write to MBC5 cart, address %04X\n", dwAddress);
}