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RSP: implement SP_SEMAPHORE_REG

This commit is contained in:
zilmar 2013-01-12 08:18:19 +11:00
parent 196b8ee100
commit 5bba8a011a
3 changed files with 7 additions and 7 deletions
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2
Source/RSP/Interpreter CPU.c
View File

@ -459,8 +459,6 @@ DWORD RunInterpreterCPU(DWORD Cycles) {
break;
}
}
*PrgCount -= 4;
return Cycles;
}

6
Source/RSP/Interpreter Ops.c
View File

@ -382,9 +382,9 @@ void RSP_Cop0_MF (void) {
case 5: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.SP_DMA_FULL_REG; break;
case 6: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.SP_DMA_BUSY_REG; break;
case 7:
RSP_GPR[RSPOpC.rt].W = 0;
//RSP_GPR[RSPOpC.rt].W = *RSPInfo.SP_SEMAPHORE_REG;
//*RSPInfo.SP_SEMAPHORE_REG = 1;
RSP_GPR[RSPOpC.rt].W = *RSPInfo.SP_SEMAPHORE_REG;
*RSPInfo.SP_SEMAPHORE_REG = 1;
RSP_Running = FALSE;
break;
case 8: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.DPC_START_REG ; break;
case 9: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.DPC_END_REG ; break;

6
Source/RSP/Recompiler Ops.c
View File

@ -1492,8 +1492,10 @@ void Compile_Cop0_MF ( void ) {
MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
break;
case 7:
MoveConstToVariable(0, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
//Cheat_r4300iOpcode(RSP_Cop0_MF,"RSP_Cop0_MF");
Cheat_r4300iOpcode(RSP_Cop0_MF,"RSP_Cop0_MF");
MoveConstToVariable(CompilePC + 4,PrgCount,"RSP PC");
Ret();
NextInstruction = FINISH_BLOCK;
break;
case 8:
MoveVariableToX86reg(RSPInfo.DPC_START_REG, "DPC_START_REG", x86_EAX);