Update Recompiler Analysis.c
Fix typos, capitalization, punctuation, title case, change multi line comments to single line comments where appropriate, fix abbreviations, add some TODOs, remove some lines, fix spacing, adjust some wording
This commit is contained in:
Derek "Turtle" Roe
parent
a3e301c022
commit
4e7dc1b6f6
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@ -54,7 +54,7 @@ Boolean IsNextInstructionMmx(DWORD PC)
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if ((RspOp.rs & 0x10) != 0) {
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switch (RspOp.funct) {
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case RSP_VECTOR_VMULF:
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case RSP_VECTOR_VMUDL: /* Warning: Not all handled? */
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case RSP_VECTOR_VMUDL: // Warning: Not all handled?
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case RSP_VECTOR_VMUDM:
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case RSP_VECTOR_VMUDN:
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case RSP_VECTOR_VMUDH:
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@ -81,7 +81,7 @@ Boolean IsNextInstructionMmx(DWORD PC)
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case RSP_VECTOR_VADD:
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case RSP_VECTOR_VSUB:
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/* Requires no accumulator write! & No flags! */
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// Requires no accumulator write, and no flags!
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if (WriteToAccum(Low16BitAccum, PC) == TRUE) {
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return FALSE;
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} else if (UseRspFlags(PC) == TRUE) {
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@ -105,7 +105,7 @@ Boolean IsNextInstructionMmx(DWORD PC)
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** TRUE: Accumulation series
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** FALSE: Accumulator is reset after this op
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**
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** Input: PC, Location in accumulator
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** Input: PC, location in accumulator
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*************************************************************/
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#define HIT_BRANCH 0x2
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@ -138,7 +138,7 @@ DWORD WriteToAccum2(int Location, int PC, Boolean RecursiveCall)
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Instruction_State = DO_DELAY_SLOT;
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break;
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default:
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CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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break;
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@ -171,24 +171,24 @@ DWORD WriteToAccum2(int Location, int PC, Boolean RecursiveCall)
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break;
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default:
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CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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break;
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case RSP_J:
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/* there is no way a loopback is going to use accumulator */
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// There is no way a loopback is going to use accumulator
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if (Compiler.bAudioUcode && (((int)(RspOp.target << 2) & 0xFFC) < PC)) {
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return FALSE;
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}
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/* rarely occurs let them have their way */
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// Rarely occurs let them have their way
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else {
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Instruction_State = DO_DELAY_SLOT;
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break;
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}
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case RSP_JAL:
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/* there is no way calling a subroutine is going to use accum */
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/* or come back and continue an existing calculation */
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// There is no way calling a subroutine is going to use an accumulator
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// or come back and continue an existing calculation
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if(Compiler.bAudioUcode) {
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break;
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} else {
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@ -204,11 +204,11 @@ DWORD WriteToAccum2(int Location, int PC, Boolean RecursiveCall)
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if (Compiler.bAudioUcode) {
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OPCODE NextOp;
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/* ignore backward branches and pretend its a nop */
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// Ignore backward branches and pretend it's a NOP
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if (BranchImmed <= 0) {
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break;
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}
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/* if the opcode 8 bytes before the dest is a J backward than ignore this */
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// If the opcode (which is 8 bytes before the destination and also a J backward) then ignore this
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BranchImmed = (PC + ((short)RspOp.offset << 2) + 4) & 0xFFC;
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RSP_LW_IMEM(BranchImmed - 8, &NextOp.Hex);
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if (RspOp.op == RSP_J && (int)(RspOp.target << 2) < PC) {
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@ -260,8 +260,8 @@ DWORD WriteToAccum2(int Location, int PC, Boolean RecursiveCall)
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case RSP_VECTOR_VNOR:
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case RSP_VECTOR_VXOR:
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case RSP_VECTOR_VNXOR:
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/* since these modify the accumulator lower-16 bits we can */
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/* safely assume these 'reset' the accumulator no matter what */
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// Since these modify the accumulator lower-16 bits we can
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// safely assume these 'reset' the accumulator no matter what
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// return FALSE;
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case RSP_VECTOR_VCR:
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case RSP_VECTOR_VCH:
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@ -283,7 +283,7 @@ DWORD WriteToAccum2(int Location, int PC, Boolean RecursiveCall)
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case RSP_VECTOR_VSAW:
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return TRUE;
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default:
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CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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} else {
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@ -294,7 +294,7 @@ DWORD WriteToAccum2(int Location, int PC, Boolean RecursiveCall)
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case RSP_COP2_MF:
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break;
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default:
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CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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}
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@ -322,7 +322,7 @@ DWORD WriteToAccum2(int Location, int PC, Boolean RecursiveCall)
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case RSP_LSC2_HV:
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break;
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default:
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CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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break;
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@ -342,12 +342,12 @@ DWORD WriteToAccum2(int Location, int PC, Boolean RecursiveCall)
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case RSP_LSC2_TV:
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break;
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default:
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CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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break;
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default:
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CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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switch (Instruction_State) {
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@ -362,42 +362,42 @@ DWORD WriteToAccum2(int Location, int PC, Boolean RecursiveCall)
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} while (Instruction_State != FINISH_BLOCK);
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/*
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* This is a tricky situation because most of the
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* microcode does loops, so looping back and checking
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* can prove effective, but it's still a branch..
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*/
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This is a tricky situation because most of the
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microcode does loops, so looping back and checking
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can prove effective, but it's still a branch...
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*/
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if (BranchTarget != 0 && RecursiveCall == FALSE) {
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DWORD BranchTaken, BranchFall;
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/* analysis of branch taken */
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// Analysis of branch taken
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BranchTaken = WriteToAccum2(Location, BranchTarget - 4, TRUE);
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/* analysis of branch as nop */
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// Analysis of branch as NOP
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BranchFall = WriteToAccum2(Location, PC, TRUE);
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if (BranchImmed < 0) {
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if (BranchTaken != FALSE) {
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/*
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* took this back branch and found a place
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* that needs this vector as a source
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*/
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// took this back branch and found a place
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// that needs this vector as a source
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return TRUE;
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} else if (BranchFall == HIT_BRANCH) {
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return TRUE;
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}
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/* otherwise this is completely valid */
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// Otherwise this is completely valid
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return BranchFall;
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} else {
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if (BranchFall != FALSE) {
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/*
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* took this forward branch and found a place
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* that needs this vector as a source
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*/
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// Took this forward branch and found a place
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// that needs this vector as a source
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return TRUE;
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} else if (BranchTaken == HIT_BRANCH) {
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return TRUE;
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}
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/* otherwise this is completely valid */
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// Otherwise this is completely valid
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return BranchTaken;
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}
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}
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@ -420,7 +420,6 @@ Boolean WriteToAccum(int Location, int PC)
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** Output:
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** TRUE: Destination is used as a source later
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** FALSE: Destination is over-written later
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**
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** Input: PC, Register
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*************************************************************/
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@ -454,7 +453,7 @@ Boolean WriteToVectorDest2(DWORD DestReg, int PC, Boolean RecursiveCall)
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Instruction_State = DO_DELAY_SLOT;
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break;
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default:
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CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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break;
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@ -487,20 +486,20 @@ Boolean WriteToVectorDest2(DWORD DestReg, int PC, Boolean RecursiveCall)
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break;
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default:
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CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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break;
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case RSP_J:
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/* there is no way a loopback is going to use accumulator */
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// There is no way a loopback is going to use accumulator
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if (Compiler.bAudioUcode && (int)(RspOp.target << 2) < PC) {
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return FALSE;
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}
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/* rarely occurs let them have their way */
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// Rarely occurs let them have their way
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return TRUE;
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case RSP_JAL:
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/* Assume reg is being passed to function or used after the function call */
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// Assume register is being passed to function or used after the function call
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return TRUE;
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case RSP_BEQ:
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@ -511,11 +510,11 @@ Boolean WriteToVectorDest2(DWORD DestReg, int PC, Boolean RecursiveCall)
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if (Compiler.bAudioUcode) {
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OPCODE NextOp;
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/* ignore backward branches and pretend its a nop */
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// Ignore backward branches and pretend it's a NOP
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if (BranchImmed <= 0) {
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break;
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}
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/* if the opcode 8 bytes before the dest is a J backward than ignore this */
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// If the opcode (which is 8 bytes before the destination and also a J backward) then ignore this
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BranchImmed = (PC + ((short)RspOp.offset << 2) + 4) & 0xFFC;
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RSP_LW_IMEM(BranchImmed - 8, &NextOp.Hex);
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if (RspOp.op == RSP_J && (int)(RspOp.target << 2) < PC) {
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@ -592,7 +591,7 @@ Boolean WriteToVectorDest2(DWORD DestReg, int PC, Boolean RecursiveCall)
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if (DestReg == RspOp.sa) { return FALSE; }
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break;
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default:
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CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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} else {
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@ -607,7 +606,7 @@ Boolean WriteToVectorDest2(DWORD DestReg, int PC, Boolean RecursiveCall)
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if (DestReg == RspOp.rd) { return TRUE; }
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break;
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default:
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CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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}
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@ -641,7 +640,7 @@ Boolean WriteToVectorDest2(DWORD DestReg, int PC, Boolean RecursiveCall)
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break;
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default:
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CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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break;
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@ -678,12 +677,12 @@ Boolean WriteToVectorDest2(DWORD DestReg, int PC, Boolean RecursiveCall)
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break;
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default:
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CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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break;
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default:
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CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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switch (Instruction_State) {
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@ -698,42 +697,42 @@ Boolean WriteToVectorDest2(DWORD DestReg, int PC, Boolean RecursiveCall)
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} while (Instruction_State != FINISH_BLOCK);
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/*
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* This is a tricky situation because most of the
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* microcode does loops, so looping back and checking
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* can prove effective, but it's still a branch..
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*/
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This is a tricky situation because most of the
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microcode does loops, so looping back and checking
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can prove effective, but it's still a branch...
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*/
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if (BranchTarget != 0 && RecursiveCall == FALSE) {
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DWORD BranchTaken, BranchFall;
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/* analysis of branch taken */
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// Analysis of branch taken
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BranchTaken = WriteToVectorDest2(DestReg, BranchTarget - 4, TRUE);
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/* analysis of branch as nop */
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// Analysis of branch as NOP
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BranchFall = WriteToVectorDest2(DestReg, PC, TRUE);
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if (BranchImmed < 0) {
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if (BranchTaken != FALSE) {
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/*
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* took this back branch and found a place
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* Took this back branch and found a place
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* that needs this vector as a source
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*/
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return TRUE;
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} else if (BranchFall == HIT_BRANCH) {
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return TRUE;
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}
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/* otherwise this is completely valid */
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// Otherwise this is completely valid
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return BranchFall;
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} else {
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if (BranchFall != FALSE) {
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/*
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* took this forward branch and found a place
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* Took this forward branch and found a place
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* that needs this vector as a source
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*/
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return TRUE;
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} else if (BranchTaken == HIT_BRANCH) {
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return TRUE;
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}
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/* otherwise this is completely valid */
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// Otherwise this is completely valid
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return BranchTaken;
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}
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}
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@ -747,7 +746,7 @@ Boolean WriteToVectorDest(DWORD DestReg, int PC)
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value = WriteToVectorDest2(DestReg, PC, FALSE);
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if (value == HIT_BRANCH) {
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return TRUE; /* ??? */
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return TRUE; // TODO: ???
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} else
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return value;
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}
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@ -758,11 +757,10 @@ Boolean WriteToVectorDest(DWORD DestReg, int PC)
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** Output:
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** TRUE: Flags are determined not in use
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** FALSE: Either unable to determine or are in use
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**
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** Input: PC
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*************************************************************/
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/* TODO: consider delay slots and such in a branch? */
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// TODO: consider delay slots and such in a branch?
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Boolean UseRspFlags(int PC)
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{
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OPCODE RspOp;
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@ -790,7 +788,7 @@ Boolean UseRspFlags(int PC)
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Instruction_State = DO_DELAY_SLOT;
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break;
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default:
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CompilerWarning("Unkown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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break;
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@ -820,7 +818,7 @@ Boolean UseRspFlags(int PC)
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break;
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default:
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CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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break;
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@ -897,7 +895,7 @@ Boolean UseRspFlags(int PC)
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break;
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default:
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CompilerWarning("Unkown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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} else {
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@ -910,7 +908,7 @@ Boolean UseRspFlags(int PC)
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case RSP_COP2_MF:
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break;
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default:
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CompilerWarning("Unkown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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}
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@ -938,7 +936,7 @@ Boolean UseRspFlags(int PC)
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case RSP_LSC2_HV:
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break;
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default:
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CompilerWarning("Unkown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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break;
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@ -958,12 +956,12 @@ Boolean UseRspFlags(int PC)
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case RSP_LSC2_TV:
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break;
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default:
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CompilerWarning("Unkown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
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CompilerWarning("Unknown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
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return TRUE;
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}
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break;
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default:
|
||||
CompilerWarning("Unkown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
|
||||
CompilerWarning("Unknown opcode in UseRspFlags\n%s",RSPOpcodeName(RspOp.Hex,PC));
|
||||
return TRUE;
|
||||
}
|
||||
switch (Instruction_State) {
|
||||
|
|
@ -985,7 +983,6 @@ Boolean UseRspFlags(int PC)
|
|||
** Output:
|
||||
** TRUE: Register is constant throughout
|
||||
** FALSE: Register is not constant at all
|
||||
**
|
||||
** Input: PC, Pointer to constant to fill
|
||||
*************************************************************/
|
||||
|
||||
|
|
@ -1003,7 +1000,7 @@ Boolean IsRegisterConstant(DWORD Reg, DWORD * Constant)
|
|||
|
||||
RSP_LW_IMEM(PC, &RspOp.Hex);
|
||||
|
||||
/* resample command in microcode likes S7 */
|
||||
// Resample command in microcode likes S7
|
||||
/* if (PC == 0xFBC) {
|
||||
PC += 4;
|
||||
continue;
|
||||
|
|
@ -1041,7 +1038,7 @@ Boolean IsRegisterConstant(DWORD Reg, DWORD * Constant)
|
|||
break;
|
||||
|
||||
default:
|
||||
// CompilerWarning("Unkown opcode in IsRegisterConstant\n%s",RSPOpcodeName(RspOp.Hex,PC));
|
||||
// CompilerWarning("Unknown opcode in IsRegisterConstant\n%s",RSPOpcodeName(RspOp.Hex,PC));
|
||||
// return FALSE;
|
||||
break;
|
||||
}
|
||||
|
|
@ -1117,7 +1114,7 @@ Boolean IsRegisterConstant(DWORD Reg, DWORD * Constant)
|
|||
break;
|
||||
|
||||
default:
|
||||
// CompilerWarning("Unkown opcode in IsRegisterConstant\n%s",RSPOpcodeName(RspOp.Hex,PC));
|
||||
// CompilerWarning("Unknown opcode in IsRegisterConstant\n%s",RSPOpcodeName(RspOp.Hex,PC));
|
||||
// return FALSE;
|
||||
break;
|
||||
}
|
||||
|
|
@ -1141,7 +1138,7 @@ Boolean IsRegisterConstant(DWORD Reg, DWORD * Constant)
|
|||
case RSP_SC2:
|
||||
break;
|
||||
default:
|
||||
// CompilerWarning("Unkown opcode in IsRegisterConstant\n%s",RSPOpcodeName(RspOp.Hex,PC));
|
||||
// CompilerWarning("Unknown opcode in IsRegisterConstant\n%s",RSPOpcodeName(RspOp.Hex,PC));
|
||||
// return FALSE;
|
||||
break;
|
||||
}
|
||||
|
|
@ -1162,13 +1159,12 @@ Boolean IsRegisterConstant(DWORD Reg, DWORD * Constant)
|
|||
** Output:
|
||||
** TRUE: opcode is a branch
|
||||
** FALSE: opcode is not a branch
|
||||
**
|
||||
** Input: PC
|
||||
*************************************************************/
|
||||
|
||||
Boolean IsOpcodeBranch(DWORD PC, OPCODE RspOp)
|
||||
{
|
||||
PC = PC; // unused
|
||||
PC = PC; // Unused
|
||||
|
||||
switch (RspOp.op) {
|
||||
case RSP_REGIMM:
|
||||
|
|
@ -1266,31 +1262,31 @@ Boolean IsOpcodeBranch(DWORD PC, OPCODE RspOp)
|
|||
** with valid opcode data
|
||||
*************************************************************/
|
||||
|
||||
/* 3 possible values, GPR, VEC, VEC & GPR, NOOP is zero */
|
||||
// 3 possible values, GPR, VEC, VEC & GPR, NOOP is zero
|
||||
#define GPR_Instruction 0x0001 /* GPR Instruction flag */
|
||||
#define VEC_Instruction 0x0002 /* Vec Instruction flag */
|
||||
#define COPO_MF_Instruction 0x0080 /* MF Cop 0 Instruction */
|
||||
#define Flag_Instruction 0x0100 /* Access Flags */
|
||||
#define Instruction_Mask (GPR_Instruction | VEC_Instruction)
|
||||
|
||||
/* 3 possible values, one flag must be set only */
|
||||
// 3 possible values, one flag must be set only
|
||||
#define Load_Operation 0x0004 /* Load Instruction flag */
|
||||
#define Store_Operation 0x0008 /* Store Instruction flag */
|
||||
#define Accum_Operation 0x0010 /* Vector op uses accum - loads & stores dont */
|
||||
#define MemOperation_Mask (Load_Operation | Store_Operation)
|
||||
#define Operation_Mask (MemOperation_Mask | Accum_Operation)
|
||||
|
||||
/* Per situation basis flags */
|
||||
// Per situation basis flags
|
||||
#define VEC_ResetAccum 0x0000 /* Vector op resets acc */
|
||||
#define VEC_Accumulate 0x0020 /* Vector op accumulates */
|
||||
|
||||
/* N/A in instruction assembler syntax, possibly an unused register specifier */
|
||||
// N/A in instruction assembler syntax, possibly an unused register specifier
|
||||
#define UNUSED_OPERAND ~0u
|
||||
|
||||
#define InvalidOpcode 0x0040
|
||||
|
||||
#pragma warning(push)
|
||||
#pragma warning(disable : 4201) // nonstandard extension used : nameless struct/union
|
||||
#pragma warning(disable : 4201) // Non-standard extension used: nameless struct/union
|
||||
|
||||
typedef struct {
|
||||
union {
|
||||
|
|
@ -1321,7 +1317,7 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
|
|||
break;
|
||||
|
||||
default:
|
||||
CompilerWarning("Unkown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
|
||||
CompilerWarning("Unknown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
|
||||
info->flags = InvalidOpcode;
|
||||
break;
|
||||
}
|
||||
|
|
@ -1369,7 +1365,7 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
|
|||
break;
|
||||
|
||||
default:
|
||||
CompilerWarning("Unkown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
|
||||
CompilerWarning("Unknown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
|
||||
info->flags = InvalidOpcode;
|
||||
break;
|
||||
}
|
||||
|
|
@ -1500,14 +1496,14 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
|
|||
info->DestReg = RspOp->sa;
|
||||
info->SourceReg0 = RspOp->rt;
|
||||
info->SourceReg1 = UNUSED_OPERAND;
|
||||
info->flags = VEC_Instruction | VEC_ResetAccum | Accum_Operation; /* Assume reset? */
|
||||
info->flags = VEC_Instruction | VEC_ResetAccum | Accum_Operation; // Assume reset?
|
||||
break;
|
||||
|
||||
case RSP_VECTOR_VMRG:
|
||||
info->DestReg = RspOp->sa;
|
||||
info->SourceReg0 = RspOp->rt;
|
||||
info->SourceReg1 = RspOp->rd;
|
||||
info->flags = VEC_Instruction | VEC_ResetAccum | Accum_Operation | Flag_Instruction; /* Assum reset? */
|
||||
info->flags = VEC_Instruction | VEC_ResetAccum | Accum_Operation | Flag_Instruction; // Assume reset?
|
||||
break;
|
||||
|
||||
case RSP_VECTOR_VSAW:
|
||||
|
|
@ -1519,7 +1515,7 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
|
|||
break;
|
||||
|
||||
default:
|
||||
CompilerWarning("Unkown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
|
||||
CompilerWarning("Unknown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
|
||||
info->flags = InvalidOpcode;
|
||||
break;
|
||||
}
|
||||
|
|
@ -1538,7 +1534,7 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
|
|||
info->flags = GPR_Instruction | Load_Operation | Flag_Instruction;
|
||||
break;
|
||||
|
||||
/* RD is always the vector register, RT is always GPR */
|
||||
// RD is always the vector register, RT is always GPR
|
||||
case RSP_COP2_MT:
|
||||
info->DestReg = RspOp->rd;
|
||||
info->SourceReg0 = RspOp->rt;
|
||||
|
|
@ -1552,7 +1548,7 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
|
|||
info->flags = VEC_Instruction | GPR_Instruction | Store_Operation;
|
||||
break;
|
||||
default:
|
||||
CompilerWarning("Unkown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
|
||||
CompilerWarning("Unknown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
|
||||
info->flags = InvalidOpcode;
|
||||
break;
|
||||
}
|
||||
|
|
@ -1596,7 +1592,7 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
|
|||
info->flags = InvalidOpcode;
|
||||
break;
|
||||
default:
|
||||
CompilerWarning("Unkown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
|
||||
CompilerWarning("Unknown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
|
||||
info->flags = InvalidOpcode;
|
||||
break;
|
||||
}
|
||||
|
|
@ -1623,13 +1619,13 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
|
|||
info->flags = InvalidOpcode;
|
||||
break;
|
||||
default:
|
||||
CompilerWarning("Unkown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
|
||||
CompilerWarning("Unknown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
|
||||
info->flags = InvalidOpcode;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
/* CompilerWarning("Unkown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
|
||||
/* CompilerWarning("Unknown opcode in GetInstructionInfo\n%s",RSPOpcodeName(RspOp->Hex,PC));
|
||||
*/ info->flags = InvalidOpcode;
|
||||
break;
|
||||
}
|
||||
|
|
@ -1702,7 +1698,7 @@ Boolean CompareInstructions(DWORD PC, OPCODE * Top, OPCODE * Bottom)
|
|||
CPU_Message("to %s (%X)", RSPOpcodeName ( Bottom->Hex, PC), PC);
|
||||
#endif
|
||||
|
||||
/* usually branches and such */
|
||||
// Usually branches and such
|
||||
if ((info0.flags & InvalidOpcode) != 0) return FALSE;
|
||||
if ((info1.flags & InvalidOpcode) != 0) return FALSE;
|
||||
|
||||
|
|
@ -1710,156 +1706,162 @@ Boolean CompareInstructions(DWORD PC, OPCODE * Top, OPCODE * Bottom)
|
|||
|
||||
InstructionType = (info0.flags & Instruction_Mask) << 2;
|
||||
InstructionType |= info1.flags & Instruction_Mask;
|
||||
InstructionType &= 0x0F; /* Paranoia */
|
||||
InstructionType &= 0x0F; // Paranoia
|
||||
|
||||
/* 4 bit range, 16 possible combinations */
|
||||
// 4-bit range, 16 possible combinations
|
||||
switch (InstructionType) {
|
||||
/*
|
||||
** Detect noop instruction, 7 cases, (see flags) */
|
||||
case 0x01: case 0x02: case 0x03: /* First is a noop */
|
||||
|
||||
// Detect NOOP instruction, 7 cases, (see flags)
|
||||
case 0x01: case 0x02: case 0x03: // First is a NOOP
|
||||
return TRUE;
|
||||
case 0x00: /* Both ??? */
|
||||
case 0x10: case 0x20: case 0x30: /* Second is a noop */
|
||||
case 0x00: // Both?
|
||||
case 0x10: case 0x20: case 0x30: // Second is a NOOP
|
||||
return FALSE;
|
||||
|
||||
case 0x06: /* GPR than Vector - 01,10 */
|
||||
case 0x06: // GPR then Vector - 01,10
|
||||
if ((info0.flags & MemOperation_Mask) != 0 && (info1.flags & MemOperation_Mask) != 0) {
|
||||
/* TODO: We have a vector & GPR memory operation */
|
||||
// TODO: We have a vector and GPR memory operation
|
||||
return FALSE;
|
||||
} else if ((info1.flags & MemOperation_Mask) != 0) {
|
||||
/* We have a vector memory operation */
|
||||
// We have a vector memory operation
|
||||
return (info1.IndexReg == info0.DestReg) ? FALSE : TRUE;
|
||||
}
|
||||
/* We could have memory or normal gpr instruction here
|
||||
** paired with some kind of vector operation
|
||||
*/
|
||||
|
||||
// We could have memory or normal GPR instruction here
|
||||
// paired with some kind of vector operation
|
||||
|
||||
return TRUE;
|
||||
case 0x0A: /* Vector than Vector - 10,10 */
|
||||
case 0x0A: // Vector then Vector - 10,10
|
||||
|
||||
/*
|
||||
** Check for Vector Store than Vector multiply (VMULF)
|
||||
** Check for vector store then vector multiply (VMULF)
|
||||
**
|
||||
** This basically gives preferences to putting stores
|
||||
** as close to the finish of an operation as possible
|
||||
*/
|
||||
|
||||
if ((info0.flags & Store_Operation) != 0 && (info1.flags & Accum_Operation) != 0
|
||||
&& !(info1.flags & VEC_Accumulate)) { return FALSE; }
|
||||
|
||||
/*
|
||||
** Look for loads and than some kind of vector operation
|
||||
** that does no accumulating, there is no reason to reorder
|
||||
*/
|
||||
|
||||
// Look for loads and than some kind of vector operation
|
||||
// that does no accumulating, there is no reason to reorder
|
||||
|
||||
if ((info0.flags & Load_Operation) != 0 && (info1.flags & Accum_Operation) != 0
|
||||
&& !(info1.flags & VEC_Accumulate)) { return FALSE; }
|
||||
|
||||
if ((info0.flags & MemOperation_Mask) != 0 && (info1.flags & MemOperation_Mask) != 0) {
|
||||
/*
|
||||
** TODO: This is a bitch, its best to leave it alone
|
||||
**/
|
||||
|
||||
// TODO: This is a pain, it's best to leave it alone
|
||||
|
||||
return FALSE;
|
||||
} else if ((info1.flags & MemOperation_Mask) != 0) {
|
||||
/* Remember stored reg & loaded reg are the same */
|
||||
// Remember stored REG & loaded REG are the same
|
||||
if (info0.DestReg == info1.DestReg) { return FALSE; }
|
||||
|
||||
if (info1.flags & Load_Operation) {
|
||||
if (info0.SourceReg0 == info1.DestReg) { return FALSE; }
|
||||
if (info0.SourceReg1 == info1.DestReg) { return FALSE; }
|
||||
} else if (info1.flags & Store_Operation) {
|
||||
/* It can store source regs */
|
||||
// It can store source REGS
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
} else if ((info0.flags & MemOperation_Mask) != 0) {
|
||||
/* Remember stored reg & loaded reg are the same */
|
||||
// Remember stored REG & loaded REG are the same
|
||||
if (info0.DestReg == info1.DestReg) { return FALSE; }
|
||||
|
||||
if (info0.flags & Load_Operation) {
|
||||
if (info1.SourceReg0 == info0.DestReg) { return FALSE; }
|
||||
if (info1.SourceReg1 == info0.DestReg) { return FALSE; }
|
||||
} else if (info0.flags & Store_Operation) {
|
||||
/* It can store source regs */
|
||||
// It can store source REGS
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
} else if ((info0.flags & VEC_Accumulate) != 0) {
|
||||
|
||||
/*
|
||||
** Example:
|
||||
** VMACF
|
||||
** VMUDH or VMADH or VADD
|
||||
** VMACF
|
||||
** VMUDH or VMADH or VADD
|
||||
*/
|
||||
|
||||
return FALSE;
|
||||
} else if ((info1.flags & VEC_Accumulate) != 0) {
|
||||
|
||||
/*
|
||||
** Example:
|
||||
** VMULF
|
||||
** VMADH
|
||||
** VMULF
|
||||
** VMADH
|
||||
*/
|
||||
|
||||
return FALSE;
|
||||
} else {
|
||||
|
||||
/*
|
||||
** Example:
|
||||
** VMULF or VADDC
|
||||
** VADD or VMUDH
|
||||
** VMULF or VADDC
|
||||
** VADD or VMUDH
|
||||
*/
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x09: /* Vector than GPR - 10,01 */
|
||||
/**********
|
||||
** this is where the bias comes into play, otherwise
|
||||
** we can sit here all day swapping these 2 types
|
||||
***********/
|
||||
case 0x09: // Vector then GPR - 10,01
|
||||
|
||||
/*
|
||||
This is where the bias comes into play, otherwise
|
||||
we can sit here all day swapping these 2 types
|
||||
*/
|
||||
|
||||
return FALSE;
|
||||
|
||||
case 0x05: /* GPR than GPR - 01,01 */
|
||||
case 0x07: /* GPR than Cop2 - 01, 11 */
|
||||
case 0x0D: /* Cop2 than GPR - 11, 01 */
|
||||
case 0x0F: /* Cop2 than Cop2 - 11, 11 */
|
||||
case 0x05: // GPR then GPR - 01,01
|
||||
case 0x07: // GPR then COP2 - 01, 11
|
||||
case 0x0D: // COP2 then GPR - 11, 01
|
||||
case 0x0F: // COP2 then COP2 - 11, 11
|
||||
return FALSE;
|
||||
|
||||
case 0x0B: /* Vector than Cop2 - 10, 11 */
|
||||
case 0x0B: // Vector then COP2 - 10, 11
|
||||
if (info1.flags & Load_Operation) {
|
||||
/* Move To Cop2 (dest) from GPR (source) */
|
||||
// Move To COP2 (destination) from GPR (source)
|
||||
if (info1.DestReg == info0.DestReg) { return FALSE; }
|
||||
if (info1.DestReg == info0.SourceReg0) { return FALSE; }
|
||||
if (info1.DestReg == info0.SourceReg1) { return FALSE; }
|
||||
} else if (info1.flags & Store_Operation) {
|
||||
/* Move From Cop2 (source) to GPR (dest) */
|
||||
// Move From COP2 (source) to GPR (destination)
|
||||
if (info1.SourceReg0 == info0.DestReg) { return FALSE; }
|
||||
if (info1.SourceReg0 == info0.SourceReg0) { return FALSE; }
|
||||
if (info1.SourceReg0 == info0.SourceReg1) { return FALSE; }
|
||||
} else {
|
||||
CompilerWarning("ReOrder: Unhandled Vector than Cop2");
|
||||
CompilerWarning("Reorder: Unhandled Vector than COP2");
|
||||
}
|
||||
// we want vectors on top
|
||||
// We want vectors on top
|
||||
return FALSE;
|
||||
|
||||
case 0x0E: /* Cop2 than Vector - 11, 10 */
|
||||
case 0x0E: // COP2 then Vector - 11, 10
|
||||
if (info0.flags & Load_Operation) {
|
||||
/* Move To Cop2 (dest) from GPR (source) */
|
||||
// Move To COP2 (destination) from GPR (source)
|
||||
if (info0.DestReg == info1.DestReg) { return FALSE; }
|
||||
if (info0.DestReg == info1.SourceReg0) { return FALSE; }
|
||||
if (info0.DestReg == info1.SourceReg1) { return FALSE; }
|
||||
} else if (info0.flags & Store_Operation) {
|
||||
/* Move From Cop2 (source) to GPR (dest) */
|
||||
// Move From COP2 (source) to GPR (destination)
|
||||
if (info0.SourceReg0 == info1.DestReg) { return FALSE; }
|
||||
if (info0.SourceReg0 == info1.SourceReg0) { return FALSE; }
|
||||
if (info0.SourceReg0 == info1.SourceReg1) { return FALSE; }
|
||||
if (info0.DestReg == info1.SourceReg0) { return FALSE; }
|
||||
} else {
|
||||
CompilerWarning("ReOrder: Unhandled Cop2 than Vector");
|
||||
CompilerWarning("Reorder: Unhandled COP2 than Vector");
|
||||
}
|
||||
// we want this at the top
|
||||
// We want this at the top
|
||||
return TRUE;
|
||||
|
||||
default:
|
||||
CompilerWarning("ReOrder: Unhandled instruction type: %i", InstructionType);
|
||||
CompilerWarning("Reorder: Unhandled instruction type: %i", InstructionType);
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
|
|
|
|||
Loading…
Reference in New Issue