From 4174ec153bcf7845d48c85db4eba80ed18df2a3e Mon Sep 17 00:00:00 2001 From: zilmar Date: Sat, 1 Oct 2016 09:32:32 +1000 Subject: [PATCH] [Android] Add MulF32 --- .../N64System/Recompiler/Arm/ArmOps.cpp | 21 +++++++++++++++++++ .../N64System/Recompiler/Arm/ArmOps.h | 1 + 2 files changed, 22 insertions(+) diff --git a/Source/Project64-core/N64System/Recompiler/Arm/ArmOps.cpp b/Source/Project64-core/N64System/Recompiler/Arm/ArmOps.cpp index 6b4daf916..aeabcac2b 100644 --- a/Source/Project64-core/N64System/Recompiler/Arm/ArmOps.cpp +++ b/Source/Project64-core/N64System/Recompiler/Arm/ArmOps.cpp @@ -497,6 +497,27 @@ void CArmOps::OrArmRegToArmReg(ArmReg DestReg, ArmReg SourceReg1, ArmReg SourceR AddCode32(op.Hex); } +void CArmOps::MulF32(ArmFpuSingle DestReg, ArmFpuSingle SourceReg1, ArmFpuSingle SourceReg2) +{ + CPU_Message(" vmul.f32\t%s, %s, %s", ArmFpuSingleName(DestReg), ArmFpuSingleName(SourceReg1), ArmFpuSingleName(SourceReg2)); + Arm32Opcode op = {0}; + op.VnVmVd.vn = SourceReg1 >> 1; + op.VnVmVd.op1 = 0x2; + op.VnVmVd.d = DestReg & 1; + op.VnVmVd.op2 = 0x1DC; + + op.VnVmVd.vm = SourceReg2 >> 1; + op.VnVmVd.op3 = 0; + op.VnVmVd.m = SourceReg2 & 1; + op.VnVmVd.op4 = 0; + op.VnVmVd.n = SourceReg1 & 1; + op.VnVmVd.sz = 0; + op.VnVmVd.op5 = 0x5; + op.VnVmVd.vd = DestReg >> 1; + + AddCode32(op.Hex); +} + void CArmOps::PushArmReg(uint16_t Registers) { if (Registers == 0) diff --git a/Source/Project64-core/N64System/Recompiler/Arm/ArmOps.h b/Source/Project64-core/N64System/Recompiler/Arm/ArmOps.h index 106f535df..a3af7e09e 100644 --- a/Source/Project64-core/N64System/Recompiler/Arm/ArmOps.h +++ b/Source/Project64-core/N64System/Recompiler/Arm/ArmOps.h @@ -160,6 +160,7 @@ protected: static void MoveVariableToArmReg(void * Variable, const char * VariableName, ArmReg reg); static void MoveVariableToFloatReg(void * Variable, const char * VariableName, ArmFpuSingle reg); static void OrArmRegToArmReg(ArmReg DestReg, ArmReg SourceReg1, ArmReg SourceReg2, uint32_t shift); + static void MulF32(ArmFpuSingle DestReg, ArmFpuSingle SourceReg1, ArmFpuSingle SourceReg2); static void PushArmReg(uint16_t Registers); static void PopArmReg(uint16_t Registers); static void ShiftRightSignImmed(ArmReg DestReg, ArmReg SourceReg, uint32_t shift);