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Merge pull request #250 from cxd4/i_dont_always_zero_but_when_i_do_i_dont 

minor clean-ups to how MIPS GPR $zero is handled in VR4300 and RSP CPUs
This commit is contained in:
zilmar 2015-03-09 12:03:04 +11:00
parent b6341d0b92 cb9f9e2b56
commit 3eb5f57c11
5 changed files with 22 additions and 83 deletions
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2
Source/Project64/N64 System/Interpreter/Interpreter CPU.cpp
View File

@ -337,7 +337,7 @@ void CInterpreterCPU::ExecuteOps ( int Cycles )
//WriteTraceF((TraceType)(TraceError | TraceNoHeader),"%X: %d %d",*_PROGRAM_COUNTER,*g_NextTimer,g_SystemTimer->CurrentType());
}*/
m_R4300i_Opcode[ Opcode.op ]();
_GPR[0].DW = 0;
_GPR[0].DW = 0; /* MIPS $zero hard-wired to 0 */
Cycles -= CountPerOp;
*g_NextTimer -= CountPerOp;

9
Source/Project64/N64 System/Interpreter/Interpreter Ops 32.cpp
View File

@ -709,7 +709,6 @@ void R4300iOp32::ADDI (void) {
StackValue += (short)m_Opcode.immediate;
}
#endif
if (m_Opcode.rt == 0) { return; }
_GPR[m_Opcode.rt].W[0] = (_GPR[m_Opcode.rs].W[0] + ((short)m_Opcode.immediate));
#ifdef Interpreter_StackTest
if (m_Opcode.rt == 29 && m_Opcode.rs != 29) {
@ -761,7 +760,6 @@ void R4300iOp32::XORI (void) {
}
void R4300iOp32::LUI (void) {
if (m_Opcode.rt == 0) { return; }
_GPR[m_Opcode.rt].W[0] = (long)((short)m_Opcode.offset << 16);
#ifdef Interpreter_StackTest
if (m_Opcode.rt == 29) {
@ -840,7 +838,6 @@ void R4300iOp32::BGTZL (void) {
void R4300iOp32::LB (void) {
DWORD Address = _GPR[m_Opcode.base].UW[0] + (short)m_Opcode.offset;
if (m_Opcode.rt == 0) { return; }
if (!g_MMU->LB_VAddr(Address,_GPR[m_Opcode.rt].UB[0])) {
if (bShowTLBMisses()) {
g_Notify->DisplayError(L"LB TLB: %X",Address);
@ -892,8 +889,6 @@ void R4300iOp32::LW (void) {
Log_LW((*_PROGRAM_COUNTER),Address);
}
if (m_Opcode.rt == 0) { return; }
if (!g_MMU->LW_VAddr(Address,_GPR[m_Opcode.rt].UW[0])) {
if (bShowTLBMisses()) {
g_Notify->DisplayError(L"LW TLB: %X",Address);
@ -952,7 +947,6 @@ void R4300iOp32::LWR (void) {
void R4300iOp32::LWU (void) {
DWORD Address = _GPR[m_Opcode.base].UW[0] + (short)m_Opcode.offset;
if ((Address & 3) != 0) { ADDRESS_ERROR_EXCEPTION(Address,TRUE); }
if (m_Opcode.rt == 0) { return; }
if (!g_MMU->LW_VAddr(Address,_GPR[m_Opcode.rt].UW[0])) {
if (bShowTLBMisses()) {
@ -969,8 +963,6 @@ void R4300iOp32::LL (void) {
DWORD Address = _GPR[m_Opcode.base].UW[0] + (short)m_Opcode.offset;
if ((Address & 3) != 0) { ADDRESS_ERROR_EXCEPTION(Address,TRUE); }
if (m_Opcode.rt == 0) { return; }
if (!g_MMU->LW_VAddr(Address,_GPR[m_Opcode.rt].UW[0])) {
if (bShowTLBMisses()) {
g_Notify->DisplayError(L"LL TLB: %X",Address);
@ -996,7 +988,6 @@ void R4300iOp32::SPECIAL_SRA (void) {
}
void R4300iOp32::SPECIAL_SLLV (void) {
if (m_Opcode.rd == 0) { return; }
_GPR[m_Opcode.rd].W[0] = (_GPR[m_Opcode.rt].W[0] << (_GPR[m_Opcode.rs].UW[0] & 0x1F));
}

9
Source/Project64/N64 System/Interpreter/Interpreter Ops.cpp
View File

@ -814,7 +814,6 @@ void R4300iOp::ADDI (void)
StackValue += (short)m_Opcode.immediate;
}
#endif
if (m_Opcode.rt == 0) { return; }
_GPR[m_Opcode.rt].DW = (_GPR[m_Opcode.rs].W[0] + ((short)m_Opcode.immediate));
#ifdef Interpreter_StackTest
if (m_Opcode.rt == 29 && m_Opcode.rs != 29) {
@ -873,7 +872,6 @@ void R4300iOp::XORI (void)
void R4300iOp::LUI (void)
{
if (m_Opcode.rt == 0) { return; }
_GPR[m_Opcode.rt].DW = (long)((short)m_Opcode.offset << 16);
#ifdef Interpreter_StackTest
if (m_Opcode.rt == 29) {
@ -1016,7 +1014,6 @@ void R4300iOp::LDR (void)
void R4300iOp::LB (void)
{
DWORD Address = _GPR[m_Opcode.base].UW[0] + (short)m_Opcode.offset;
if (m_Opcode.rt == 0) { return; }
if (!g_MMU->LB_VAddr(Address,_GPR[m_Opcode.rt].UB[0])) {
if (bShowTLBMisses()) {
g_Notify->DisplayError(L"LB TLB: %X",Address);
@ -1072,8 +1069,6 @@ void R4300iOp::LW (void)
Log_LW((*_PROGRAM_COUNTER),Address);
}
if (m_Opcode.rt == 0) { return; }
if (!g_MMU->LW_VAddr(Address,_GPR[m_Opcode.rt].UW[0])) {
if (bShowTLBMisses()) {
g_Notify->DisplayError(L"LW TLB: %X",Address);
@ -1136,7 +1131,6 @@ void R4300iOp::LWU (void)
{
DWORD Address = _GPR[m_Opcode.base].UW[0] + (short)m_Opcode.offset;
if ((Address & 3) != 0) { ADDRESS_ERROR_EXCEPTION(Address,TRUE); }
if (m_Opcode.rt == 0) { return; }
if (!g_MMU->LW_VAddr(Address,_GPR[m_Opcode.rt].UW[0])) {
if (bShowTLBMisses()) {
@ -1381,8 +1375,6 @@ void R4300iOp::LL (void)
DWORD Address = _GPR[m_Opcode.base].UW[0] + (short)m_Opcode.offset;
if ((Address & 3) != 0) { ADDRESS_ERROR_EXCEPTION(Address,TRUE); }
if (m_Opcode.rt == 0) { return; }
if (!g_MMU->LW_VAddr(Address,_GPR[m_Opcode.rt].UW[0]))
{
if (bShowTLBMisses())
@ -1543,7 +1535,6 @@ void R4300iOp::SPECIAL_SRA (void)
void R4300iOp::SPECIAL_SLLV (void)
{
if (m_Opcode.rd == 0) { return; }
_GPR[m_Opcode.rd].DW = (_GPR[m_Opcode.rt].W[0] << (_GPR[m_Opcode.rs].UW[0] & 0x1F));
}

1
Source/RSP/Interpreter CPU.c
View File

@ -444,6 +444,7 @@ DWORD RunInterpreterCPU(DWORD Cycles) {
RSP_LW_IMEM(*PrgCount, &RSPOpC.Hex);
RSP_Opcode[ RSPOpC.op ]();
RSP_GPR[0].W = 0x00000000; /* MIPS $zero hard-wired to 0 */
switch (RSP_NextInstruction) {
case NORMAL:

84
Source/RSP/Interpreter Ops.c
View File

@ -98,19 +98,14 @@ void RSP_Opcode_BGTZ ( void ) {
}
void RSP_Opcode_ADDI ( void ) {
if (RSPOpC.rt != 0) {
RSP_GPR[RSPOpC.rt].W = RSP_GPR[RSPOpC.rs].W + (int16_t)RSPOpC.immediate;
}
RSP_GPR[RSPOpC.rt].W = RSP_GPR[RSPOpC.rs].W + (int16_t)RSPOpC.immediate;
}
void RSP_Opcode_ADDIU ( void ) {
if (RSPOpC.rt != 0) {
RSP_GPR[RSPOpC.rt].UW = RSP_GPR[RSPOpC.rs].UW + (uint32_t)((int16_t)RSPOpC.immediate);
}
RSP_GPR[RSPOpC.rt].UW = RSP_GPR[RSPOpC.rs].UW + (uint32_t)((int16_t)RSPOpC.immediate);
}
void RSP_Opcode_SLTI (void) {
if (RSPOpC.rt == 0) { return; }
if (RSP_GPR[RSPOpC.rs].W < (int16_t)RSPOpC.immediate) {
RSP_GPR[RSPOpC.rt].W = 1;
} else {
@ -119,7 +114,6 @@ void RSP_Opcode_SLTI (void) {
}
void RSP_Opcode_SLTIU (void) {
if (RSPOpC.rt == 0) { return; }
if (RSP_GPR[RSPOpC.rs].UW < (uint32_t)(int16_t)RSPOpC.immediate) {
RSP_GPR[RSPOpC.rt].W = 1;
} else {
@ -128,27 +122,19 @@ void RSP_Opcode_SLTIU (void) {
}
void RSP_Opcode_ANDI ( void ) {
if (RSPOpC.rt != 0) {
RSP_GPR[RSPOpC.rt].W = RSP_GPR[RSPOpC.rs].W & RSPOpC.immediate;
}
RSP_GPR[RSPOpC.rt].W = RSP_GPR[RSPOpC.rs].W & RSPOpC.immediate;
}
void RSP_Opcode_ORI ( void ) {
if (RSPOpC.rt != 0) {
RSP_GPR[RSPOpC.rt].W = RSP_GPR[RSPOpC.rs].W | RSPOpC.immediate;
}
RSP_GPR[RSPOpC.rt].W = RSP_GPR[RSPOpC.rs].W | RSPOpC.immediate;
}
void RSP_Opcode_XORI ( void ) {
if (RSPOpC.rt != 0) {
RSP_GPR[RSPOpC.rt].W = RSP_GPR[RSPOpC.rs].W ^ RSPOpC.immediate;
}
RSP_GPR[RSPOpC.rt].W = RSP_GPR[RSPOpC.rs].W ^ RSPOpC.immediate;
}
void RSP_Opcode_LUI (void) {
if (RSPOpC.rt != 0) {
RSP_GPR[RSPOpC.rt].W = RSPOpC.immediate << 16;
}
RSP_GPR[RSPOpC.rt].W = RSPOpC.immediate << 16;
}
void RSP_Opcode_COP0 (void) {
@ -213,39 +199,27 @@ void RSP_Opcode_SC2 (void) {
/********************** R4300i OpCodes: Special **********************/
void RSP_Special_SLL ( void ) {
if (RSPOpC.rd != 0) {
RSP_GPR[RSPOpC.rd].W = RSP_GPR[RSPOpC.rt].W << RSPOpC.sa;
}
RSP_GPR[RSPOpC.rd].W = RSP_GPR[RSPOpC.rt].W << RSPOpC.sa;
}
void RSP_Special_SRL ( void ) {
if (RSPOpC.rd != 0) {
RSP_GPR[RSPOpC.rd].UW = RSP_GPR[RSPOpC.rt].UW >> RSPOpC.sa;
}
RSP_GPR[RSPOpC.rd].UW = RSP_GPR[RSPOpC.rt].UW >> RSPOpC.sa;
}
void RSP_Special_SRA ( void ) {
if (RSPOpC.rd != 0) {
RSP_GPR[RSPOpC.rd].W = RSP_GPR[RSPOpC.rt].W >> RSPOpC.sa;
}
RSP_GPR[RSPOpC.rd].W = RSP_GPR[RSPOpC.rt].W >> RSPOpC.sa;
}
void RSP_Special_SLLV (void) {
if (RSPOpC.rd != 0) {
RSP_GPR[RSPOpC.rd].W = RSP_GPR[RSPOpC.rt].W << (RSP_GPR[RSPOpC.rs].W & 0x1F);
}
RSP_GPR[RSPOpC.rd].W = RSP_GPR[RSPOpC.rt].W << (RSP_GPR[RSPOpC.rs].W & 0x1F);
}
void RSP_Special_SRLV (void) {
if (RSPOpC.rd != 0) {
RSP_GPR[RSPOpC.rd].UW = RSP_GPR[RSPOpC.rt].UW >> (RSP_GPR[RSPOpC.rs].W & 0x1F);
}
RSP_GPR[RSPOpC.rd].UW = RSP_GPR[RSPOpC.rt].UW >> (RSP_GPR[RSPOpC.rs].W & 0x1F);
}
void RSP_Special_SRAV (void) {
if (RSPOpC.rd != 0) {
RSP_GPR[RSPOpC.rd].W = RSP_GPR[RSPOpC.rt].W >> (RSP_GPR[RSPOpC.rs].W & 0x1F);
}
RSP_GPR[RSPOpC.rd].W = RSP_GPR[RSPOpC.rt].W >> (RSP_GPR[RSPOpC.rs].W & 0x1F);
}
void RSP_Special_JR (void) {
@ -269,55 +243,38 @@ void RSP_Special_BREAK ( void ) {
}
void RSP_Special_ADD (void) {
if (RSPOpC.rd != 0) {
RSP_GPR[RSPOpC.rd].W = RSP_GPR[RSPOpC.rs].W + RSP_GPR[RSPOpC.rt].W;
}
RSP_GPR[RSPOpC.rd].W = RSP_GPR[RSPOpC.rs].W + RSP_GPR[RSPOpC.rt].W;
}
void RSP_Special_ADDU (void) {
if (RSPOpC.rd != 0) {
RSP_GPR[RSPOpC.rd].UW = RSP_GPR[RSPOpC.rs].UW + RSP_GPR[RSPOpC.rt].UW;
}
RSP_GPR[RSPOpC.rd].UW = RSP_GPR[RSPOpC.rs].UW + RSP_GPR[RSPOpC.rt].UW;
}
void RSP_Special_SUB (void) {
if (RSPOpC.rd != 0) {
RSP_GPR[RSPOpC.rd].W = RSP_GPR[RSPOpC.rs].W - RSP_GPR[RSPOpC.rt].W;
}
RSP_GPR[RSPOpC.rd].W = RSP_GPR[RSPOpC.rs].W - RSP_GPR[RSPOpC.rt].W;
}
void RSP_Special_SUBU (void) {
if (RSPOpC.rd != 0) {
RSP_GPR[RSPOpC.rd].UW = RSP_GPR[RSPOpC.rs].UW - RSP_GPR[RSPOpC.rt].UW;
}
RSP_GPR[RSPOpC.rd].UW = RSP_GPR[RSPOpC.rs].UW - RSP_GPR[RSPOpC.rt].UW;
}
void RSP_Special_AND (void) {
if (RSPOpC.rd != 0) {
RSP_GPR[RSPOpC.rd].UW = RSP_GPR[RSPOpC.rs].UW & RSP_GPR[RSPOpC.rt].UW;
}
RSP_GPR[RSPOpC.rd].UW = RSP_GPR[RSPOpC.rs].UW & RSP_GPR[RSPOpC.rt].UW;
}
void RSP_Special_OR (void) {
if (RSPOpC.rd != 0) {
RSP_GPR[RSPOpC.rd].UW = RSP_GPR[RSPOpC.rs].UW | RSP_GPR[RSPOpC.rt].UW;
}
RSP_GPR[RSPOpC.rd].UW = RSP_GPR[RSPOpC.rs].UW | RSP_GPR[RSPOpC.rt].UW;
}
void RSP_Special_XOR (void) {
if (RSPOpC.rd != 0) {
RSP_GPR[RSPOpC.rd].UW = RSP_GPR[RSPOpC.rs].UW ^ RSP_GPR[RSPOpC.rt].UW;
}
RSP_GPR[RSPOpC.rd].UW = RSP_GPR[RSPOpC.rs].UW ^ RSP_GPR[RSPOpC.rt].UW;
}
void RSP_Special_NOR (void) {
if (RSPOpC.rd != 0) {
RSP_GPR[RSPOpC.rd].UW = ~(RSP_GPR[RSPOpC.rs].UW | RSP_GPR[RSPOpC.rt].UW);
}
RSP_GPR[RSPOpC.rd].UW = ~(RSP_GPR[RSPOpC.rs].UW | RSP_GPR[RSPOpC.rt].UW);
}
void RSP_Special_SLT (void) {
if (RSPOpC.rd == 0) { return; }
if (RSP_GPR[RSPOpC.rs].W < RSP_GPR[RSPOpC.rt].W) {
RSP_GPR[RSPOpC.rd].UW = 1;
} else {
@ -326,7 +283,6 @@ void RSP_Special_SLT (void) {
}
void RSP_Special_SLTU (void) {
if (RSPOpC.rd == 0) { return; }
if (RSP_GPR[RSPOpC.rs].UW < RSP_GPR[RSPOpC.rt].UW) {
RSP_GPR[RSPOpC.rd].UW = 1;
} else {