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Core: Convert DoBreakException to TriggerException

This commit is contained in:
zilmar 2023-05-18 11:47:00 +09:30
parent b2c2a03a2e
commit 3b8dfce64a
4 changed files with 5 additions and 36 deletions
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4
Source/Project64-core/N64System/Interpreter/InterpreterOps.cpp
View File

@ -1310,9 +1310,7 @@ void R4300iOp::SPECIAL_BREAK()
} }
else else
{ {
g_Reg->DoBreakException(g_System->m_PipelineStage == PIPELINE_STAGE_JUMP); g_Reg->TriggerException(EXC_BREAK);
g_System->m_PipelineStage = PIPELINE_STAGE_JUMP;
g_System->m_JumpToLocation = (*_PROGRAM_COUNTER);
} }
} }

30
Source/Project64-core/N64System/Mips/Register.cpp
View File

@ -591,36 +591,6 @@ void CRegisters::FixFpuLocations()
} }
} }
void CRegisters::DoBreakException(bool DelaySlot)
{
if (HaveDebugger())
{
if ((STATUS_REGISTER & STATUS_EXL) != 0)
{
g_Notify->DisplayError("EXL set in break exception");
}
if ((STATUS_REGISTER & STATUS_ERL) != 0)
{
g_Notify->DisplayError("ERL set in break exception");
}
}
CAUSE_REGISTER.ExceptionCode = EXC_BREAK;
CAUSE_REGISTER.CoprocessorUnitNumber = 0;
if (DelaySlot)
{
CAUSE_REGISTER.BranchDelay = 1;
EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER - 4);
}
else
{
CAUSE_REGISTER.BranchDelay = 0;
EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER);
}
STATUS_REGISTER |= STATUS_EXL;
m_PROGRAM_COUNTER = 0x80000180;
}
bool CRegisters::DoIntrException(bool DelaySlot) bool CRegisters::DoIntrException(bool DelaySlot)
{ {
if ((STATUS_REGISTER & STATUS_IE) == 0 || (STATUS_REGISTER & STATUS_EXL) != 0 || (STATUS_REGISTER & STATUS_ERL) != 0) if ((STATUS_REGISTER & STATUS_IE) == 0 || (STATUS_REGISTER & STATUS_EXL) != 0 || (STATUS_REGISTER & STATUS_ERL) != 0)

1
Source/Project64-core/N64System/Mips/Register.h
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@ -404,7 +404,6 @@ public:
void CheckInterrupts(); void CheckInterrupts();
void DoAddressError(bool DelaySlot, uint64_t BadVaddr, bool FromRead); void DoAddressError(bool DelaySlot, uint64_t BadVaddr, bool FromRead);
void DoBreakException(bool DelaySlot);
bool DoIntrException(bool DelaySlot); bool DoIntrException(bool DelaySlot);
void DoTLBReadMiss(bool DelaySlot, uint64_t BadVaddr); void DoTLBReadMiss(bool DelaySlot, uint64_t BadVaddr);
void DoTLBWriteMiss(bool DelaySlot, uint64_t BadVaddr); void DoTLBWriteMiss(bool DelaySlot, uint64_t BadVaddr);

6
Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp
View File

@ -9479,8 +9479,10 @@ void CX86RecompilerOps::CompileExit(uint32_t JumpPC, uint32_t TargetPC, CRegInfo
ExitCodeBlock(); ExitCodeBlock();
break; break;
case ExitReason_Break: case ExitReason_Break:
m_Assembler.PushImm32(InDelaySlot ? "true" : "false", InDelaySlot); m_Assembler.MoveConstToVariable(&g_System->m_PipelineStage, "System->m_PipelineStage", m_PipelineStage == PIPELINE_STAGE_JUMP || m_PipelineStage == PIPELINE_STAGE_DELAY_SLOT ? PIPELINE_STAGE_JUMP : PIPELINE_STAGE_NORMAL);
m_Assembler.CallThis((uint32_t)g_Reg, AddressOf(&CRegisters::DoBreakException), "CRegisters::DoBreakException", 8); m_Assembler.push(0);
m_Assembler.PushImm32("EXC_BREAK", EXC_BREAK);
m_Assembler.CallThis((uint32_t)g_Reg, AddressOf(&CRegisters::TriggerException), "CRegisters::TriggerException", 12);
ExitCodeBlock(); ExitCodeBlock();
break; break;
case ExitReason_COP1Unuseable: case ExitReason_COP1Unuseable: