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Core: LL/LLD store address

This commit is contained in:
zilmar 2023-10-12 19:55:29 +10:30
parent a6405cfa2d
commit 3a68d3d92a
4 changed files with 12 additions and 4 deletions
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10
Source/Project64-core/N64System/Interpreter/InterpreterOps.cpp
View File

@ -1192,6 +1192,10 @@ void R4300iOp::LL()
{ {
_GPR[m_Opcode.rt].DW = (int32_t)MemoryValue; _GPR[m_Opcode.rt].DW = (int32_t)MemoryValue;
(*_LLBit) = 1; (*_LLBit) = 1;
uint32_t PhysicalAddr;
bool MemoryUsed;
g_TLB->VAddrToPAddr(Address, PhysicalAddr, MemoryUsed);
_CP0[17] = PhysicalAddr >> 4;
} }
} }
@ -1234,6 +1238,10 @@ void R4300iOp::LLD()
if (g_MMU->LD_Memory(Address, _GPR[m_Opcode.rt].UDW)) if (g_MMU->LD_Memory(Address, _GPR[m_Opcode.rt].UDW))
{ {
(*_LLBit) = 1; (*_LLBit) = 1;
uint32_t PhysicalAddr;
bool MemoryUsed;
g_TLB->VAddrToPAddr(Address, PhysicalAddr, MemoryUsed);
_CP0[17] = PhysicalAddr >> 4;
} }
} }
@ -2151,7 +2159,7 @@ void R4300iOp::COP1_S_MOV()
{ {
return; return;
} }
*_FPR_UDW[m_Opcode.fd] = (*(uint64_t *)_FPR_D[m_Opcode.fs] & 0xFFFFFFFF00000000ll) | *(uint32_t *)_FPR_S_L[m_Opcode.fs]; *_FPR_UDW[m_Opcode.fd] = (*(uint64_t *)_FPR_D[m_Opcode.fs] & 0xFFFFFFFF00000000ll) | *(uint32_t *)_FPR_S_L[m_Opcode.fs];
} }
void R4300iOp::COP1_S_NEG() void R4300iOp::COP1_S_NEG()

2
Source/Project64-core/N64System/MemoryHandler/DisplayControlRegHandler.cpp
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@ -93,7 +93,7 @@ bool DisplayControlRegHandler::Write32(uint32_t Address, uint32_t Value, uint32_
break; break;
case 0x04100004: case 0x04100004:
DPC_END_REG = MaskedValue & 0xFFFFF8; DPC_END_REG = MaskedValue & 0xFFFFF8;
if (DPC_STATUS_REG & DPC_STATUS_START_VALID) if (DPC_STATUS_REG & DPC_STATUS_START_VALID)
{ {
DPC_CURRENT_REG = DPC_START_REG; DPC_CURRENT_REG = DPC_START_REG;
DPC_STATUS_REG &= ~DPC_STATUS_START_VALID; DPC_STATUS_REG &= ~DPC_STATUS_START_VALID;

2
Source/Project64-core/N64System/Mips/Register.cpp
View File

@ -768,7 +768,7 @@ void CRegisters::FixFpuLocations()
m_FPR_S[i] = STATUS_REGISTER.FR == 0 ? &m_FPR[i & ~1].F[i & 1] : &m_FPR[i].F[0]; m_FPR_S[i] = STATUS_REGISTER.FR == 0 ? &m_FPR[i & ~1].F[i & 1] : &m_FPR[i].F[0];
m_FPR_S_L[i] = STATUS_REGISTER.FR == 0 ? &m_FPR[i & ~1].F[0] : &m_FPR[i].F[0]; m_FPR_S_L[i] = STATUS_REGISTER.FR == 0 ? &m_FPR[i & ~1].F[0] : &m_FPR[i].F[0];
m_FPR_D[i] = STATUS_REGISTER.FR == 0 ? &m_FPR[i & ~1].D : &m_FPR[i].D; m_FPR_D[i] = STATUS_REGISTER.FR == 0 ? &m_FPR[i & ~1].D : &m_FPR[i].D;
} }
} }
bool CRegisters::DoIntrException() bool CRegisters::DoIntrException()

2
Source/Project64-core/N64System/Mips/TLB.cpp
View File

@ -323,7 +323,7 @@ bool CTLB::VAddrToPAddr(uint64_t VAddr, uint32_t & PAddr, bool & MemoryUnused)
} }
if (Segment == MemorySegment_Direct32 || Segment == MemorySegment_Cached32) if (Segment == MemorySegment_Direct32 || Segment == MemorySegment_Cached32)
{ {
PAddr = VAddr & 0x1FFFFFFF; PAddr = VAddr & 0x7FFFFFFF;
return true; return true;
} }
return false; return false;