More fixes related to changes in ABL

This commit is contained in:
zilmar 2012-10-23 19:06:13 +11:00
parent a75034a723
commit 39d57a5750
5 changed files with 67 additions and 22 deletions

View File

@ -535,14 +535,15 @@ bool CCodeBlock::AnalyzeInstruction ( DWORD PC, DWORD & TargetPC, DWORD & Contin
TargetPC = PC + ((short)Command.offset << 2) + 4;
if (TargetPC == PC + 8)
{
_Notify->BreakPoint(__FILE__,__LINE__);
TargetPC = (DWORD)-1;
} else {
if (TargetPC == PC)
{
_Notify->BreakPoint(__FILE__,__LINE__);
}
ContinuePC = PC + 8;
IncludeDelaySlot = true;
}
if (TargetPC == PC)
{
_Notify->BreakPoint(__FILE__,__LINE__);
}
ContinuePC = PC + 8;
IncludeDelaySlot = true;
break;
case R4300i_COP1_BC_BCFL:
case R4300i_COP1_BC_BCTL:
@ -566,18 +567,21 @@ bool CCodeBlock::AnalyzeInstruction ( DWORD PC, DWORD & TargetPC, DWORD & Contin
break;
case R4300i_ANDI: case R4300i_ORI: case R4300i_XORI: case R4300i_LUI:
case R4300i_ADDI: case R4300i_ADDIU: case R4300i_SLTI: case R4300i_SLTIU:
case R4300i_DADDI: case R4300i_DADDIU: case R4300i_LB: case R4300i_LH:
case R4300i_LW: case R4300i_LWL: case R4300i_LWR: case R4300i_LDL:
case R4300i_LDR: case R4300i_LBU: case R4300i_LHU: case R4300i_LD:
case R4300i_LWC1: case R4300i_LDC1: case R4300i_CACHE: case R4300i_SB:
case R4300i_SH: case R4300i_SW: case R4300i_SWR: case R4300i_SWL:
case R4300i_SWC1: case R4300i_SDC1: case R4300i_SD:
case R4300i_DADDI: case R4300i_DADDIU: case R4300i_LDL: case R4300i_LDR:
case R4300i_LB: case R4300i_LH: case R4300i_LWL: case R4300i_LW:
case R4300i_LBU: case R4300i_LHU: case R4300i_LWR: case R4300i_LWU:
case R4300i_SB: case R4300i_SH: case R4300i_SWL: case R4300i_SW:
case R4300i_SWR: case R4300i_CACHE: case R4300i_LWC1: case R4300i_LDC1:
case R4300i_LD: case R4300i_SWC1: case R4300i_SDC1: case R4300i_SD:
break;
case R4300i_BEQL:
TargetPC = PC + ((short)Command.offset << 2) + 4;
if (TargetPC == PC)
{
_Notify->BreakPoint(__FILE__,__LINE__);
if (!DelaySlotEffectsCompare(PC,Command.rs,Command.rt))
{
PermLoop = true;
}
}
if (Command.rs != 0 || Command.rt != 0)
{
@ -602,6 +606,11 @@ bool CCodeBlock::AnalyzeInstruction ( DWORD PC, DWORD & TargetPC, DWORD & Contin
IncludeDelaySlot = true;
break;
default:
if (Command.Hex == 0x7C1C97C0)
{
EndBlock = true;
break;
}
_Notify->BreakPoint(__FILE__,__LINE__);
return false;
}

View File

@ -868,6 +868,16 @@ bool CCodeSection::ParentContinue ( void )
return true;
}
/*int TestValue = 0;
void TestFunc ( void )
{
TestValue += 1;
if (TestValue >= 4)
{
_Notify->BreakPoint(__FILE__,__LINE__);
}
}*/
bool CCodeSection::GenerateX86Code ( DWORD Test )
{
if (this == NULL) { return false; }
@ -946,6 +956,25 @@ bool CCodeSection::GenerateX86Code ( DWORD Test )
}
}*/
/*if (m_CompilePC == 0x801C1B88)
{
BeforeCallDirect(m_RegWorkingSet);
Call_Direct(AddressOf(TestFunc), "TestFunc");
AfterCallDirect(m_RegWorkingSet);
}*/
/*if (m_CompilePC >= 0x801C1AF8 && m_CompilePC <= 0x801C1C00 && m_NextInstruction == NORMAL)
{
UpdateCounters(m_RegWorkingSet,false,true);
MoveConstToVariable(m_CompilePC,&_Reg->m_PROGRAM_COUNTER,"PROGRAM_COUNTER");
if (_SyncSystem) {
BeforeCallDirect(m_RegWorkingSet);
MoveConstToX86reg((DWORD)_BaseSystem,x86_ECX);
Call_Direct(AddressOf(&CN64System::SyncSystemPC), "CN64System::SyncSystemPC");
AfterCallDirect(m_RegWorkingSet);
}
}*/
/*if ((m_CompilePC == 0x80263900) && m_NextInstruction == NORMAL)
{
X86BreakPoint(__FILE__,__LINE__);
@ -1690,6 +1719,8 @@ bool CCodeSection::InheritParentInfo ( void )
CJumpInfo * JumpInfo = ParentList[FirstParent].JumpInfo;
m_RegWorkingSet = JumpInfo->RegSet;
m_RegWorkingSet.ResetX86Protection();
if (JumpInfo->LinkLocation != NULL) {
CPU_Message(" Section_%d (from %d):",m_SectionID,Parent->m_SectionID);
SetJump32(JumpInfo->LinkLocation,(DWORD *)m_RecompPos);

View File

@ -392,12 +392,10 @@ bool LoopAnalysis::CheckLoopRegisterUsage( CCodeSection * Section)
}
if (m_PC == Section->m_Jump.TargetPC)
{
_Notify->BreakPoint(__FILE__,__LINE__);
#ifdef tofix
if (!DelaySlotEffectsCompare(m_PC,m_Command.rs,m_Command.rt)) {
Section->m_Jump.PermLoop = true;
if (!DelaySlotEffectsCompare(m_PC,m_Command.rs,m_Command.rt) && !Section->m_Jump.PermLoop)
{
_Notify->BreakPoint(__FILE__,__LINE__);
}
#endif
}
#endif
}

View File

@ -642,8 +642,11 @@ void CRecompilerOps::BEQ_Compare (void) {
m_Section->m_Jump.FallThrough = FALSE;
m_Section->m_Cont.FallThrough = TRUE;
}
} else if (IsMapped(m_Opcode.rs) && IsMapped(m_Opcode.rt)) {
if (Is64Bit(m_Opcode.rs) || Is64Bit(m_Opcode.rt)) {
}
else if (IsMapped(m_Opcode.rs) && IsMapped(m_Opcode.rt))
{
if ((Is64Bit(m_Opcode.rs) || Is64Bit(m_Opcode.rt)) && !b32BitCore())
{
ProtectGPR(m_Opcode.rs);
ProtectGPR(m_Opcode.rt);

View File

@ -632,7 +632,11 @@ void CRegInfo::Map_GPR_64bit ( int MipsReg, int MipsRegToLoad)
if (Is32Bit(MipsReg)) {
SetX86Protected(x86lo,TRUE);
x86Hi = FreeX86Reg();
if (x86Hi < 0) { _Notify->DisplayError("Map_GPR_64bit\n\nOut of registers"); return; }
if (x86Hi == x86_Unknown)
{
_Notify->BreakPoint(__FILE__,__LINE__);
return;
}
SetX86Protected(x86Hi,TRUE);
CPU_Message(" regcache: allocate %s to hi word of %s",x86_Name(x86Hi),CRegName::GPR[MipsReg]);