More fixes related to changes in ABL
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a75034a723
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@ -535,14 +535,15 @@ bool CCodeBlock::AnalyzeInstruction ( DWORD PC, DWORD & TargetPC, DWORD & Contin
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TargetPC = PC + ((short)Command.offset << 2) + 4;
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if (TargetPC == PC + 8)
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{
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_Notify->BreakPoint(__FILE__,__LINE__);
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TargetPC = (DWORD)-1;
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} else {
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if (TargetPC == PC)
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{
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_Notify->BreakPoint(__FILE__,__LINE__);
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}
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ContinuePC = PC + 8;
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IncludeDelaySlot = true;
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}
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if (TargetPC == PC)
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{
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_Notify->BreakPoint(__FILE__,__LINE__);
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}
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ContinuePC = PC + 8;
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IncludeDelaySlot = true;
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break;
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case R4300i_COP1_BC_BCFL:
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case R4300i_COP1_BC_BCTL:
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@ -566,18 +567,21 @@ bool CCodeBlock::AnalyzeInstruction ( DWORD PC, DWORD & TargetPC, DWORD & Contin
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break;
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case R4300i_ANDI: case R4300i_ORI: case R4300i_XORI: case R4300i_LUI:
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case R4300i_ADDI: case R4300i_ADDIU: case R4300i_SLTI: case R4300i_SLTIU:
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case R4300i_DADDI: case R4300i_DADDIU: case R4300i_LB: case R4300i_LH:
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case R4300i_LW: case R4300i_LWL: case R4300i_LWR: case R4300i_LDL:
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case R4300i_LDR: case R4300i_LBU: case R4300i_LHU: case R4300i_LD:
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case R4300i_LWC1: case R4300i_LDC1: case R4300i_CACHE: case R4300i_SB:
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case R4300i_SH: case R4300i_SW: case R4300i_SWR: case R4300i_SWL:
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case R4300i_SWC1: case R4300i_SDC1: case R4300i_SD:
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case R4300i_DADDI: case R4300i_DADDIU: case R4300i_LDL: case R4300i_LDR:
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case R4300i_LB: case R4300i_LH: case R4300i_LWL: case R4300i_LW:
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case R4300i_LBU: case R4300i_LHU: case R4300i_LWR: case R4300i_LWU:
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case R4300i_SB: case R4300i_SH: case R4300i_SWL: case R4300i_SW:
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case R4300i_SWR: case R4300i_CACHE: case R4300i_LWC1: case R4300i_LDC1:
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case R4300i_LD: case R4300i_SWC1: case R4300i_SDC1: case R4300i_SD:
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break;
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case R4300i_BEQL:
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TargetPC = PC + ((short)Command.offset << 2) + 4;
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if (TargetPC == PC)
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{
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_Notify->BreakPoint(__FILE__,__LINE__);
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if (!DelaySlotEffectsCompare(PC,Command.rs,Command.rt))
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{
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PermLoop = true;
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}
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}
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if (Command.rs != 0 || Command.rt != 0)
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{
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@ -602,6 +606,11 @@ bool CCodeBlock::AnalyzeInstruction ( DWORD PC, DWORD & TargetPC, DWORD & Contin
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IncludeDelaySlot = true;
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break;
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default:
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if (Command.Hex == 0x7C1C97C0)
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{
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EndBlock = true;
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break;
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}
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_Notify->BreakPoint(__FILE__,__LINE__);
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return false;
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}
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@ -868,6 +868,16 @@ bool CCodeSection::ParentContinue ( void )
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return true;
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}
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/*int TestValue = 0;
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void TestFunc ( void )
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{
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TestValue += 1;
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if (TestValue >= 4)
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{
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_Notify->BreakPoint(__FILE__,__LINE__);
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}
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}*/
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bool CCodeSection::GenerateX86Code ( DWORD Test )
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{
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if (this == NULL) { return false; }
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@ -946,6 +956,25 @@ bool CCodeSection::GenerateX86Code ( DWORD Test )
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}
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}*/
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/*if (m_CompilePC == 0x801C1B88)
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{
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BeforeCallDirect(m_RegWorkingSet);
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Call_Direct(AddressOf(TestFunc), "TestFunc");
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AfterCallDirect(m_RegWorkingSet);
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}*/
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/*if (m_CompilePC >= 0x801C1AF8 && m_CompilePC <= 0x801C1C00 && m_NextInstruction == NORMAL)
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{
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UpdateCounters(m_RegWorkingSet,false,true);
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MoveConstToVariable(m_CompilePC,&_Reg->m_PROGRAM_COUNTER,"PROGRAM_COUNTER");
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if (_SyncSystem) {
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BeforeCallDirect(m_RegWorkingSet);
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MoveConstToX86reg((DWORD)_BaseSystem,x86_ECX);
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Call_Direct(AddressOf(&CN64System::SyncSystemPC), "CN64System::SyncSystemPC");
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AfterCallDirect(m_RegWorkingSet);
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}
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}*/
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/*if ((m_CompilePC == 0x80263900) && m_NextInstruction == NORMAL)
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{
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X86BreakPoint(__FILE__,__LINE__);
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@ -1690,6 +1719,8 @@ bool CCodeSection::InheritParentInfo ( void )
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CJumpInfo * JumpInfo = ParentList[FirstParent].JumpInfo;
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m_RegWorkingSet = JumpInfo->RegSet;
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m_RegWorkingSet.ResetX86Protection();
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if (JumpInfo->LinkLocation != NULL) {
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CPU_Message(" Section_%d (from %d):",m_SectionID,Parent->m_SectionID);
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SetJump32(JumpInfo->LinkLocation,(DWORD *)m_RecompPos);
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@ -392,12 +392,10 @@ bool LoopAnalysis::CheckLoopRegisterUsage( CCodeSection * Section)
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}
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if (m_PC == Section->m_Jump.TargetPC)
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{
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_Notify->BreakPoint(__FILE__,__LINE__);
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#ifdef tofix
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if (!DelaySlotEffectsCompare(m_PC,m_Command.rs,m_Command.rt)) {
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Section->m_Jump.PermLoop = true;
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if (!DelaySlotEffectsCompare(m_PC,m_Command.rs,m_Command.rt) && !Section->m_Jump.PermLoop)
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{
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_Notify->BreakPoint(__FILE__,__LINE__);
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}
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#endif
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}
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#endif
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}
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@ -642,8 +642,11 @@ void CRecompilerOps::BEQ_Compare (void) {
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m_Section->m_Jump.FallThrough = FALSE;
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m_Section->m_Cont.FallThrough = TRUE;
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}
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} else if (IsMapped(m_Opcode.rs) && IsMapped(m_Opcode.rt)) {
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if (Is64Bit(m_Opcode.rs) || Is64Bit(m_Opcode.rt)) {
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}
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else if (IsMapped(m_Opcode.rs) && IsMapped(m_Opcode.rt))
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{
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if ((Is64Bit(m_Opcode.rs) || Is64Bit(m_Opcode.rt)) && !b32BitCore())
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{
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ProtectGPR(m_Opcode.rs);
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ProtectGPR(m_Opcode.rt);
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@ -632,7 +632,11 @@ void CRegInfo::Map_GPR_64bit ( int MipsReg, int MipsRegToLoad)
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if (Is32Bit(MipsReg)) {
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SetX86Protected(x86lo,TRUE);
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x86Hi = FreeX86Reg();
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if (x86Hi < 0) { _Notify->DisplayError("Map_GPR_64bit\n\nOut of registers"); return; }
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if (x86Hi == x86_Unknown)
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{
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_Notify->BreakPoint(__FILE__,__LINE__);
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return;
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}
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SetX86Protected(x86Hi,TRUE);
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CPU_Message(" regcache: allocate %s to hi word of %s",x86_Name(x86Hi),CRegName::GPR[MipsReg]);
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