Matched RSP interpreter more closely
I have only seen the edgecase for SQV happen when IsRegConst(RSPOpC.base) == TRUE. Changing SQV fixed Telefoot / Mia Ham. I optimized VAND, for games like Kirby64.
This commit is contained in:
LegendOfDragoon
parent
02fe2e7241
commit
1cb03b4120
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@ -278,11 +278,10 @@ DWORD WriteToAccum2 (int Location, int PC, BOOL RecursiveCall) {
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case RSP_VECTOR_VEQ:
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case RSP_VECTOR_VGE:
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case RSP_VECTOR_VMRG:
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case RSP_VECTOR_VMOV:
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if (Location == Low16BitAccum) { return FALSE; }
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break;
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case RSP_VECTOR_VMOV:
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break;
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case RSP_VECTOR_VSAW:
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return TRUE;
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default:
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@ -3134,10 +3134,11 @@ void Compile_Vector_VADD ( void ) {
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AdcX86RegToX86Reg(x86_EAX, x86_EBX);
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if (bWriteToAccum == TRUE) {
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MoveX86regHalfToVariable(x86_EAX, &RSP_ACCUM[el].HW[1], "RSP_ACCUM[el].HW[1]");
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if (bWriteToAccum != FALSE) {
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el);
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MoveX86regHalfToVariable(x86_EAX, &RSP_ACCUM[el].HW[1], Reg);
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}
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if (bWriteToDest == TRUE) {
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if (bWriteToDest != FALSE) {
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CompX86RegToX86Reg(x86_EAX, x86_ESI);
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CondMoveGreater(x86_EAX, x86_ESI);
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CompX86RegToX86Reg(x86_EAX, x86_EDI);
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@ -3248,10 +3249,12 @@ void Compile_Vector_VSUB ( void ) {
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SbbX86RegToX86Reg(x86_EAX, x86_EBX);
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if (bWriteToAccum == TRUE) {
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MoveX86regHalfToVariable(x86_EAX, &RSP_ACCUM[el].HW[1], "RSP_ACCUM[el].HW[1]");
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if (bWriteToAccum != FALSE) {
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el);
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MoveX86regHalfToVariable(x86_EAX, &RSP_ACCUM[el].HW[1], Reg);
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}
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if (bWriteToDest == TRUE) {
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if (bWriteToDest != FALSE) {
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CompX86RegToX86Reg(x86_EAX, x86_ESI);
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CondMoveGreater(x86_EAX, x86_ESI);
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CompX86RegToX86Reg(x86_EAX, x86_EDI);
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@ -3408,10 +3411,12 @@ void Compile_Vector_VADDC ( void ) {
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}
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OrX86RegToX86Reg(x86_ECX, x86_EDX);
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if (bWriteToAccum == TRUE) {
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MoveX86regHalfToVariable(x86_EAX, &RSP_ACCUM[el].HW[1], "RSP_ACCUM[el].HW[1]");
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if (bWriteToAccum != FALSE) {
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el);
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MoveX86regHalfToVariable(x86_EAX, &RSP_ACCUM[el].HW[1], Reg);
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}
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if (bWriteToDest == TRUE) {
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if (bWriteToDest != FALSE) {
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sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.sa, el);
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MoveX86regHalfToVariable(x86_EAX, &RSP_Vect[RSPOpC.sa].HW[el], Reg);
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}
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@ -3470,10 +3475,11 @@ void Compile_Vector_VSUBC ( void ) {
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ShiftLeftSignImmed(x86_EDX, 7 - el);
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OrX86RegToX86Reg(x86_ECX, x86_EDX);
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if (bWriteToAccum == TRUE) {
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MoveX86regHalfToVariable(x86_EAX, &RSP_ACCUM[el].HW[1], "RSP_ACCUM[el].HW[1]");
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if (bWriteToAccum != FALSE) {
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el);
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MoveX86regHalfToVariable(x86_EAX, &RSP_ACCUM[el].HW[1], Reg);
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}
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if (bWriteToDest == TRUE) {
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if (bWriteToDest != FALSE) {
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sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.sa, el);
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MoveX86regHalfToVariable(x86_EAX, &RSP_Vect[RSPOpC.sa].HW[el], Reg);
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}
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@ -3690,6 +3696,7 @@ BOOL Compile_Vector_VAND_MMX ( void ) {
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void Compile_Vector_VAND ( void ) {
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char Reg[256];
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int el, del, count;
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BOOL bWriteToDest = WriteToVectorDest(RSPOpC.sa, CompilePC);
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BOOL bElement = ((RSPOpC.rs & 0x0f) >= 8) ? TRUE : FALSE;
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BOOL bWriteToAccum = WriteToAccum(Low16BitAccum, CompilePC);
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@ -3726,11 +3733,13 @@ void Compile_Vector_VAND ( void ) {
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AndX86RegHalfToX86RegHalf(x86_EAX, x86_EBX);
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}
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sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.sa, el);
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MoveX86regHalfToVariable(x86_EAX, &RSP_Vect[RSPOpC.sa].HW[el], Reg);
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if (bWriteToDest != FALSE) {
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sprintf(Reg, "RSP_Vect[%i].HW[%i]", RSPOpC.sa, el);
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MoveX86regHalfToVariable(x86_EAX, &RSP_Vect[RSPOpC.sa].HW[el], Reg);
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}
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if (bWriteToAccum != FALSE) {
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sprintf(Reg, "RSP_ACCUM[el].HW[1]", el);
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", el);
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MoveX86regHalfToVariable(x86_EAX, &RSP_ACCUM[el].HW[1], Reg);
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}
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}
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@ -3964,13 +3973,22 @@ void Compile_Vector_VRCPH ( void ) {
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void Compile_Vector_VMOV ( void ) {
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char Reg[256];
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int el;
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int el, count;
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BOOL bWriteToAccum = WriteToAccum(Low16BitAccum, CompilePC);
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#ifndef CompileVmov
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Cheat_r4300iOpcode(RSP_Vector_VMOV, "RSP_Vector_VMOV"); return;
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#endif
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#ifndef CompileVmov
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Cheat_r4300iOpcode(RSP_Vector_VMOV,"RSP_Vector_VMOV"); return;
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#endif
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CPU_Message(" %X %s", CompilePC, RSPOpcodeName(RSPOpC.Hex, CompilePC));
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CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
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if (bWriteToAccum){
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for (count = 0; count < 8; count++) {
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sprintf(Reg, "RSP_Vect[%i].UHW[%i]", RSPOpC.rt, EleSpec[RSPOpC.rs].B[count]);
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MoveVariableToX86regHalf(&RSP_Vect[RSPOpC.rt].UHW[EleSpec[RSPOpC.rs].B[count]], Reg, x86_EAX);
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sprintf(Reg, "RSP_ACCUM[%i].HW[1]", count);
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MoveX86regHalfToVariable(x86_EAX, &RSP_ACCUM[count].HW[1], Reg);
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}
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}
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el = EleSpec[RSPOpC.rs].B[(RSPOpC.rd & 0x7)];
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sprintf(Reg, "RSP_Vect[%i].UHW[%i]", RSPOpC.rt, el);
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@ -4585,32 +4603,32 @@ void Compile_Opcode_SLV ( void ) {
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void Compile_Opcode_SDV ( void ) {
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char Reg[256];
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int offset = (RSPOpC.voffset << 3);
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BYTE * Jump[2], * LoopEntry;
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BYTE * Jump[2], *LoopEntry;
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//if ((RSPOpC.del & 0x7) != 0) {
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// rsp_UnknownOpcode();
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// return;
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//}
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#ifndef CompileSdv
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Cheat_r4300iOpcode(RSP_Opcode_SDV,"RSP_Opcode_SDV"); return;
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#endif
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CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
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#ifndef CompileSdv
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Cheat_r4300iOpcode(RSP_Opcode_SDV, "RSP_Opcode_SDV"); return;
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#endif
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CPU_Message(" %X %s", CompilePC, RSPOpcodeName(RSPOpC.Hex, CompilePC));
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if (IsRegConst(RSPOpC.base) == TRUE) {
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DWORD Addr = (MipsRegConst(RSPOpC.base) + offset) & 0xfff;
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if ((Addr & 3) != 0) {
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CompilerWarning("Unaligned SDV at constant address PC = %04X", CompilePC);
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Cheat_r4300iOpcodeNoMessage(RSP_Opcode_SDV,"RSP_Opcode_SDV");
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Cheat_r4300iOpcodeNoMessage(RSP_Opcode_SDV, "RSP_Opcode_SDV");
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return;
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}
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sprintf(Reg, "RSP_Vect[%i].B[%i]", RSPOpC.rt, 16 - RSPOpC.del - 4);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[16 - RSPOpC.del - 4], Reg, x86_EAX);
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sprintf(Reg, "RSP_Vect[%i].B[%i]", RSPOpC.rt, 16 - RSPOpC.del - 8);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[16 - RSPOpC.del - 8], Reg, x86_EBX);
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sprintf(Reg, "RSP_Vect[%i].B[%i]", RSPOpC.rt, (16 - RSPOpC.del - 4) & 0xF);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[(16 - RSPOpC.del - 4) & 0xF], Reg, x86_EAX);
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sprintf(Reg, "RSP_Vect[%i].B[%i]", RSPOpC.rt, (16 - RSPOpC.del - 8) & 0xF);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[(16 - RSPOpC.del - 8) & 0xF], Reg, x86_EBX);
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sprintf(Reg, "Dmem + %Xh", Addr);
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MoveX86regToVariable(x86_EAX, RSPInfo.DMEM + Addr, Reg);
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@ -4618,7 +4636,7 @@ void Compile_Opcode_SDV ( void ) {
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MoveX86regToVariable(x86_EBX, RSPInfo.DMEM + Addr + 4, Reg);
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return;
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}
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MoveVariableToX86reg(&RSP_GPR[RSPOpC.base].UW, GPR_Name(RSPOpC.base), x86_EBX);
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if (offset != 0) {
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AddConstToX86Reg(x86_EBX, offset);
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@ -4627,11 +4645,11 @@ void Compile_Opcode_SDV ( void ) {
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TestConstToX86Reg(3, x86_EBX);
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JneLabel32("Unaligned", 0);
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Jump[0] = RecompPos - 4;
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CompilerToggleBuffer();
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CPU_Message(" Unaligned:");
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x86_SetBranch32b((DWORD*)Jump[0], (DWORD*)RecompPos);
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sprintf(Reg, "RSP_Vect[%i].UB[%i]", RSPOpC.rt, 15 - RSPOpC.del);
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MoveOffsetToX86reg((DWORD)&RSP_Vect[RSPOpC.rt].UB[15 - RSPOpC.del], Reg, x86_EDI);
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MoveConstToX86reg(8, x86_ECX);
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@ -4652,10 +4670,10 @@ void Compile_Opcode_SDV ( void ) {
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Jump[1] = RecompPos - 4;
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CompilerToggleBuffer();
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sprintf(Reg, "RSP_Vect[%i].B[%i]", RSPOpC.rt, 16 - RSPOpC.del - 4);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[16 - RSPOpC.del - 4], Reg, x86_EAX);
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sprintf(Reg, "RSP_Vect[%i].B[%i]", RSPOpC.rt, 16 - RSPOpC.del - 8);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[16 - RSPOpC.del - 8], Reg, x86_ECX);
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sprintf(Reg, "RSP_Vect[%i].B[%i]", RSPOpC.rt, (16 - RSPOpC.del - 4) & 0xF);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[(16 - RSPOpC.del - 4) & 0xF], Reg, x86_EAX);
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sprintf(Reg, "RSP_Vect[%i].B[%i]", RSPOpC.rt, (16 - RSPOpC.del - 8) & 0xF);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[(16 - RSPOpC.del - 8) & 0xF], Reg, x86_ECX);
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MoveX86regToN64Mem(x86_EAX, x86_EBX);
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MoveX86regToN64MemDisp(x86_ECX, x86_EBX, 4);
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@ -4674,10 +4692,10 @@ void Compile_Opcode_SQV ( void ) {
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CPU_Message(" %X %s",CompilePC,RSPOpcodeName(RSPOpC.Hex,CompilePC));
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if (RSPOpC.del != 0) {
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rsp_UnknownOpcode();
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return;
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}
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//if (RSPOpC.del != 0) {
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// rsp_UnknownOpcode();
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// return;
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//}
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if (IsRegConst(RSPOpC.base) == TRUE) {
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DWORD Addr = (MipsRegConst(RSPOpC.base) + offset) & 0xfff;
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@ -4693,14 +4711,25 @@ void Compile_Opcode_SQV ( void ) {
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*/
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if (IsSseEnabled == FALSE) {
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sprintf(Reg, "RSP_Vect[%i].B[12]", RSPOpC.rt);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[12], Reg, x86_EAX);
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sprintf(Reg, "RSP_Vect[%i].B[8]", RSPOpC.rt);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[8], Reg, x86_EBX);
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sprintf(Reg, "RSP_Vect[%i].B[4]", RSPOpC.rt);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[4], Reg, x86_ECX);
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sprintf(Reg, "RSP_Vect[%i].B[0]", RSPOpC.rt);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[0], Reg, x86_EDX);
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if (RSPOpC.del == 12) {
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sprintf(Reg, "RSP_Vect[%i].B[0]", RSPOpC.rt);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[0], Reg, x86_EDX);
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sprintf(Reg, "RSP_Vect[%i].B[12]", RSPOpC.rt);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[12], Reg, x86_EAX);
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sprintf(Reg, "RSP_Vect[%i].B[8]", RSPOpC.rt);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[8], Reg, x86_EBX);
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sprintf(Reg, "RSP_Vect[%i].B[4]", RSPOpC.rt);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[4], Reg, x86_ECX);
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} else {
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sprintf(Reg, "RSP_Vect[%i].B[12]", RSPOpC.rt);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[12], Reg, x86_EAX);
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sprintf(Reg, "RSP_Vect[%i].B[8]", RSPOpC.rt);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[8], Reg, x86_EBX);
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sprintf(Reg, "RSP_Vect[%i].B[4]", RSPOpC.rt);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[4], Reg, x86_ECX);
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sprintf(Reg, "RSP_Vect[%i].B[0]", RSPOpC.rt);
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MoveVariableToX86reg(&RSP_Vect[RSPOpC.rt].B[0], Reg, x86_EDX);
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}
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sprintf(Reg, "Dmem+%Xh+0", Addr);
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MoveX86regToVariable(x86_EAX, RSPInfo.DMEM + Addr + 0, Reg);
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@ -4713,7 +4742,11 @@ void Compile_Opcode_SQV ( void ) {
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} else {
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sprintf(Reg, "RSP_Vect[%i].B[0]", RSPOpC.rt);
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SseMoveAlignedVariableToReg(&RSP_Vect[RSPOpC.rt].B[0], Reg, x86_XMM0);
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SseShuffleReg(x86_XMM0, x86_MM0, 0x1b);
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if (RSPOpC.del == 12) {
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SseShuffleReg(x86_XMM0, x86_MM0, 0x6c);
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} else {
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SseShuffleReg(x86_XMM0, x86_MM0, 0x1b);
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}
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sprintf(Reg, "Dmem+%Xh", Addr);
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SseMoveUnalignedRegToVariable(x86_XMM0, RSPInfo.DMEM + Addr, Reg);
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}
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