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[Project64] Get Register class to use standard type

This commit is contained in:
zilmar 2015-11-09 07:45:41 +11:00
parent 21b80c240f
commit 1a09c2baea
5 changed files with 852 additions and 834 deletions
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4
Source/Project64/N64 System/Interpreter/Interpreter CPU.cpp
View File

@ -264,7 +264,7 @@ void CInterpreterCPU::InPermLoop()
void CInterpreterCPU::ExecuteCPU()
{
bool & Done = g_System->m_EndEmulation;
DWORD & PROGRAM_COUNTER = *_PROGRAM_COUNTER;
uint32_t & PROGRAM_COUNTER = *_PROGRAM_COUNTER;
OPCODE & Opcode = R4300iOp::m_Opcode;
DWORD & JumpToLocation = R4300iOp::m_JumpToLocation;
bool & TestTimer = R4300iOp::m_TestTimer;
@ -350,7 +350,7 @@ void CInterpreterCPU::ExecuteCPU()
void CInterpreterCPU::ExecuteOps(int Cycles)
{
bool & Done = g_System->m_EndEmulation;
DWORD & PROGRAM_COUNTER = *_PROGRAM_COUNTER;
uint32_t & PROGRAM_COUNTER = *_PROGRAM_COUNTER;
OPCODE & Opcode = R4300iOp::m_Opcode;
DWORD & JumpToLocation = R4300iOp::m_JumpToLocation;
bool & TestTimer = R4300iOp::m_TestTimer;

44
Source/Project64/N64 System/Mips/Register Class.cpp
View File

@ -46,20 +46,19 @@ const char * CRegName::FPR_Ctrl[32] = {"Revision","Unknown","Unknown","Unknown",
"Unknown","Unknown","Unknown","Unknown","Unknown","Unknown",
"Unknown","Unknown","FCSR"};
DWORD * CSystemRegisters::_PROGRAM_COUNTER = NULL;
uint32_t * CSystemRegisters::_PROGRAM_COUNTER = NULL;
MIPS_DWORD * CSystemRegisters::_GPR = NULL;
MIPS_DWORD * CSystemRegisters::_FPR = NULL;
DWORD * CSystemRegisters::_CP0 = NULL;
uint32_t * CSystemRegisters::_CP0 = NULL;
MIPS_DWORD * CSystemRegisters::_RegHI = NULL;
MIPS_DWORD * CSystemRegisters::_RegLO = NULL;
float ** CSystemRegisters::_FPR_S;
double ** CSystemRegisters::_FPR_D;
DWORD * CSystemRegisters::_FPCR = NULL;
DWORD * CSystemRegisters::_LLBit = NULL;
uint32_t * CSystemRegisters::_FPCR = NULL;
uint32_t * CSystemRegisters::_LLBit = NULL;
ROUNDING_MODE * CSystemRegisters::_RoundingModel = NULL;
CP0registers::CP0registers(DWORD * _CP0) :
CP0registers::CP0registers(uint32_t * _CP0) :
INDEX_REGISTER(_CP0[0]),
RANDOM_REGISTER(_CP0[1]),
ENTRYLO0_REGISTER(_CP0[2]),
@ -80,10 +79,9 @@ CP0registers::CP0registers(DWORD * _CP0) :
ERROREPC_REGISTER(_CP0[30]),
FAKE_CAUSE_REGISTER(_CP0[32])
{
}
Rdram_InterfaceReg::Rdram_InterfaceReg(DWORD * _RdramInterface) :
Rdram_InterfaceReg::Rdram_InterfaceReg(uint32_t * _RdramInterface) :
RDRAM_CONFIG_REG(_RdramInterface[0]),
RDRAM_DEVICE_TYPE_REG(_RdramInterface[0]),
RDRAM_DEVICE_ID_REG(_RdramInterface[1]),
@ -96,10 +94,9 @@ Rdram_InterfaceReg::Rdram_InterfaceReg(DWORD * _RdramInterface) :
RDRAM_ADDR_SELECT_REG(_RdramInterface[8]),
RDRAM_DEVICE_MANUF_REG(_RdramInterface[9])
{
}
Mips_InterfaceReg::Mips_InterfaceReg(DWORD * _MipsInterface) :
Mips_InterfaceReg::Mips_InterfaceReg(uint32_t * _MipsInterface) :
MI_INIT_MODE_REG(_MipsInterface[0]),
MI_MODE_REG(_MipsInterface[0]),
MI_VERSION_REG(_MipsInterface[1]),
@ -107,10 +104,9 @@ Mips_InterfaceReg::Mips_InterfaceReg(DWORD * _MipsInterface) :
MI_INTR_REG(_MipsInterface[2]),
MI_INTR_MASK_REG(_MipsInterface[3])
{
}
Video_InterfaceReg::Video_InterfaceReg(DWORD * _VideoInterface) :
Video_InterfaceReg::Video_InterfaceReg(uint32_t * _VideoInterface) :
VI_STATUS_REG(_VideoInterface[0]),
VI_CONTROL_REG(_VideoInterface[0]),
VI_ORIGIN_REG(_VideoInterface[1]),
@ -135,10 +131,9 @@ Video_InterfaceReg::Video_InterfaceReg(DWORD * _VideoInterface) :
VI_X_SCALE_REG(_VideoInterface[12]),
VI_Y_SCALE_REG(_VideoInterface[13])
{
}
AudioInterfaceReg::AudioInterfaceReg(DWORD * _AudioInterface) :
AudioInterfaceReg::AudioInterfaceReg(uint32_t * _AudioInterface) :
AI_DRAM_ADDR_REG(_AudioInterface[0]),
AI_LEN_REG(_AudioInterface[1]),
AI_CONTROL_REG(_AudioInterface[2]),
@ -146,10 +141,9 @@ AudioInterfaceReg::AudioInterfaceReg(DWORD * _AudioInterface) :
AI_DACRATE_REG(_AudioInterface[4]),
AI_BITRATE_REG(_AudioInterface[5])
{
}
PeripheralInterfaceReg::PeripheralInterfaceReg(DWORD * PeripheralInterface) :
PeripheralInterfaceReg::PeripheralInterfaceReg(uint32_t * PeripheralInterface) :
PI_DRAM_ADDR_REG(PeripheralInterface[0]),
PI_CART_ADDR_REG(PeripheralInterface[1]),
PI_RD_LEN_REG(PeripheralInterface[2]),
@ -166,10 +160,9 @@ PeripheralInterfaceReg::PeripheralInterfaceReg(DWORD * PeripheralInterface) :
PI_BSD_DOM2_PGS_REG(PeripheralInterface[11]),
PI_BSD_DOM2_RLS_REG(PeripheralInterface[12])
{
}
RDRAMInt_InterfaceReg::RDRAMInt_InterfaceReg(DWORD * RdramInterface) :
RDRAMInt_InterfaceReg::RDRAMInt_InterfaceReg(uint32_t * RdramInterface) :
RI_MODE_REG(RdramInterface[0]),
RI_CONFIG_REG(RdramInterface[1]),
RI_CURRENT_LOAD_REG(RdramInterface[2]),
@ -180,10 +173,9 @@ RDRAMInt_InterfaceReg::RDRAMInt_InterfaceReg(DWORD * RdramInterface) :
RI_RERROR_REG(RdramInterface[6]),
RI_WERROR_REG(RdramInterface[7])
{
}
DisplayControlReg::DisplayControlReg(DWORD * _DisplayProcessor) :
DisplayControlReg::DisplayControlReg(uint32_t * _DisplayProcessor) :
DPC_START_REG(_DisplayProcessor[0]),
DPC_END_REG(_DisplayProcessor[1]),
DPC_CURRENT_REG(_DisplayProcessor[2]),
@ -193,10 +185,9 @@ DisplayControlReg::DisplayControlReg(DWORD * _DisplayProcessor) :
DPC_PIPEBUSY_REG(_DisplayProcessor[6]),
DPC_TMEM_REG(_DisplayProcessor[7])
{
}
SigProcessor_InterfaceReg::SigProcessor_InterfaceReg(DWORD * _SignalProcessorInterface) :
SigProcessor_InterfaceReg::SigProcessor_InterfaceReg(uint32_t * _SignalProcessorInterface) :
SP_MEM_ADDR_REG(_SignalProcessorInterface[0]),
SP_DRAM_ADDR_REG(_SignalProcessorInterface[1]),
SP_RD_LEN_REG(_SignalProcessorInterface[2]),
@ -208,16 +199,14 @@ SigProcessor_InterfaceReg::SigProcessor_InterfaceReg(DWORD * _SignalProcessorInt
SP_PC_REG(_SignalProcessorInterface[8]),
SP_IBIST_REG(_SignalProcessorInterface[9])
{
}
Serial_InterfaceReg::Serial_InterfaceReg(DWORD * SerialInterface) :
Serial_InterfaceReg::Serial_InterfaceReg(uint32_t * SerialInterface) :
SI_DRAM_ADDR_REG(SerialInterface[0]),
SI_PIF_ADDR_RD64B_REG(SerialInterface[1]),
SI_PIF_ADDR_WR64B_REG(SerialInterface[2]),
SI_STATUS_REG(SerialInterface[3])
{
}
CRegisters::CRegisters(CN64System * System, CSystemEvents * SystemEvents) :
@ -329,7 +318,7 @@ void CRegisters::CheckInterrupts()
}
}
void CRegisters::DoAddressError(bool DelaySlot, DWORD BadVaddr, bool FromRead)
void CRegisters::DoAddressError(bool DelaySlot, uint32_t BadVaddr, bool FromRead)
{
if (bHaveDebugger())
{
@ -445,7 +434,6 @@ void CRegisters::DoCopUnusableException(bool DelaySlot, int Coprocessor)
m_PROGRAM_COUNTER = 0x80000180;
}
bool CRegisters::DoIntrException(bool DelaySlot)
{
if ((STATUS_REGISTER & STATUS_IE) == 0)
@ -486,7 +474,7 @@ bool CRegisters::DoIntrException(bool DelaySlot)
return true;
}
void CRegisters::DoTLBReadMiss(bool DelaySlot, DWORD BadVaddr)
void CRegisters::DoTLBReadMiss(bool DelaySlot, uint32_t BadVaddr)
{
CAUSE_REGISTER = EXC_RMISS;
BAD_VADDR_REGISTER = BadVaddr;

370
Source/Project64/N64 System/Mips/Register Class.h
View File

@ -13,31 +13,34 @@
//CPO registers by name
class CP0registers
{
CP0registers();
protected:
CP0registers (DWORD * _CP0);
CP0registers (uint32_t * _CP0);
public:
DWORD & INDEX_REGISTER;
DWORD & RANDOM_REGISTER;
DWORD & ENTRYLO0_REGISTER;
DWORD & ENTRYLO1_REGISTER;
DWORD & CONTEXT_REGISTER;
DWORD & PAGE_MASK_REGISTER;
DWORD & WIRED_REGISTER;
DWORD & BAD_VADDR_REGISTER;
DWORD & COUNT_REGISTER;
DWORD & ENTRYHI_REGISTER;
DWORD & COMPARE_REGISTER;
DWORD & STATUS_REGISTER;
DWORD & CAUSE_REGISTER;
DWORD & EPC_REGISTER;
DWORD & CONFIG_REGISTER;
DWORD & TAGLO_REGISTER;
DWORD & TAGHI_REGISTER;
DWORD & ERROREPC_REGISTER;
DWORD & FAKE_CAUSE_REGISTER;
uint32_t & INDEX_REGISTER;
uint32_t & RANDOM_REGISTER;
uint32_t & ENTRYLO0_REGISTER;
uint32_t & ENTRYLO1_REGISTER;
uint32_t & CONTEXT_REGISTER;
uint32_t & PAGE_MASK_REGISTER;
uint32_t & WIRED_REGISTER;
uint32_t & BAD_VADDR_REGISTER;
uint32_t & COUNT_REGISTER;
uint32_t & ENTRYHI_REGISTER;
uint32_t & COMPARE_REGISTER;
uint32_t & STATUS_REGISTER;
uint32_t & CAUSE_REGISTER;
uint32_t & EPC_REGISTER;
uint32_t & CONFIG_REGISTER;
uint32_t & TAGLO_REGISTER;
uint32_t & TAGHI_REGISTER;
uint32_t & ERROREPC_REGISTER;
uint32_t & FAKE_CAUSE_REGISTER;
private:
CP0registers(); // Disable default constructor
CP0registers(const CP0registers&); // Disable copy constructor
CP0registers& operator=(const CP0registers&); // Disable assignment
};
//CPO register flags
@ -114,40 +117,46 @@ enum
//Rdram Registers
class Rdram_InterfaceReg
{
Rdram_InterfaceReg();
protected:
Rdram_InterfaceReg (DWORD * _RdramInterface);
Rdram_InterfaceReg (uint32_t * _RdramInterface);
public:
DWORD & RDRAM_CONFIG_REG;
DWORD & RDRAM_DEVICE_TYPE_REG;
DWORD & RDRAM_DEVICE_ID_REG;
DWORD & RDRAM_DELAY_REG;
DWORD & RDRAM_MODE_REG;
DWORD & RDRAM_REF_INTERVAL_REG;
DWORD & RDRAM_REF_ROW_REG;
DWORD & RDRAM_RAS_INTERVAL_REG;
DWORD & RDRAM_MIN_INTERVAL_REG;
DWORD & RDRAM_ADDR_SELECT_REG;
DWORD & RDRAM_DEVICE_MANUF_REG;
uint32_t & RDRAM_CONFIG_REG;
uint32_t & RDRAM_DEVICE_TYPE_REG;
uint32_t & RDRAM_DEVICE_ID_REG;
uint32_t & RDRAM_DELAY_REG;
uint32_t & RDRAM_MODE_REG;
uint32_t & RDRAM_REF_INTERVAL_REG;
uint32_t & RDRAM_REF_ROW_REG;
uint32_t & RDRAM_RAS_INTERVAL_REG;
uint32_t & RDRAM_MIN_INTERVAL_REG;
uint32_t & RDRAM_ADDR_SELECT_REG;
uint32_t & RDRAM_DEVICE_MANUF_REG;
private:
Rdram_InterfaceReg(); // Disable default constructor
Rdram_InterfaceReg(const Rdram_InterfaceReg&); // Disable copy constructor
Rdram_InterfaceReg& operator=(const Rdram_InterfaceReg&); // Disable assignment
};
//Mips interface registers
class Mips_InterfaceReg
{
Mips_InterfaceReg ();
protected:
Mips_InterfaceReg (DWORD * _MipsInterface);
Mips_InterfaceReg (uint32_t * _MipsInterface);
public:
DWORD & MI_INIT_MODE_REG;
DWORD & MI_MODE_REG;
DWORD & MI_VERSION_REG;
DWORD & MI_NOOP_REG;
DWORD & MI_INTR_REG;
DWORD & MI_INTR_MASK_REG;
uint32_t & MI_INIT_MODE_REG;
uint32_t & MI_MODE_REG;
uint32_t & MI_VERSION_REG;
uint32_t & MI_NOOP_REG;
uint32_t & MI_INTR_REG;
uint32_t & MI_INTR_MASK_REG;
private:
Mips_InterfaceReg(); // Disable default constructor
Mips_InterfaceReg(const Mips_InterfaceReg&); // Disable copy constructor
Mips_InterfaceReg& operator=(const Mips_InterfaceReg&); // Disable assignment
};
//Mips interface flags
@ -198,54 +207,60 @@ enum
//Mips interface registers
class Video_InterfaceReg
{
Video_InterfaceReg();
protected:
Video_InterfaceReg (DWORD * _VideoInterface);
Video_InterfaceReg (uint32_t * _VideoInterface);
public:
DWORD & VI_STATUS_REG;
DWORD & VI_CONTROL_REG;
DWORD & VI_ORIGIN_REG;
DWORD & VI_DRAM_ADDR_REG;
DWORD & VI_WIDTH_REG;
DWORD & VI_H_WIDTH_REG;
DWORD & VI_INTR_REG;
DWORD & VI_V_INTR_REG;
DWORD & VI_CURRENT_REG;
DWORD & VI_V_CURRENT_LINE_REG;
DWORD & VI_BURST_REG;
DWORD & VI_TIMING_REG;
DWORD & VI_V_SYNC_REG;
DWORD & VI_H_SYNC_REG;
DWORD & VI_LEAP_REG;
DWORD & VI_H_SYNC_LEAP_REG;
DWORD & VI_H_START_REG;
DWORD & VI_H_VIDEO_REG;
DWORD & VI_V_START_REG;
DWORD & VI_V_VIDEO_REG;
DWORD & VI_V_BURST_REG;
DWORD & VI_X_SCALE_REG;
DWORD & VI_Y_SCALE_REG;
uint32_t & VI_STATUS_REG;
uint32_t & VI_CONTROL_REG;
uint32_t & VI_ORIGIN_REG;
uint32_t & VI_DRAM_ADDR_REG;
uint32_t & VI_WIDTH_REG;
uint32_t & VI_H_WIDTH_REG;
uint32_t & VI_INTR_REG;
uint32_t & VI_V_INTR_REG;
uint32_t & VI_CURRENT_REG;
uint32_t & VI_V_CURRENT_LINE_REG;
uint32_t & VI_BURST_REG;
uint32_t & VI_TIMING_REG;
uint32_t & VI_V_SYNC_REG;
uint32_t & VI_H_SYNC_REG;
uint32_t & VI_LEAP_REG;
uint32_t & VI_H_SYNC_LEAP_REG;
uint32_t & VI_H_START_REG;
uint32_t & VI_H_VIDEO_REG;
uint32_t & VI_V_START_REG;
uint32_t & VI_V_VIDEO_REG;
uint32_t & VI_V_BURST_REG;
uint32_t & VI_X_SCALE_REG;
uint32_t & VI_Y_SCALE_REG;
private:
Video_InterfaceReg(); // Disable default constructor
Video_InterfaceReg(const Video_InterfaceReg&); // Disable copy constructor
Video_InterfaceReg& operator=(const Video_InterfaceReg&); // Disable assignment
};
//Display Processor Control Registers
class DisplayControlReg
{
DisplayControlReg();
protected:
DisplayControlReg (DWORD * _DisplayProcessor);
DisplayControlReg (uint32_t * _DisplayProcessor);
public:
DWORD & DPC_START_REG;
DWORD & DPC_END_REG;
DWORD & DPC_CURRENT_REG;
DWORD & DPC_STATUS_REG;
DWORD & DPC_CLOCK_REG;
DWORD & DPC_BUFBUSY_REG;
DWORD & DPC_PIPEBUSY_REG;
DWORD & DPC_TMEM_REG;
uint32_t & DPC_START_REG;
uint32_t & DPC_END_REG;
uint32_t & DPC_CURRENT_REG;
uint32_t & DPC_STATUS_REG;
uint32_t & DPC_CLOCK_REG;
uint32_t & DPC_BUFBUSY_REG;
uint32_t & DPC_PIPEBUSY_REG;
uint32_t & DPC_TMEM_REG;
private:
DisplayControlReg(); // Disable default constructor
DisplayControlReg(const DisplayControlReg&); // Disable copy constructor
DisplayControlReg& operator=(const DisplayControlReg&); // Disable assignment
};
enum
@ -279,18 +294,21 @@ enum
*/
class AudioInterfaceReg
{
AudioInterfaceReg();
protected:
AudioInterfaceReg (DWORD * _AudioInterface);
AudioInterfaceReg (uint32_t * _AudioInterface);
public:
DWORD & AI_DRAM_ADDR_REG;
DWORD & AI_LEN_REG;
DWORD & AI_CONTROL_REG;
DWORD & AI_STATUS_REG;
DWORD & AI_DACRATE_REG;
DWORD & AI_BITRATE_REG;
uint32_t & AI_DRAM_ADDR_REG;
uint32_t & AI_LEN_REG;
uint32_t & AI_CONTROL_REG;
uint32_t & AI_STATUS_REG;
uint32_t & AI_DACRATE_REG;
uint32_t & AI_BITRATE_REG;
private:
AudioInterfaceReg(); // Disable default constructor
AudioInterfaceReg(const AudioInterfaceReg&); // Disable copy constructor
AudioInterfaceReg& operator=(const AudioInterfaceReg&); // Disable assignment
};
enum
@ -303,65 +321,76 @@ enum
class PeripheralInterfaceReg
{
PeripheralInterfaceReg();
protected:
PeripheralInterfaceReg (DWORD * PeripheralInterface);
PeripheralInterfaceReg (uint32_t * PeripheralInterface);
public:
DWORD & PI_DRAM_ADDR_REG;
DWORD & PI_CART_ADDR_REG;
DWORD & PI_RD_LEN_REG;
DWORD & PI_WR_LEN_REG;
DWORD & PI_STATUS_REG;
DWORD & PI_BSD_DOM1_LAT_REG;
DWORD & PI_DOMAIN1_REG;
DWORD & PI_BSD_DOM1_PWD_REG;
DWORD & PI_BSD_DOM1_PGS_REG;
DWORD & PI_BSD_DOM1_RLS_REG;
DWORD & PI_BSD_DOM2_LAT_REG;
DWORD & PI_DOMAIN2_REG;
DWORD & PI_BSD_DOM2_PWD_REG;
DWORD & PI_BSD_DOM2_PGS_REG;
DWORD & PI_BSD_DOM2_RLS_REG;
uint32_t & PI_DRAM_ADDR_REG;
uint32_t & PI_CART_ADDR_REG;
uint32_t & PI_RD_LEN_REG;
uint32_t & PI_WR_LEN_REG;
uint32_t & PI_STATUS_REG;
uint32_t & PI_BSD_DOM1_LAT_REG;
uint32_t & PI_DOMAIN1_REG;
uint32_t & PI_BSD_DOM1_PWD_REG;
uint32_t & PI_BSD_DOM1_PGS_REG;
uint32_t & PI_BSD_DOM1_RLS_REG;
uint32_t & PI_BSD_DOM2_LAT_REG;
uint32_t & PI_DOMAIN2_REG;
uint32_t & PI_BSD_DOM2_PWD_REG;
uint32_t & PI_BSD_DOM2_PGS_REG;
uint32_t & PI_BSD_DOM2_RLS_REG;
private:
PeripheralInterfaceReg(); // Disable default constructor
PeripheralInterfaceReg(const PeripheralInterfaceReg&); // Disable copy constructor
PeripheralInterfaceReg& operator=(const PeripheralInterfaceReg&); // Disable assignment
};
class RDRAMInt_InterfaceReg
{
RDRAMInt_InterfaceReg();
protected:
RDRAMInt_InterfaceReg (DWORD * RdramInterface);
RDRAMInt_InterfaceReg (uint32_t * RdramInterface);
public:
DWORD & RI_MODE_REG;
DWORD & RI_CONFIG_REG;
DWORD & RI_CURRENT_LOAD_REG;
DWORD & RI_SELECT_REG;
DWORD & RI_COUNT_REG;
DWORD & RI_REFRESH_REG;
DWORD & RI_LATENCY_REG;
DWORD & RI_RERROR_REG;
DWORD & RI_WERROR_REG;
uint32_t & RI_MODE_REG;
uint32_t & RI_CONFIG_REG;
uint32_t & RI_CURRENT_LOAD_REG;
uint32_t & RI_SELECT_REG;
uint32_t & RI_COUNT_REG;
uint32_t & RI_REFRESH_REG;
uint32_t & RI_LATENCY_REG;
uint32_t & RI_RERROR_REG;
uint32_t & RI_WERROR_REG;
private:
RDRAMInt_InterfaceReg(); // Disable default constructor
RDRAMInt_InterfaceReg(const RDRAMInt_InterfaceReg&); // Disable copy constructor
RDRAMInt_InterfaceReg& operator=(const RDRAMInt_InterfaceReg&); // Disable assignment
};
//Signal Processor Interface;
class SigProcessor_InterfaceReg
{
protected:
SigProcessor_InterfaceReg (DWORD * _SignalProcessorInterface);
SigProcessor_InterfaceReg (uint32_t * _SignalProcessorInterface);
public:
DWORD & SP_MEM_ADDR_REG;
DWORD & SP_DRAM_ADDR_REG;
DWORD & SP_RD_LEN_REG;
DWORD & SP_WR_LEN_REG;
DWORD & SP_STATUS_REG;
DWORD & SP_DMA_FULL_REG;
DWORD & SP_DMA_BUSY_REG;
DWORD & SP_SEMAPHORE_REG;
DWORD & SP_PC_REG;
DWORD & SP_IBIST_REG;
uint32_t & SP_MEM_ADDR_REG;
uint32_t & SP_DRAM_ADDR_REG;
uint32_t & SP_RD_LEN_REG;
uint32_t & SP_WR_LEN_REG;
uint32_t & SP_STATUS_REG;
uint32_t & SP_DMA_FULL_REG;
uint32_t & SP_DMA_BUSY_REG;
uint32_t & SP_SEMAPHORE_REG;
uint32_t & SP_PC_REG;
uint32_t & SP_IBIST_REG;
private:
SigProcessor_InterfaceReg(); // Disable default constructor
SigProcessor_InterfaceReg(const SigProcessor_InterfaceReg&); // Disable copy constructor
SigProcessor_InterfaceReg& operator=(const SigProcessor_InterfaceReg&); // Disable assignment
};
//Signal Processor interface flags
@ -421,19 +450,21 @@ enum
PI_CLR_INTR = 0x02,
};
class Serial_InterfaceReg
{
Serial_InterfaceReg();
protected:
Serial_InterfaceReg (DWORD * SerialInterface);
Serial_InterfaceReg (uint32_t * SerialInterface);
public:
DWORD & SI_DRAM_ADDR_REG;
DWORD & SI_PIF_ADDR_RD64B_REG;
DWORD & SI_PIF_ADDR_WR64B_REG;
DWORD & SI_STATUS_REG;
uint32_t & SI_DRAM_ADDR_REG;
uint32_t & SI_PIF_ADDR_RD64B_REG;
uint32_t & SI_PIF_ADDR_WR64B_REG;
uint32_t & SI_STATUS_REG;
private:
Serial_InterfaceReg(); // Disable default constructor
Serial_InterfaceReg(const Serial_InterfaceReg&); // Disable copy constructor
Serial_InterfaceReg& operator=(const Serial_InterfaceReg&); // Disable assignment
};
//Serial Interface flags
@ -445,16 +476,16 @@ enum
SI_STATUS_INTERRUPT = 0x1000,
};
enum ROUNDING_MODE
{
ROUND_NEAR = _RC_NEAR,
ROUND_DOWN = _RC_DOWN,
ROUND_UP = _RC_UP,
ROUND_CHOP = _RC_CHOP,
ROUND_NEAR = 0x00000000, // _RC_NEAR
ROUND_DOWN = 0x00000100, // _RC_DOWN
ROUND_UP = 0x00000200, // _RC_UP
ROUND_CHOP = 0x00000300, // _RC_CHOP
};
class CRegName {
class CRegName
{
public:
static const char *GPR[32];
static const char *GPR_Hi[32];
@ -467,16 +498,16 @@ public:
class CSystemRegisters
{
protected:
static DWORD * _PROGRAM_COUNTER;
static uint32_t * _PROGRAM_COUNTER;
static MIPS_DWORD * _GPR;
static MIPS_DWORD * _FPR;
static DWORD * _CP0;
static uint32_t * _CP0;
static MIPS_DWORD * _RegHI;
static MIPS_DWORD * _RegLO;
static float ** _FPR_S;
static double ** _FPR_D;
static DWORD * _FPCR;
static DWORD * _LLBit;
static uint32_t * _FPCR;
static uint32_t * _LLBit;
static ROUNDING_MODE * _RoundingModel;
};
@ -502,41 +533,40 @@ public:
CRegisters(CN64System * System, CSystemEvents * SystemEvents);
//General Registers
DWORD m_PROGRAM_COUNTER;
uint32_t m_PROGRAM_COUNTER;
MIPS_DWORD m_GPR[32];
DWORD m_CP0[33];
uint32_t m_CP0[33];
MIPS_DWORD m_HI;
MIPS_DWORD m_LO;
DWORD m_LLBit;
uint32_t m_LLBit;
//Floating point registers/information
DWORD m_FPCR[32];
uint32_t m_FPCR[32];
ROUNDING_MODE m_RoundingModel;
MIPS_DWORD m_FPR[32];
float * m_FPR_S[32];
double * m_FPR_D[32];
//Memory Mapped N64 registers
DWORD m_RDRAM_Registers[10];
DWORD m_SigProcessor_Interface[10];
DWORD m_Display_ControlReg[10];
DWORD m_Mips_Interface[4];
DWORD m_Video_Interface[14];
DWORD m_Audio_Interface[6];
DWORD m_Peripheral_Interface[13];
DWORD m_RDRAM_Interface[8];
DWORD m_SerialInterface[4];
DWORD m_AudioIntrReg;
DWORD m_GfxIntrReg;
DWORD m_RspIntrReg;
uint32_t m_RDRAM_Registers[10];
uint32_t m_SigProcessor_Interface[10];
uint32_t m_Display_ControlReg[10];
uint32_t m_Mips_Interface[4];
uint32_t m_Video_Interface[14];
uint32_t m_Audio_Interface[6];
uint32_t m_Peripheral_Interface[13];
uint32_t m_RDRAM_Interface[8];
uint32_t m_SerialInterface[4];
uint32_t m_AudioIntrReg;
uint32_t m_GfxIntrReg;
uint32_t m_RspIntrReg;
void CheckInterrupts ();
void DoAddressError ( bool DelaySlot, DWORD BadVaddr, bool FromRead );
void DoAddressError ( bool DelaySlot, uint32_t BadVaddr, bool FromRead );
void DoBreakException ( bool DelaySlot );
void DoCopUnusableException ( bool DelaySlot, int Coprocessor );
void DoCopUnusableException ( bool DelaySlot, int32_t Coprocessor );
bool DoIntrException ( bool DelaySlot );
void DoTLBReadMiss ( bool DelaySlot, DWORD BadVaddr );
void DoTLBReadMiss ( bool DelaySlot, uint32_t BadVaddr );
void DoSysCallException ( bool DelaySlot);
void FixFpuLocations ();
void Reset ();

2
Source/Project64/N64 System/Recompiler/Recompiler Class.cpp
View File

@ -93,7 +93,7 @@ void CRecompiler::Run()
void CRecompiler::RecompilerMain_VirtualTable()
{
bool & Done = m_EndEmulation;
DWORD & PC = PROGRAM_COUNTER;
uint32_t & PC = PROGRAM_COUNTER;
while(!Done)
{

2
Source/Project64/N64 System/Recompiler/Recompiler Class.h
View File

@ -70,5 +70,5 @@ private:
DWORD m_MemoryStack;
//Quick access to registers
DWORD & PROGRAM_COUNTER;
uint32_t & PROGRAM_COUNTER;
};