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[Project64] Get Register class to use standard type

This commit is contained in:
zilmar 2015-11-09 07:45:41 +11:00
parent 21b80c240f
commit 1a09c2baea
5 changed files with 852 additions and 834 deletions
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4
Source/Project64/N64 System/Interpreter/Interpreter CPU.cpp
View File

@ -264,7 +264,7 @@ void CInterpreterCPU::InPermLoop()
void CInterpreterCPU::ExecuteCPU() void CInterpreterCPU::ExecuteCPU()
{ {
bool & Done = g_System->m_EndEmulation; bool & Done = g_System->m_EndEmulation;
DWORD & PROGRAM_COUNTER = *_PROGRAM_COUNTER; uint32_t & PROGRAM_COUNTER = *_PROGRAM_COUNTER;
OPCODE & Opcode = R4300iOp::m_Opcode; OPCODE & Opcode = R4300iOp::m_Opcode;
DWORD & JumpToLocation = R4300iOp::m_JumpToLocation; DWORD & JumpToLocation = R4300iOp::m_JumpToLocation;
bool & TestTimer = R4300iOp::m_TestTimer; bool & TestTimer = R4300iOp::m_TestTimer;
@ -350,7 +350,7 @@ void CInterpreterCPU::ExecuteCPU()
void CInterpreterCPU::ExecuteOps(int Cycles) void CInterpreterCPU::ExecuteOps(int Cycles)
{ {
bool & Done = g_System->m_EndEmulation; bool & Done = g_System->m_EndEmulation;
DWORD & PROGRAM_COUNTER = *_PROGRAM_COUNTER; uint32_t & PROGRAM_COUNTER = *_PROGRAM_COUNTER;
OPCODE & Opcode = R4300iOp::m_Opcode; OPCODE & Opcode = R4300iOp::m_Opcode;
DWORD & JumpToLocation = R4300iOp::m_JumpToLocation; DWORD & JumpToLocation = R4300iOp::m_JumpToLocation;
bool & TestTimer = R4300iOp::m_TestTimer; bool & TestTimer = R4300iOp::m_TestTimer;

870
Source/Project64/N64 System/Mips/Register Class.cpp
View File

@ -11,543 +11,531 @@
#include "stdafx.h" #include "stdafx.h"
const char * CRegName::GPR[32] = {"r0","at","v0","v1","a0","a1","a2","a3", const char * CRegName::GPR[32] = {"r0","at","v0","v1","a0","a1","a2","a3",
"t0","t1","t2","t3","t4","t5","t6","t7", "t0","t1","t2","t3","t4","t5","t6","t7",
"s0","s1","s2","s3","s4","s5","s6","s7", "s0","s1","s2","s3","s4","s5","s6","s7",
"t8","t9","k0","k1","gp","sp","s8","ra"}; "t8","t9","k0","k1","gp","sp","s8","ra"};
const char *CRegName::GPR_Hi[32] = {"r0.HI","at.HI","v0.HI","v1.HI","a0.HI","a1.HI", const char *CRegName::GPR_Hi[32] = {"r0.HI","at.HI","v0.HI","v1.HI","a0.HI","a1.HI",
"a2.HI","a3.HI","t0.HI","t1.HI","t2.HI","t3.HI", "a2.HI","a3.HI","t0.HI","t1.HI","t2.HI","t3.HI",
"t4.HI","t5.HI","t6.HI","t7.HI","s0.HI","s1.HI", "t4.HI","t5.HI","t6.HI","t7.HI","s0.HI","s1.HI",
"s2.HI","s3.HI","s4.HI","s5.HI","s6.HI","s7.HI", "s2.HI","s3.HI","s4.HI","s5.HI","s6.HI","s7.HI",
"t8.HI","t9.HI","k0.HI","k1.HI","gp.HI","sp.HI", "t8.HI","t9.HI","k0.HI","k1.HI","gp.HI","sp.HI",
"s8.HI","ra.HI"}; "s8.HI","ra.HI"};
const char *CRegName::GPR_Lo[32] = {"r0.LO","at.LO","v0.LO","v1.LO","a0.LO","a1.LO", const char *CRegName::GPR_Lo[32] = {"r0.LO","at.LO","v0.LO","v1.LO","a0.LO","a1.LO",
"a2.LO","a3.LO","t0.LO","t1.LO","t2.LO","t3.LO", "a2.LO","a3.LO","t0.LO","t1.LO","t2.LO","t3.LO",
"t4.LO","t5.LO","t6.LO","t7.LO","s0.LO","s1.LO", "t4.LO","t5.LO","t6.LO","t7.LO","s0.LO","s1.LO",
"s2.LO","s3.LO","s4.LO","s5.LO","s6.LO","s7.LO", "s2.LO","s3.LO","s4.LO","s5.LO","s6.LO","s7.LO",
"t8.LO","t9.LO","k0.LO","k1.LO","gp.LO","sp.LO", "t8.LO","t9.LO","k0.LO","k1.LO","gp.LO","sp.LO",
"s8.LO","ra.LO"}; "s8.LO","ra.LO"};
const char * CRegName::Cop0[32] = {"Index","Random","EntryLo0","EntryLo1","Context","PageMask","Wired","", const char * CRegName::Cop0[32] = {"Index","Random","EntryLo0","EntryLo1","Context","PageMask","Wired","",
"BadVAddr","Count","EntryHi","Compare","Status","Cause","EPC","PRId", "BadVAddr","Count","EntryHi","Compare","Status","Cause","EPC","PRId",
"Config","LLAddr","WatchLo","WatchHi","XContext","","","", "Config","LLAddr","WatchLo","WatchHi","XContext","","","",
"","","ECC","CacheErr","TagLo","TagHi","ErrEPC",""}; "","","ECC","CacheErr","TagLo","TagHi","ErrEPC",""};
const char * CRegName::FPR[32] = {"f0","f1","f2","f3","f4","f5","f6","f7", const char * CRegName::FPR[32] = {"f0","f1","f2","f3","f4","f5","f6","f7",
"f8","f9","f10","f11","f12","f13","f14","f15", "f8","f9","f10","f11","f12","f13","f14","f15",
"f16","f17","f18","f19","f20","f21","f22","f23", "f16","f17","f18","f19","f20","f21","f22","f23",
"f24","f25","f26","f27","f28","f29","f30","f31"}; "f24","f25","f26","f27","f28","f29","f30","f31"};
const char * CRegName::FPR_Ctrl[32] = {"Revision","Unknown","Unknown","Unknown","Unknown", const char * CRegName::FPR_Ctrl[32] = {"Revision","Unknown","Unknown","Unknown","Unknown",
"Unknown","Unknown","Unknown","Unknown","Unknown","Unknown", "Unknown","Unknown","Unknown","Unknown","Unknown","Unknown",
"Unknown","Unknown","Unknown","Unknown","Unknown","Unknown", "Unknown","Unknown","Unknown","Unknown","Unknown","Unknown",
"Unknown","Unknown","Unknown","Unknown","Unknown","Unknown", "Unknown","Unknown","Unknown","Unknown","Unknown","Unknown",
"Unknown","Unknown","Unknown","Unknown","Unknown","Unknown", "Unknown","Unknown","Unknown","Unknown","Unknown","Unknown",
"Unknown","Unknown","FCSR"}; "Unknown","Unknown","FCSR"};
DWORD * CSystemRegisters::_PROGRAM_COUNTER = NULL; uint32_t * CSystemRegisters::_PROGRAM_COUNTER = NULL;
MIPS_DWORD * CSystemRegisters::_GPR = NULL; MIPS_DWORD * CSystemRegisters::_GPR = NULL;
MIPS_DWORD * CSystemRegisters::_FPR = NULL; MIPS_DWORD * CSystemRegisters::_FPR = NULL;
DWORD * CSystemRegisters::_CP0 = NULL; uint32_t * CSystemRegisters::_CP0 = NULL;
MIPS_DWORD * CSystemRegisters::_RegHI = NULL; MIPS_DWORD * CSystemRegisters::_RegHI = NULL;
MIPS_DWORD * CSystemRegisters::_RegLO = NULL; MIPS_DWORD * CSystemRegisters::_RegLO = NULL;
float ** CSystemRegisters::_FPR_S; float ** CSystemRegisters::_FPR_S;
double ** CSystemRegisters::_FPR_D; double ** CSystemRegisters::_FPR_D;
DWORD * CSystemRegisters::_FPCR = NULL; uint32_t * CSystemRegisters::_FPCR = NULL;
DWORD * CSystemRegisters::_LLBit = NULL; uint32_t * CSystemRegisters::_LLBit = NULL;
ROUNDING_MODE * CSystemRegisters::_RoundingModel = NULL; ROUNDING_MODE * CSystemRegisters::_RoundingModel = NULL;
CP0registers::CP0registers(uint32_t * _CP0) :
CP0registers::CP0registers(DWORD * _CP0) : INDEX_REGISTER(_CP0[0]),
INDEX_REGISTER(_CP0[0]), RANDOM_REGISTER(_CP0[1]),
RANDOM_REGISTER(_CP0[1]), ENTRYLO0_REGISTER(_CP0[2]),
ENTRYLO0_REGISTER(_CP0[2]), ENTRYLO1_REGISTER(_CP0[3]),
ENTRYLO1_REGISTER(_CP0[3]), CONTEXT_REGISTER(_CP0[4]),
CONTEXT_REGISTER(_CP0[4]), PAGE_MASK_REGISTER(_CP0[5]),
PAGE_MASK_REGISTER(_CP0[5]), WIRED_REGISTER(_CP0[6]),
WIRED_REGISTER(_CP0[6]), BAD_VADDR_REGISTER(_CP0[8]),
BAD_VADDR_REGISTER(_CP0[8]), COUNT_REGISTER(_CP0[9]),
COUNT_REGISTER(_CP0[9]), ENTRYHI_REGISTER(_CP0[10]),
ENTRYHI_REGISTER(_CP0[10]), COMPARE_REGISTER(_CP0[11]),
COMPARE_REGISTER(_CP0[11]), STATUS_REGISTER(_CP0[12]),
STATUS_REGISTER(_CP0[12]), CAUSE_REGISTER(_CP0[13]),
CAUSE_REGISTER(_CP0[13]), EPC_REGISTER(_CP0[14]),
EPC_REGISTER(_CP0[14]), CONFIG_REGISTER(_CP0[16]),
CONFIG_REGISTER(_CP0[16]), TAGLO_REGISTER(_CP0[28]),
TAGLO_REGISTER(_CP0[28]), TAGHI_REGISTER(_CP0[29]),
TAGHI_REGISTER(_CP0[29]), ERROREPC_REGISTER(_CP0[30]),
ERROREPC_REGISTER(_CP0[30]), FAKE_CAUSE_REGISTER(_CP0[32])
FAKE_CAUSE_REGISTER(_CP0[32])
{ {
} }
Rdram_InterfaceReg::Rdram_InterfaceReg(DWORD * _RdramInterface) : Rdram_InterfaceReg::Rdram_InterfaceReg(uint32_t * _RdramInterface) :
RDRAM_CONFIG_REG(_RdramInterface[0]), RDRAM_CONFIG_REG(_RdramInterface[0]),
RDRAM_DEVICE_TYPE_REG(_RdramInterface[0]), RDRAM_DEVICE_TYPE_REG(_RdramInterface[0]),
RDRAM_DEVICE_ID_REG(_RdramInterface[1]), RDRAM_DEVICE_ID_REG(_RdramInterface[1]),
RDRAM_DELAY_REG(_RdramInterface[2]), RDRAM_DELAY_REG(_RdramInterface[2]),
RDRAM_MODE_REG(_RdramInterface[3]), RDRAM_MODE_REG(_RdramInterface[3]),
RDRAM_REF_INTERVAL_REG(_RdramInterface[4]), RDRAM_REF_INTERVAL_REG(_RdramInterface[4]),
RDRAM_REF_ROW_REG(_RdramInterface[5]), RDRAM_REF_ROW_REG(_RdramInterface[5]),
RDRAM_RAS_INTERVAL_REG(_RdramInterface[6]), RDRAM_RAS_INTERVAL_REG(_RdramInterface[6]),
RDRAM_MIN_INTERVAL_REG(_RdramInterface[7]), RDRAM_MIN_INTERVAL_REG(_RdramInterface[7]),
RDRAM_ADDR_SELECT_REG(_RdramInterface[8]), RDRAM_ADDR_SELECT_REG(_RdramInterface[8]),
RDRAM_DEVICE_MANUF_REG(_RdramInterface[9]) RDRAM_DEVICE_MANUF_REG(_RdramInterface[9])
{ {
} }
Mips_InterfaceReg::Mips_InterfaceReg(DWORD * _MipsInterface) : Mips_InterfaceReg::Mips_InterfaceReg(uint32_t * _MipsInterface) :
MI_INIT_MODE_REG(_MipsInterface[0]), MI_INIT_MODE_REG(_MipsInterface[0]),
MI_MODE_REG(_MipsInterface[0]), MI_MODE_REG(_MipsInterface[0]),
MI_VERSION_REG(_MipsInterface[1]), MI_VERSION_REG(_MipsInterface[1]),
MI_NOOP_REG(_MipsInterface[1]), MI_NOOP_REG(_MipsInterface[1]),
MI_INTR_REG(_MipsInterface[2]), MI_INTR_REG(_MipsInterface[2]),
MI_INTR_MASK_REG(_MipsInterface[3]) MI_INTR_MASK_REG(_MipsInterface[3])
{ {
} }
Video_InterfaceReg::Video_InterfaceReg(DWORD * _VideoInterface) : Video_InterfaceReg::Video_InterfaceReg(uint32_t * _VideoInterface) :
VI_STATUS_REG(_VideoInterface[0]), VI_STATUS_REG(_VideoInterface[0]),
VI_CONTROL_REG(_VideoInterface[0]), VI_CONTROL_REG(_VideoInterface[0]),
VI_ORIGIN_REG(_VideoInterface[1]), VI_ORIGIN_REG(_VideoInterface[1]),
VI_DRAM_ADDR_REG(_VideoInterface[1]), VI_DRAM_ADDR_REG(_VideoInterface[1]),
VI_WIDTH_REG(_VideoInterface[2]), VI_WIDTH_REG(_VideoInterface[2]),
VI_H_WIDTH_REG(_VideoInterface[2]), VI_H_WIDTH_REG(_VideoInterface[2]),
VI_INTR_REG(_VideoInterface[3]), VI_INTR_REG(_VideoInterface[3]),
VI_V_INTR_REG(_VideoInterface[3]), VI_V_INTR_REG(_VideoInterface[3]),
VI_CURRENT_REG(_VideoInterface[4]), VI_CURRENT_REG(_VideoInterface[4]),
VI_V_CURRENT_LINE_REG(_VideoInterface[4]), VI_V_CURRENT_LINE_REG(_VideoInterface[4]),
VI_BURST_REG(_VideoInterface[5]), VI_BURST_REG(_VideoInterface[5]),
VI_TIMING_REG(_VideoInterface[5]), VI_TIMING_REG(_VideoInterface[5]),
VI_V_SYNC_REG(_VideoInterface[6]), VI_V_SYNC_REG(_VideoInterface[6]),
VI_H_SYNC_REG(_VideoInterface[7]), VI_H_SYNC_REG(_VideoInterface[7]),
VI_LEAP_REG(_VideoInterface[8]), VI_LEAP_REG(_VideoInterface[8]),
VI_H_SYNC_LEAP_REG(_VideoInterface[8]), VI_H_SYNC_LEAP_REG(_VideoInterface[8]),
VI_H_START_REG(_VideoInterface[9]), VI_H_START_REG(_VideoInterface[9]),
VI_H_VIDEO_REG(_VideoInterface[9]), VI_H_VIDEO_REG(_VideoInterface[9]),
VI_V_START_REG(_VideoInterface[10]), VI_V_START_REG(_VideoInterface[10]),
VI_V_VIDEO_REG(_VideoInterface[10]), VI_V_VIDEO_REG(_VideoInterface[10]),
VI_V_BURST_REG(_VideoInterface[11]), VI_V_BURST_REG(_VideoInterface[11]),
VI_X_SCALE_REG(_VideoInterface[12]), VI_X_SCALE_REG(_VideoInterface[12]),
VI_Y_SCALE_REG(_VideoInterface[13]) VI_Y_SCALE_REG(_VideoInterface[13])
{ {
} }
AudioInterfaceReg::AudioInterfaceReg(DWORD * _AudioInterface) : AudioInterfaceReg::AudioInterfaceReg(uint32_t * _AudioInterface) :
AI_DRAM_ADDR_REG(_AudioInterface[0]), AI_DRAM_ADDR_REG(_AudioInterface[0]),
AI_LEN_REG(_AudioInterface[1]), AI_LEN_REG(_AudioInterface[1]),
AI_CONTROL_REG(_AudioInterface[2]), AI_CONTROL_REG(_AudioInterface[2]),
AI_STATUS_REG(_AudioInterface[3]), AI_STATUS_REG(_AudioInterface[3]),
AI_DACRATE_REG(_AudioInterface[4]), AI_DACRATE_REG(_AudioInterface[4]),
AI_BITRATE_REG(_AudioInterface[5]) AI_BITRATE_REG(_AudioInterface[5])
{ {
}
PeripheralInterfaceReg::PeripheralInterfaceReg(DWORD * PeripheralInterface) :
PI_DRAM_ADDR_REG(PeripheralInterface[0]),
PI_CART_ADDR_REG(PeripheralInterface[1]),
PI_RD_LEN_REG(PeripheralInterface[2]),
PI_WR_LEN_REG(PeripheralInterface[3]),
PI_STATUS_REG(PeripheralInterface[4]),
PI_BSD_DOM1_LAT_REG(PeripheralInterface[5]),
PI_DOMAIN1_REG(PeripheralInterface[5]),
PI_BSD_DOM1_PWD_REG(PeripheralInterface[6]),
PI_BSD_DOM1_PGS_REG(PeripheralInterface[7]),
PI_BSD_DOM1_RLS_REG(PeripheralInterface[8]),
PI_BSD_DOM2_LAT_REG(PeripheralInterface[9]),
PI_DOMAIN2_REG(PeripheralInterface[9]),
PI_BSD_DOM2_PWD_REG(PeripheralInterface[10]),
PI_BSD_DOM2_PGS_REG(PeripheralInterface[11]),
PI_BSD_DOM2_RLS_REG(PeripheralInterface[12])
{
} }
RDRAMInt_InterfaceReg::RDRAMInt_InterfaceReg(DWORD * RdramInterface) : PeripheralInterfaceReg::PeripheralInterfaceReg(uint32_t * PeripheralInterface) :
RI_MODE_REG(RdramInterface[0]), PI_DRAM_ADDR_REG(PeripheralInterface[0]),
RI_CONFIG_REG(RdramInterface[1]), PI_CART_ADDR_REG(PeripheralInterface[1]),
RI_CURRENT_LOAD_REG(RdramInterface[2]), PI_RD_LEN_REG(PeripheralInterface[2]),
RI_SELECT_REG(RdramInterface[3]), PI_WR_LEN_REG(PeripheralInterface[3]),
RI_COUNT_REG(RdramInterface[4]), PI_STATUS_REG(PeripheralInterface[4]),
RI_REFRESH_REG(RdramInterface[4]), PI_BSD_DOM1_LAT_REG(PeripheralInterface[5]),
RI_LATENCY_REG(RdramInterface[5]), PI_DOMAIN1_REG(PeripheralInterface[5]),
RI_RERROR_REG(RdramInterface[6]), PI_BSD_DOM1_PWD_REG(PeripheralInterface[6]),
RI_WERROR_REG(RdramInterface[7]) PI_BSD_DOM1_PGS_REG(PeripheralInterface[7]),
PI_BSD_DOM1_RLS_REG(PeripheralInterface[8]),
PI_BSD_DOM2_LAT_REG(PeripheralInterface[9]),
PI_DOMAIN2_REG(PeripheralInterface[9]),
PI_BSD_DOM2_PWD_REG(PeripheralInterface[10]),
PI_BSD_DOM2_PGS_REG(PeripheralInterface[11]),
PI_BSD_DOM2_RLS_REG(PeripheralInterface[12])
{ {
} }
DisplayControlReg::DisplayControlReg(DWORD * _DisplayProcessor) : RDRAMInt_InterfaceReg::RDRAMInt_InterfaceReg(uint32_t * RdramInterface) :
DPC_START_REG(_DisplayProcessor[0]), RI_MODE_REG(RdramInterface[0]),
DPC_END_REG(_DisplayProcessor[1]), RI_CONFIG_REG(RdramInterface[1]),
DPC_CURRENT_REG(_DisplayProcessor[2]), RI_CURRENT_LOAD_REG(RdramInterface[2]),
DPC_STATUS_REG(_DisplayProcessor[3]), RI_SELECT_REG(RdramInterface[3]),
DPC_CLOCK_REG(_DisplayProcessor[4]), RI_COUNT_REG(RdramInterface[4]),
DPC_BUFBUSY_REG(_DisplayProcessor[5]), RI_REFRESH_REG(RdramInterface[4]),
DPC_PIPEBUSY_REG(_DisplayProcessor[6]), RI_LATENCY_REG(RdramInterface[5]),
DPC_TMEM_REG(_DisplayProcessor[7]) RI_RERROR_REG(RdramInterface[6]),
RI_WERROR_REG(RdramInterface[7])
{ {
} }
SigProcessor_InterfaceReg::SigProcessor_InterfaceReg(DWORD * _SignalProcessorInterface) : DisplayControlReg::DisplayControlReg(uint32_t * _DisplayProcessor) :
SP_MEM_ADDR_REG(_SignalProcessorInterface[0]), DPC_START_REG(_DisplayProcessor[0]),
SP_DRAM_ADDR_REG(_SignalProcessorInterface[1]), DPC_END_REG(_DisplayProcessor[1]),
SP_RD_LEN_REG(_SignalProcessorInterface[2]), DPC_CURRENT_REG(_DisplayProcessor[2]),
SP_WR_LEN_REG(_SignalProcessorInterface[3]), DPC_STATUS_REG(_DisplayProcessor[3]),
SP_STATUS_REG(_SignalProcessorInterface[4]), DPC_CLOCK_REG(_DisplayProcessor[4]),
SP_DMA_FULL_REG(_SignalProcessorInterface[5]), DPC_BUFBUSY_REG(_DisplayProcessor[5]),
SP_DMA_BUSY_REG(_SignalProcessorInterface[6]), DPC_PIPEBUSY_REG(_DisplayProcessor[6]),
SP_SEMAPHORE_REG(_SignalProcessorInterface[7]), DPC_TMEM_REG(_DisplayProcessor[7])
SP_PC_REG(_SignalProcessorInterface[8]),
SP_IBIST_REG(_SignalProcessorInterface[9])
{ {
} }
Serial_InterfaceReg::Serial_InterfaceReg(DWORD * SerialInterface) : SigProcessor_InterfaceReg::SigProcessor_InterfaceReg(uint32_t * _SignalProcessorInterface) :
SI_DRAM_ADDR_REG(SerialInterface[0]), SP_MEM_ADDR_REG(_SignalProcessorInterface[0]),
SI_PIF_ADDR_RD64B_REG(SerialInterface[1]), SP_DRAM_ADDR_REG(_SignalProcessorInterface[1]),
SI_PIF_ADDR_WR64B_REG(SerialInterface[2]), SP_RD_LEN_REG(_SignalProcessorInterface[2]),
SI_STATUS_REG(SerialInterface[3]) SP_WR_LEN_REG(_SignalProcessorInterface[3]),
SP_STATUS_REG(_SignalProcessorInterface[4]),
SP_DMA_FULL_REG(_SignalProcessorInterface[5]),
SP_DMA_BUSY_REG(_SignalProcessorInterface[6]),
SP_SEMAPHORE_REG(_SignalProcessorInterface[7]),
SP_PC_REG(_SignalProcessorInterface[8]),
SP_IBIST_REG(_SignalProcessorInterface[9])
{
}
Serial_InterfaceReg::Serial_InterfaceReg(uint32_t * SerialInterface) :
SI_DRAM_ADDR_REG(SerialInterface[0]),
SI_PIF_ADDR_RD64B_REG(SerialInterface[1]),
SI_PIF_ADDR_WR64B_REG(SerialInterface[2]),
SI_STATUS_REG(SerialInterface[3])
{ {
} }
CRegisters::CRegisters(CN64System * System, CSystemEvents * SystemEvents) : CRegisters::CRegisters(CN64System * System, CSystemEvents * SystemEvents) :
CP0registers(m_CP0), CP0registers(m_CP0),
Rdram_InterfaceReg(m_RDRAM_Registers), Rdram_InterfaceReg(m_RDRAM_Registers),
Mips_InterfaceReg(m_Mips_Interface), Mips_InterfaceReg(m_Mips_Interface),
Video_InterfaceReg(m_Video_Interface), Video_InterfaceReg(m_Video_Interface),
AudioInterfaceReg(m_Audio_Interface), AudioInterfaceReg(m_Audio_Interface),
PeripheralInterfaceReg(m_Peripheral_Interface), PeripheralInterfaceReg(m_Peripheral_Interface),
RDRAMInt_InterfaceReg(m_RDRAM_Interface), RDRAMInt_InterfaceReg(m_RDRAM_Interface),
SigProcessor_InterfaceReg(m_SigProcessor_Interface), SigProcessor_InterfaceReg(m_SigProcessor_Interface),
DisplayControlReg(m_Display_ControlReg), DisplayControlReg(m_Display_ControlReg),
Serial_InterfaceReg(m_SerialInterface), Serial_InterfaceReg(m_SerialInterface),
m_System(System), m_System(System),
m_SystemEvents(SystemEvents) m_SystemEvents(SystemEvents)
{ {
Reset(); Reset();
} }
void CRegisters::Reset() void CRegisters::Reset()
{ {
m_FirstInterupt = true; m_FirstInterupt = true;
memset(m_GPR,0,sizeof(m_GPR)); memset(m_GPR,0,sizeof(m_GPR));
memset(m_CP0,0,sizeof(m_CP0)); memset(m_CP0,0,sizeof(m_CP0));
memset(m_FPR,0,sizeof(m_FPR)); memset(m_FPR,0,sizeof(m_FPR));
memset(m_FPCR,0,sizeof(m_FPCR)); memset(m_FPCR,0,sizeof(m_FPCR));
m_HI.DW = 0; m_HI.DW = 0;
m_LO.DW = 0; m_LO.DW = 0;
m_RoundingModel = ROUND_NEAR; m_RoundingModel = ROUND_NEAR;
m_LLBit = 0;
//Reset System Registers m_LLBit = 0;
memset(m_RDRAM_Interface,0,sizeof(m_RDRAM_Interface));
memset(m_RDRAM_Registers,0,sizeof(m_RDRAM_Registers));
memset(m_Mips_Interface,0,sizeof(m_Mips_Interface));
memset(m_Video_Interface,0,sizeof(m_Video_Interface));
memset(m_Display_ControlReg,0,sizeof(m_Display_ControlReg));
memset(m_Audio_Interface,0,sizeof(m_Audio_Interface));
memset(m_SigProcessor_Interface,0,sizeof(m_SigProcessor_Interface));
memset(m_Peripheral_Interface,0,sizeof(m_Peripheral_Interface));
memset(m_SerialInterface,0,sizeof(m_SerialInterface));
m_AudioIntrReg = 0; //Reset System Registers
m_GfxIntrReg = 0; memset(m_RDRAM_Interface,0,sizeof(m_RDRAM_Interface));
m_RspIntrReg = 0; memset(m_RDRAM_Registers,0,sizeof(m_RDRAM_Registers));
memset(m_Mips_Interface,0,sizeof(m_Mips_Interface));
FixFpuLocations(); memset(m_Video_Interface,0,sizeof(m_Video_Interface));
memset(m_Display_ControlReg,0,sizeof(m_Display_ControlReg));
memset(m_Audio_Interface,0,sizeof(m_Audio_Interface));
memset(m_SigProcessor_Interface,0,sizeof(m_SigProcessor_Interface));
memset(m_Peripheral_Interface,0,sizeof(m_Peripheral_Interface));
memset(m_SerialInterface,0,sizeof(m_SerialInterface));
m_AudioIntrReg = 0;
m_GfxIntrReg = 0;
m_RspIntrReg = 0;
FixFpuLocations();
} }
void CRegisters::SetAsCurrentSystem() void CRegisters::SetAsCurrentSystem()
{ {
_PROGRAM_COUNTER = &m_PROGRAM_COUNTER; _PROGRAM_COUNTER = &m_PROGRAM_COUNTER;
_GPR = m_GPR; _GPR = m_GPR;
_FPR = m_FPR; _FPR = m_FPR;
_CP0 = m_CP0; _CP0 = m_CP0;
_RegHI = &m_HI; _RegHI = &m_HI;
_RegLO = &m_LO; _RegLO = &m_LO;
_FPR_S = m_FPR_S; _FPR_S = m_FPR_S;
_FPR_D = m_FPR_D; _FPR_D = m_FPR_D;
_FPCR = m_FPCR; _FPCR = m_FPCR;
_LLBit = &m_LLBit; _LLBit = &m_LLBit;
_RoundingModel = &m_RoundingModel; _RoundingModel = &m_RoundingModel;
} }
void CRegisters::CheckInterrupts() void CRegisters::CheckInterrupts()
{ {
if (!m_System->bFixedAudio() && CpuType() != CPU_SyncCores) if (!m_System->bFixedAudio() && CpuType() != CPU_SyncCores)
{ {
MI_INTR_REG &= ~MI_INTR_AI; MI_INTR_REG &= ~MI_INTR_AI;
MI_INTR_REG |= (m_AudioIntrReg & MI_INTR_AI); MI_INTR_REG |= (m_AudioIntrReg & MI_INTR_AI);
} }
MI_INTR_REG |= (m_RspIntrReg & MI_INTR_SP); MI_INTR_REG |= (m_RspIntrReg & MI_INTR_SP);
MI_INTR_REG |= (m_GfxIntrReg & MI_INTR_DP); MI_INTR_REG |= (m_GfxIntrReg & MI_INTR_DP);
if ((MI_INTR_MASK_REG & MI_INTR_REG) != 0) if ((MI_INTR_MASK_REG & MI_INTR_REG) != 0)
{ {
FAKE_CAUSE_REGISTER |= CAUSE_IP2; FAKE_CAUSE_REGISTER |= CAUSE_IP2;
} }
else else
{ {
FAKE_CAUSE_REGISTER &= ~CAUSE_IP2; FAKE_CAUSE_REGISTER &= ~CAUSE_IP2;
} }
if (( STATUS_REGISTER & STATUS_IE ) == 0 ) if (( STATUS_REGISTER & STATUS_IE ) == 0 )
{ {
return; return;
} }
if (( STATUS_REGISTER & STATUS_EXL ) != 0 ) if (( STATUS_REGISTER & STATUS_EXL ) != 0 )
{ {
return; return;
} }
if (( STATUS_REGISTER & STATUS_ERL ) != 0 ) if (( STATUS_REGISTER & STATUS_ERL ) != 0 )
{ {
return; return;
} }
if (( STATUS_REGISTER & FAKE_CAUSE_REGISTER & 0xFF00) != 0) if (( STATUS_REGISTER & FAKE_CAUSE_REGISTER & 0xFF00) != 0)
{ {
if (m_FirstInterupt) if (m_FirstInterupt)
{ {
m_FirstInterupt = false; m_FirstInterupt = false;
if (g_Recompiler) if (g_Recompiler)
{ {
g_Recompiler->ClearRecompCode_Virt(0x80000000,0x200,CRecompiler::Remove_InitialCode); g_Recompiler->ClearRecompCode_Virt(0x80000000,0x200,CRecompiler::Remove_InitialCode);
} }
} }
m_SystemEvents->QueueEvent(SysEvent_ExecuteInterrupt); m_SystemEvents->QueueEvent(SysEvent_ExecuteInterrupt);
} }
} }
void CRegisters::DoAddressError(bool DelaySlot, DWORD BadVaddr, bool FromRead) void CRegisters::DoAddressError(bool DelaySlot, uint32_t BadVaddr, bool FromRead)
{ {
if (bHaveDebugger()) if (bHaveDebugger())
{ {
g_Notify->DisplayError(L"AddressError"); g_Notify->DisplayError(L"AddressError");
if (( STATUS_REGISTER & STATUS_EXL ) != 0 ) if (( STATUS_REGISTER & STATUS_EXL ) != 0 )
{ {
g_Notify->DisplayError(L"EXL set in AddressError Exception"); g_Notify->DisplayError(L"EXL set in AddressError Exception");
} }
if (( STATUS_REGISTER & STATUS_ERL ) != 0 ) if (( STATUS_REGISTER & STATUS_ERL ) != 0 )
{ {
g_Notify->DisplayError(L"ERL set in AddressError Exception"); g_Notify->DisplayError(L"ERL set in AddressError Exception");
} }
} }
if (FromRead) if (FromRead)
{ {
CAUSE_REGISTER = EXC_RADE; CAUSE_REGISTER = EXC_RADE;
} }
else else
{ {
CAUSE_REGISTER = EXC_WADE; CAUSE_REGISTER = EXC_WADE;
} }
BAD_VADDR_REGISTER = BadVaddr; BAD_VADDR_REGISTER = BadVaddr;
if (DelaySlot) if (DelaySlot)
{ {
CAUSE_REGISTER |= CAUSE_BD; CAUSE_REGISTER |= CAUSE_BD;
EPC_REGISTER = m_PROGRAM_COUNTER - 4; EPC_REGISTER = m_PROGRAM_COUNTER - 4;
} }
else else
{ {
EPC_REGISTER = m_PROGRAM_COUNTER; EPC_REGISTER = m_PROGRAM_COUNTER;
} }
STATUS_REGISTER |= STATUS_EXL; STATUS_REGISTER |= STATUS_EXL;
m_PROGRAM_COUNTER = 0x80000180; m_PROGRAM_COUNTER = 0x80000180;
} }
void CRegisters::FixFpuLocations() void CRegisters::FixFpuLocations()
{ {
if ((STATUS_REGISTER & STATUS_FR) == 0) if ((STATUS_REGISTER & STATUS_FR) == 0)
{ {
for (int count = 0; count < 32; count ++) for (int count = 0; count < 32; count ++)
{ {
m_FPR_S[count] = &m_FPR[count >> 1].F[count & 1]; m_FPR_S[count] = &m_FPR[count >> 1].F[count & 1];
m_FPR_D[count] = &m_FPR[count >> 1].D; m_FPR_D[count] = &m_FPR[count >> 1].D;
} }
} }
else else
{ {
for (int count = 0; count < 32; count ++) { for (int count = 0; count < 32; count ++) {
m_FPR_S[count] = &m_FPR[count].F[1]; m_FPR_S[count] = &m_FPR[count].F[1];
m_FPR_D[count] = &m_FPR[count].D; m_FPR_D[count] = &m_FPR[count].D;
} }
} }
} }
void CRegisters::DoBreakException(bool DelaySlot) void CRegisters::DoBreakException(bool DelaySlot)
{ {
if (bHaveDebugger()) if (bHaveDebugger())
{ {
if (( STATUS_REGISTER & STATUS_EXL ) != 0 ) if (( STATUS_REGISTER & STATUS_EXL ) != 0 )
{ {
g_Notify->DisplayError(L"EXL set in Break Exception"); g_Notify->DisplayError(L"EXL set in Break Exception");
} }
if (( STATUS_REGISTER & STATUS_ERL ) != 0 ) if (( STATUS_REGISTER & STATUS_ERL ) != 0 )
{ {
g_Notify->DisplayError(L"ERL set in Break Exception"); g_Notify->DisplayError(L"ERL set in Break Exception");
} }
} }
CAUSE_REGISTER = EXC_BREAK; CAUSE_REGISTER = EXC_BREAK;
if (DelaySlot) if (DelaySlot)
{ {
CAUSE_REGISTER |= CAUSE_BD; CAUSE_REGISTER |= CAUSE_BD;
EPC_REGISTER = m_PROGRAM_COUNTER - 4; EPC_REGISTER = m_PROGRAM_COUNTER - 4;
} }
else else
{ {
EPC_REGISTER = m_PROGRAM_COUNTER; EPC_REGISTER = m_PROGRAM_COUNTER;
} }
STATUS_REGISTER |= STATUS_EXL; STATUS_REGISTER |= STATUS_EXL;
m_PROGRAM_COUNTER = 0x80000180; m_PROGRAM_COUNTER = 0x80000180;
} }
void CRegisters::DoCopUnusableException(bool DelaySlot, int Coprocessor) void CRegisters::DoCopUnusableException(bool DelaySlot, int Coprocessor)
{ {
if (bHaveDebugger()) if (bHaveDebugger())
{ {
if (( STATUS_REGISTER & STATUS_EXL ) != 0 ) if (( STATUS_REGISTER & STATUS_EXL ) != 0 )
{ {
g_Notify->DisplayError(L"EXL set in Break Exception"); g_Notify->DisplayError(L"EXL set in Break Exception");
} }
if (( STATUS_REGISTER & STATUS_ERL ) != 0 ) if (( STATUS_REGISTER & STATUS_ERL ) != 0 )
{ {
g_Notify->DisplayError(L"ERL set in Break Exception"); g_Notify->DisplayError(L"ERL set in Break Exception");
} }
} }
CAUSE_REGISTER = EXC_CPU; CAUSE_REGISTER = EXC_CPU;
if (Coprocessor == 1) if (Coprocessor == 1)
{ {
CAUSE_REGISTER |= 0x10000000; CAUSE_REGISTER |= 0x10000000;
} }
if (DelaySlot) if (DelaySlot)
{ {
CAUSE_REGISTER |= CAUSE_BD; CAUSE_REGISTER |= CAUSE_BD;
EPC_REGISTER = m_PROGRAM_COUNTER - 4; EPC_REGISTER = m_PROGRAM_COUNTER - 4;
} }
else else
{ {
EPC_REGISTER = m_PROGRAM_COUNTER; EPC_REGISTER = m_PROGRAM_COUNTER;
} }
STATUS_REGISTER |= STATUS_EXL; STATUS_REGISTER |= STATUS_EXL;
m_PROGRAM_COUNTER = 0x80000180; m_PROGRAM_COUNTER = 0x80000180;
} }
bool CRegisters::DoIntrException(bool DelaySlot) bool CRegisters::DoIntrException(bool DelaySlot)
{ {
if ((STATUS_REGISTER & STATUS_IE) == 0) if ((STATUS_REGISTER & STATUS_IE) == 0)
{ {
return false; return false;
} }
if ((STATUS_REGISTER & STATUS_EXL) != 0) if ((STATUS_REGISTER & STATUS_EXL) != 0)
{ {
return false; return false;
} }
if ((STATUS_REGISTER & STATUS_ERL) != 0) if ((STATUS_REGISTER & STATUS_ERL) != 0)
{ {
return false; return false;
} }
if (g_LogOptions.GenerateLog && g_LogOptions.LogExceptions && !g_LogOptions.NoInterrupts) if (g_LogOptions.GenerateLog && g_LogOptions.LogExceptions && !g_LogOptions.NoInterrupts)
{ {
LogMessage("%08X: Interrupt Generated", m_PROGRAM_COUNTER); LogMessage("%08X: Interrupt Generated", m_PROGRAM_COUNTER);
} }
CAUSE_REGISTER = FAKE_CAUSE_REGISTER; CAUSE_REGISTER = FAKE_CAUSE_REGISTER;
CAUSE_REGISTER |= EXC_INT; CAUSE_REGISTER |= EXC_INT;
if (DelaySlot) if (DelaySlot)
{ {
CAUSE_REGISTER |= CAUSE_BD; CAUSE_REGISTER |= CAUSE_BD;
EPC_REGISTER = m_PROGRAM_COUNTER - 4; EPC_REGISTER = m_PROGRAM_COUNTER - 4;
} }
else else
{ {
EPC_REGISTER = m_PROGRAM_COUNTER; EPC_REGISTER = m_PROGRAM_COUNTER;
} }
STATUS_REGISTER |= STATUS_EXL; STATUS_REGISTER |= STATUS_EXL;
m_PROGRAM_COUNTER = 0x80000180; m_PROGRAM_COUNTER = 0x80000180;
return true; return true;
} }
void CRegisters::DoTLBReadMiss(bool DelaySlot, DWORD BadVaddr) void CRegisters::DoTLBReadMiss(bool DelaySlot, uint32_t BadVaddr)
{ {
CAUSE_REGISTER = EXC_RMISS; CAUSE_REGISTER = EXC_RMISS;
BAD_VADDR_REGISTER = BadVaddr; BAD_VADDR_REGISTER = BadVaddr;
CONTEXT_REGISTER &= 0xFF80000F; CONTEXT_REGISTER &= 0xFF80000F;
CONTEXT_REGISTER |= (BadVaddr >> 9) & 0x007FFFF0; CONTEXT_REGISTER |= (BadVaddr >> 9) & 0x007FFFF0;
ENTRYHI_REGISTER = (BadVaddr & 0xFFFFE000); ENTRYHI_REGISTER = (BadVaddr & 0xFFFFE000);
if ((STATUS_REGISTER & STATUS_EXL) == 0) if ((STATUS_REGISTER & STATUS_EXL) == 0)
{ {
if (DelaySlot) if (DelaySlot)
{ {
CAUSE_REGISTER |= CAUSE_BD; CAUSE_REGISTER |= CAUSE_BD;
EPC_REGISTER = m_PROGRAM_COUNTER - 4; EPC_REGISTER = m_PROGRAM_COUNTER - 4;
} }
else else
{ {
EPC_REGISTER = m_PROGRAM_COUNTER; EPC_REGISTER = m_PROGRAM_COUNTER;
} }
if (g_TLB->AddressDefined(BadVaddr)) if (g_TLB->AddressDefined(BadVaddr))
{ {
m_PROGRAM_COUNTER = 0x80000180; m_PROGRAM_COUNTER = 0x80000180;
} }
else else
{ {
m_PROGRAM_COUNTER = 0x80000000; m_PROGRAM_COUNTER = 0x80000000;
} }
STATUS_REGISTER |= STATUS_EXL; STATUS_REGISTER |= STATUS_EXL;
} }
else else
{ {
if (bHaveDebugger()) if (bHaveDebugger())
{ {
g_Notify->DisplayError(stdstr_f("TLBMiss - EXL Set\nBadVaddr = %X\nAddress Defined: %s",BadVaddr,g_TLB->AddressDefined(BadVaddr)?"TRUE":"FALSE").ToUTF16().c_str()); g_Notify->DisplayError(stdstr_f("TLBMiss - EXL Set\nBadVaddr = %X\nAddress Defined: %s",BadVaddr,g_TLB->AddressDefined(BadVaddr)?"TRUE":"FALSE").ToUTF16().c_str());
} }
m_PROGRAM_COUNTER = 0x80000180; m_PROGRAM_COUNTER = 0x80000180;
} }
} }
void CRegisters::DoSysCallException(bool DelaySlot) void CRegisters::DoSysCallException(bool DelaySlot)
{ {
if (bHaveDebugger()) if (bHaveDebugger())
{ {
if (( STATUS_REGISTER & STATUS_EXL ) != 0 ) if (( STATUS_REGISTER & STATUS_EXL ) != 0 )
{ {
g_Notify->DisplayError(L"EXL set in SysCall Exception"); g_Notify->DisplayError(L"EXL set in SysCall Exception");
} }
if (( STATUS_REGISTER & STATUS_ERL ) != 0 ) if (( STATUS_REGISTER & STATUS_ERL ) != 0 )
{ {
g_Notify->DisplayError(L"ERL set in SysCall Exception"); g_Notify->DisplayError(L"ERL set in SysCall Exception");
} }
} }
CAUSE_REGISTER = EXC_SYSCALL; CAUSE_REGISTER = EXC_SYSCALL;
if (DelaySlot) if (DelaySlot)
{ {
CAUSE_REGISTER |= CAUSE_BD; CAUSE_REGISTER |= CAUSE_BD;
EPC_REGISTER = m_PROGRAM_COUNTER - 4; EPC_REGISTER = m_PROGRAM_COUNTER - 4;
} }
else else
{ {
EPC_REGISTER = m_PROGRAM_COUNTER; EPC_REGISTER = m_PROGRAM_COUNTER;
} }
STATUS_REGISTER |= STATUS_EXL; STATUS_REGISTER |= STATUS_EXL;
m_PROGRAM_COUNTER = 0x80000180; m_PROGRAM_COUNTER = 0x80000180;
} }

808
Source/Project64/N64 System/Mips/Register Class.h
View File

@ -13,265 +13,280 @@
//CPO registers by name //CPO registers by name
class CP0registers class CP0registers
{ {
CP0registers();
protected: protected:
CP0registers (DWORD * _CP0); CP0registers (uint32_t * _CP0);
public: public:
DWORD & INDEX_REGISTER; uint32_t & INDEX_REGISTER;
DWORD & RANDOM_REGISTER; uint32_t & RANDOM_REGISTER;
DWORD & ENTRYLO0_REGISTER; uint32_t & ENTRYLO0_REGISTER;
DWORD & ENTRYLO1_REGISTER; uint32_t & ENTRYLO1_REGISTER;
DWORD & CONTEXT_REGISTER; uint32_t & CONTEXT_REGISTER;
DWORD & PAGE_MASK_REGISTER; uint32_t & PAGE_MASK_REGISTER;
DWORD & WIRED_REGISTER; uint32_t & WIRED_REGISTER;
DWORD & BAD_VADDR_REGISTER; uint32_t & BAD_VADDR_REGISTER;
DWORD & COUNT_REGISTER; uint32_t & COUNT_REGISTER;
DWORD & ENTRYHI_REGISTER; uint32_t & ENTRYHI_REGISTER;
DWORD & COMPARE_REGISTER; uint32_t & COMPARE_REGISTER;
DWORD & STATUS_REGISTER; uint32_t & STATUS_REGISTER;
DWORD & CAUSE_REGISTER; uint32_t & CAUSE_REGISTER;
DWORD & EPC_REGISTER; uint32_t & EPC_REGISTER;
DWORD & CONFIG_REGISTER; uint32_t & CONFIG_REGISTER;
DWORD & TAGLO_REGISTER; uint32_t & TAGLO_REGISTER;
DWORD & TAGHI_REGISTER; uint32_t & TAGHI_REGISTER;
DWORD & ERROREPC_REGISTER; uint32_t & ERROREPC_REGISTER;
DWORD & FAKE_CAUSE_REGISTER; uint32_t & FAKE_CAUSE_REGISTER;
private:
CP0registers(); // Disable default constructor
CP0registers(const CP0registers&); // Disable copy constructor
CP0registers& operator=(const CP0registers&); // Disable assignment
}; };
//CPO register flags //CPO register flags
enum enum
{ {
//Status Register //Status Register
STATUS_IE = 0x00000001, STATUS_EXL = 0x00000002, STATUS_ERL = 0x00000004, STATUS_IE = 0x00000001, STATUS_EXL = 0x00000002, STATUS_ERL = 0x00000004,
STATUS_IP0 = 0x00000100, STATUS_IP1 = 0x00000200, STATUS_IP2 = 0x00000400, STATUS_IP0 = 0x00000100, STATUS_IP1 = 0x00000200, STATUS_IP2 = 0x00000400,
STATUS_IP3 = 0x00000800, STATUS_IP4 = 0x00001000, STATUS_IP5 = 0x00002000, STATUS_IP3 = 0x00000800, STATUS_IP4 = 0x00001000, STATUS_IP5 = 0x00002000,
STATUS_IP6 = 0x00004000, STATUS_IP7 = 0x00008000, STATUS_BEV = 0x00400000, STATUS_IP6 = 0x00004000, STATUS_IP7 = 0x00008000, STATUS_BEV = 0x00400000,
STATUS_FR = 0x04000000, STATUS_CU0 = 0x10000000, STATUS_CU1 = 0x20000000, STATUS_FR = 0x04000000, STATUS_CU0 = 0x10000000, STATUS_CU1 = 0x20000000,
//Cause Flags //Cause Flags
CAUSE_EXC_CODE = 0xFF, CAUSE_EXC_CODE = 0xFF,
CAUSE_IP0 = 0x100, CAUSE_IP0 = 0x100,
CAUSE_IP1 = 0x200, CAUSE_IP1 = 0x200,
CAUSE_IP2 = 0x400, CAUSE_IP2 = 0x400,
CAUSE_IP3 = 0x800, CAUSE_IP3 = 0x800,
CAUSE_IP4 = 0x1000, CAUSE_IP4 = 0x1000,
CAUSE_IP5 = 0x2000, CAUSE_IP5 = 0x2000,
CAUSE_IP6 = 0x4000, CAUSE_IP6 = 0x4000,
CAUSE_IP7 = 0x8000, CAUSE_IP7 = 0x8000,
CAUSE_BD = 0x80000000, CAUSE_BD = 0x80000000,
//Cause exception ID's //Cause exception ID's
EXC_INT = 0, /* interrupt */ EXC_INT = 0, /* interrupt */
EXC_MOD = 4, /* TLB mod */ EXC_MOD = 4, /* TLB mod */
EXC_RMISS = 8, /* Read TLB Miss */ EXC_RMISS = 8, /* Read TLB Miss */
EXC_WMISS = 12, /* Write TLB Miss */ EXC_WMISS = 12, /* Write TLB Miss */
EXC_RADE = 16, /* Read Address Error */ EXC_RADE = 16, /* Read Address Error */
EXC_WADE = 20, /* Write Address Error */ EXC_WADE = 20, /* Write Address Error */
EXC_IBE = 24, /* Instruction Bus Error */ EXC_IBE = 24, /* Instruction Bus Error */
EXC_DBE = 28, /* Data Bus Error */ EXC_DBE = 28, /* Data Bus Error */
EXC_SYSCALL = 32, /* SYSCALL */ EXC_SYSCALL = 32, /* SYSCALL */
EXC_BREAK = 36, /* BREAKpoint */ EXC_BREAK = 36, /* BREAKpoint */
EXC_II = 40, /* Illegal Instruction */ EXC_II = 40, /* Illegal Instruction */
EXC_CPU = 44, /* CoProcessor Unusable */ EXC_CPU = 44, /* CoProcessor Unusable */
EXC_OV = 48, /* OVerflow */ EXC_OV = 48, /* OVerflow */
EXC_TRAP = 52, /* Trap exception */ EXC_TRAP = 52, /* Trap exception */
EXC_VCEI = 56, /* Virt. Coherency on Inst. fetch */ EXC_VCEI = 56, /* Virt. Coherency on Inst. fetch */
EXC_FPE = 60, /* Floating Point Exception */ EXC_FPE = 60, /* Floating Point Exception */
EXC_WATCH = 92, /* Watchpoint reference */ EXC_WATCH = 92, /* Watchpoint reference */
EXC_VCED = 124,/* Virt. Coherency on data read */ EXC_VCED = 124,/* Virt. Coherency on data read */
}; };
//Float point control status register flags //Float point control status register flags
enum enum
{ {
FPCSR_FS = 0x01000000, /* flush denorm to zero */ FPCSR_FS = 0x01000000, /* flush denorm to zero */
FPCSR_C = 0x00800000, /* condition bit */ FPCSR_C = 0x00800000, /* condition bit */
FPCSR_CE = 0x00020000, /* cause: unimplemented operation */ FPCSR_CE = 0x00020000, /* cause: unimplemented operation */
FPCSR_CV = 0x00010000, /* cause: invalid operation */ FPCSR_CV = 0x00010000, /* cause: invalid operation */
FPCSR_CZ = 0x00008000, /* cause: division by zero */ FPCSR_CZ = 0x00008000, /* cause: division by zero */
FPCSR_CO = 0x00004000, /* cause: overflow */ FPCSR_CO = 0x00004000, /* cause: overflow */
FPCSR_CU = 0x00002000, /* cause: underflow */ FPCSR_CU = 0x00002000, /* cause: underflow */
FPCSR_CI = 0x00001000, /* cause: inexact operation */ FPCSR_CI = 0x00001000, /* cause: inexact operation */
FPCSR_EV = 0x00000800, /* enable: invalid operation */ FPCSR_EV = 0x00000800, /* enable: invalid operation */
FPCSR_EZ = 0x00000400, /* enable: division by zero */ FPCSR_EZ = 0x00000400, /* enable: division by zero */
FPCSR_EO = 0x00000200, /* enable: overflow */ FPCSR_EO = 0x00000200, /* enable: overflow */
FPCSR_EU = 0x00000100, /* enable: underflow */ FPCSR_EU = 0x00000100, /* enable: underflow */
FPCSR_EI = 0x00000080, /* enable: inexact operation */ FPCSR_EI = 0x00000080, /* enable: inexact operation */
FPCSR_FV = 0x00000040, /* flag: invalid operation */ FPCSR_FV = 0x00000040, /* flag: invalid operation */
FPCSR_FZ = 0x00000020, /* flag: division by zero */ FPCSR_FZ = 0x00000020, /* flag: division by zero */
FPCSR_FO = 0x00000010, /* flag: overflow */ FPCSR_FO = 0x00000010, /* flag: overflow */
FPCSR_FU = 0x00000008, /* flag: underflow */ FPCSR_FU = 0x00000008, /* flag: underflow */
FPCSR_FI = 0x00000004, /* flag: inexact operation */ FPCSR_FI = 0x00000004, /* flag: inexact operation */
FPCSR_RM_MASK = 0x00000003, /* rounding mode mask */ FPCSR_RM_MASK = 0x00000003, /* rounding mode mask */
FPCSR_RM_RN = 0x00000000, /* round to nearest */ FPCSR_RM_RN = 0x00000000, /* round to nearest */
FPCSR_RM_RZ = 0x00000001, /* round to zero */ FPCSR_RM_RZ = 0x00000001, /* round to zero */
FPCSR_RM_RP = 0x00000002, /* round to positive infinity */ FPCSR_RM_RP = 0x00000002, /* round to positive infinity */
FPCSR_RM_RM = 0x00000003, /* round to negative infinity */ FPCSR_RM_RM = 0x00000003, /* round to negative infinity */
}; };
//Rdram Registers //Rdram Registers
class Rdram_InterfaceReg class Rdram_InterfaceReg
{ {
Rdram_InterfaceReg();
protected: protected:
Rdram_InterfaceReg (DWORD * _RdramInterface); Rdram_InterfaceReg (uint32_t * _RdramInterface);
public: public:
DWORD & RDRAM_CONFIG_REG; uint32_t & RDRAM_CONFIG_REG;
DWORD & RDRAM_DEVICE_TYPE_REG; uint32_t & RDRAM_DEVICE_TYPE_REG;
DWORD & RDRAM_DEVICE_ID_REG; uint32_t & RDRAM_DEVICE_ID_REG;
DWORD & RDRAM_DELAY_REG; uint32_t & RDRAM_DELAY_REG;
DWORD & RDRAM_MODE_REG; uint32_t & RDRAM_MODE_REG;
DWORD & RDRAM_REF_INTERVAL_REG; uint32_t & RDRAM_REF_INTERVAL_REG;
DWORD & RDRAM_REF_ROW_REG; uint32_t & RDRAM_REF_ROW_REG;
DWORD & RDRAM_RAS_INTERVAL_REG; uint32_t & RDRAM_RAS_INTERVAL_REG;
DWORD & RDRAM_MIN_INTERVAL_REG; uint32_t & RDRAM_MIN_INTERVAL_REG;
DWORD & RDRAM_ADDR_SELECT_REG; uint32_t & RDRAM_ADDR_SELECT_REG;
DWORD & RDRAM_DEVICE_MANUF_REG; uint32_t & RDRAM_DEVICE_MANUF_REG;
private:
Rdram_InterfaceReg(); // Disable default constructor
Rdram_InterfaceReg(const Rdram_InterfaceReg&); // Disable copy constructor
Rdram_InterfaceReg& operator=(const Rdram_InterfaceReg&); // Disable assignment
}; };
//Mips interface registers //Mips interface registers
class Mips_InterfaceReg class Mips_InterfaceReg
{ {
Mips_InterfaceReg ();
protected: protected:
Mips_InterfaceReg (DWORD * _MipsInterface); Mips_InterfaceReg (uint32_t * _MipsInterface);
public: public:
DWORD & MI_INIT_MODE_REG; uint32_t & MI_INIT_MODE_REG;
DWORD & MI_MODE_REG; uint32_t & MI_MODE_REG;
DWORD & MI_VERSION_REG; uint32_t & MI_VERSION_REG;
DWORD & MI_NOOP_REG; uint32_t & MI_NOOP_REG;
DWORD & MI_INTR_REG; uint32_t & MI_INTR_REG;
DWORD & MI_INTR_MASK_REG; uint32_t & MI_INTR_MASK_REG;
private:
Mips_InterfaceReg(); // Disable default constructor
Mips_InterfaceReg(const Mips_InterfaceReg&); // Disable copy constructor
Mips_InterfaceReg& operator=(const Mips_InterfaceReg&); // Disable assignment
}; };
//Mips interface flags //Mips interface flags
enum enum
{ {
MI_MODE_INIT = 0x0080, /* Bit 7: init mode */ MI_MODE_INIT = 0x0080, /* Bit 7: init mode */
MI_MODE_EBUS = 0x0100, /* Bit 8: ebus test mode */ MI_MODE_EBUS = 0x0100, /* Bit 8: ebus test mode */
MI_MODE_RDRAM = 0x0200, /* Bit 9: RDRAM reg mode */ MI_MODE_RDRAM = 0x0200, /* Bit 9: RDRAM reg mode */
MI_CLR_INIT = 0x0080, /* Bit 7: clear init mode */ MI_CLR_INIT = 0x0080, /* Bit 7: clear init mode */
MI_SET_INIT = 0x0100, /* Bit 8: set init mode */ MI_SET_INIT = 0x0100, /* Bit 8: set init mode */
MI_CLR_EBUS = 0x0200, /* Bit 9: clear ebus test */ MI_CLR_EBUS = 0x0200, /* Bit 9: clear ebus test */
MI_SET_EBUS = 0x0400, /* Bit 10: set ebus test mode */ MI_SET_EBUS = 0x0400, /* Bit 10: set ebus test mode */
MI_CLR_DP_INTR = 0x0800, /* Bit 11: clear dp interrupt */ MI_CLR_DP_INTR = 0x0800, /* Bit 11: clear dp interrupt */
MI_CLR_RDRAM = 0x1000, /* Bit 12: clear RDRAM reg */ MI_CLR_RDRAM = 0x1000, /* Bit 12: clear RDRAM reg */
MI_SET_RDRAM = 0x2000, /* Bit 13: set RDRAM reg mode */ MI_SET_RDRAM = 0x2000, /* Bit 13: set RDRAM reg mode */
//Flags for writing to MI_INTR_MASK_REG //Flags for writing to MI_INTR_MASK_REG
MI_INTR_MASK_CLR_SP = 0x0001, /* Bit 0: clear SP mask */ MI_INTR_MASK_CLR_SP = 0x0001, /* Bit 0: clear SP mask */
MI_INTR_MASK_SET_SP = 0x0002, /* Bit 1: set SP mask */ MI_INTR_MASK_SET_SP = 0x0002, /* Bit 1: set SP mask */
MI_INTR_MASK_CLR_SI = 0x0004, /* Bit 2: clear SI mask */ MI_INTR_MASK_CLR_SI = 0x0004, /* Bit 2: clear SI mask */
MI_INTR_MASK_SET_SI = 0x0008, /* Bit 3: set SI mask */ MI_INTR_MASK_SET_SI = 0x0008, /* Bit 3: set SI mask */
MI_INTR_MASK_CLR_AI = 0x0010, /* Bit 4: clear AI mask */ MI_INTR_MASK_CLR_AI = 0x0010, /* Bit 4: clear AI mask */
MI_INTR_MASK_SET_AI = 0x0020, /* Bit 5: set AI mask */ MI_INTR_MASK_SET_AI = 0x0020, /* Bit 5: set AI mask */
MI_INTR_MASK_CLR_VI = 0x0040, /* Bit 6: clear VI mask */ MI_INTR_MASK_CLR_VI = 0x0040, /* Bit 6: clear VI mask */
MI_INTR_MASK_SET_VI = 0x0080, /* Bit 7: set VI mask */ MI_INTR_MASK_SET_VI = 0x0080, /* Bit 7: set VI mask */
MI_INTR_MASK_CLR_PI = 0x0100, /* Bit 8: clear PI mask */ MI_INTR_MASK_CLR_PI = 0x0100, /* Bit 8: clear PI mask */
MI_INTR_MASK_SET_PI = 0x0200, /* Bit 9: set PI mask */ MI_INTR_MASK_SET_PI = 0x0200, /* Bit 9: set PI mask */
MI_INTR_MASK_CLR_DP = 0x0400, /* Bit 10: clear DP mask */ MI_INTR_MASK_CLR_DP = 0x0400, /* Bit 10: clear DP mask */
MI_INTR_MASK_SET_DP = 0x0800, /* Bit 11: set DP mask */ MI_INTR_MASK_SET_DP = 0x0800, /* Bit 11: set DP mask */
//Flags for reading from MI_INTR_MASK_REG //Flags for reading from MI_INTR_MASK_REG
MI_INTR_MASK_SP = 0x01, /* Bit 0: SP intr mask */ MI_INTR_MASK_SP = 0x01, /* Bit 0: SP intr mask */
MI_INTR_MASK_SI = 0x02, /* Bit 1: SI intr mask */ MI_INTR_MASK_SI = 0x02, /* Bit 1: SI intr mask */
MI_INTR_MASK_AI = 0x04, /* Bit 2: AI intr mask */ MI_INTR_MASK_AI = 0x04, /* Bit 2: AI intr mask */
MI_INTR_MASK_VI = 0x08, /* Bit 3: VI intr mask */ MI_INTR_MASK_VI = 0x08, /* Bit 3: VI intr mask */
MI_INTR_MASK_PI = 0x10, /* Bit 4: PI intr mask */ MI_INTR_MASK_PI = 0x10, /* Bit 4: PI intr mask */
MI_INTR_MASK_DP = 0x20, /* Bit 5: DP intr mask */ MI_INTR_MASK_DP = 0x20, /* Bit 5: DP intr mask */
MI_INTR_SP = 0x01, /* Bit 0: SP intr */ MI_INTR_SP = 0x01, /* Bit 0: SP intr */
MI_INTR_SI = 0x02, /* Bit 1: SI intr */ MI_INTR_SI = 0x02, /* Bit 1: SI intr */
MI_INTR_AI = 0x04, /* Bit 2: AI intr */ MI_INTR_AI = 0x04, /* Bit 2: AI intr */
MI_INTR_VI = 0x08, /* Bit 3: VI intr */ MI_INTR_VI = 0x08, /* Bit 3: VI intr */
MI_INTR_PI = 0x10, /* Bit 4: PI intr */ MI_INTR_PI = 0x10, /* Bit 4: PI intr */
MI_INTR_DP = 0x20, /* Bit 5: DP intr */ MI_INTR_DP = 0x20, /* Bit 5: DP intr */
}; };
//Mips interface registers //Mips interface registers
class Video_InterfaceReg class Video_InterfaceReg
{ {
Video_InterfaceReg();
protected: protected:
Video_InterfaceReg (DWORD * _VideoInterface); Video_InterfaceReg (uint32_t * _VideoInterface);
public: public:
DWORD & VI_STATUS_REG; uint32_t & VI_STATUS_REG;
DWORD & VI_CONTROL_REG; uint32_t & VI_CONTROL_REG;
DWORD & VI_ORIGIN_REG; uint32_t & VI_ORIGIN_REG;
DWORD & VI_DRAM_ADDR_REG; uint32_t & VI_DRAM_ADDR_REG;
DWORD & VI_WIDTH_REG; uint32_t & VI_WIDTH_REG;
DWORD & VI_H_WIDTH_REG; uint32_t & VI_H_WIDTH_REG;
DWORD & VI_INTR_REG; uint32_t & VI_INTR_REG;
DWORD & VI_V_INTR_REG; uint32_t & VI_V_INTR_REG;
DWORD & VI_CURRENT_REG; uint32_t & VI_CURRENT_REG;
DWORD & VI_V_CURRENT_LINE_REG; uint32_t & VI_V_CURRENT_LINE_REG;
DWORD & VI_BURST_REG; uint32_t & VI_BURST_REG;
DWORD & VI_TIMING_REG; uint32_t & VI_TIMING_REG;
DWORD & VI_V_SYNC_REG; uint32_t & VI_V_SYNC_REG;
DWORD & VI_H_SYNC_REG; uint32_t & VI_H_SYNC_REG;
DWORD & VI_LEAP_REG; uint32_t & VI_LEAP_REG;
DWORD & VI_H_SYNC_LEAP_REG; uint32_t & VI_H_SYNC_LEAP_REG;
DWORD & VI_H_START_REG; uint32_t & VI_H_START_REG;
DWORD & VI_H_VIDEO_REG; uint32_t & VI_H_VIDEO_REG;
DWORD & VI_V_START_REG; uint32_t & VI_V_START_REG;
DWORD & VI_V_VIDEO_REG; uint32_t & VI_V_VIDEO_REG;
DWORD & VI_V_BURST_REG; uint32_t & VI_V_BURST_REG;
DWORD & VI_X_SCALE_REG; uint32_t & VI_X_SCALE_REG;
DWORD & VI_Y_SCALE_REG; uint32_t & VI_Y_SCALE_REG;
private:
Video_InterfaceReg(); // Disable default constructor
Video_InterfaceReg(const Video_InterfaceReg&); // Disable copy constructor
Video_InterfaceReg& operator=(const Video_InterfaceReg&); // Disable assignment
}; };
//Display Processor Control Registers //Display Processor Control Registers
class DisplayControlReg class DisplayControlReg
{ {
DisplayControlReg();
protected: protected:
DisplayControlReg (DWORD * _DisplayProcessor); DisplayControlReg (uint32_t * _DisplayProcessor);
public: public:
DWORD & DPC_START_REG; uint32_t & DPC_START_REG;
DWORD & DPC_END_REG; uint32_t & DPC_END_REG;
DWORD & DPC_CURRENT_REG; uint32_t & DPC_CURRENT_REG;
DWORD & DPC_STATUS_REG; uint32_t & DPC_STATUS_REG;
DWORD & DPC_CLOCK_REG; uint32_t & DPC_CLOCK_REG;
DWORD & DPC_BUFBUSY_REG; uint32_t & DPC_BUFBUSY_REG;
DWORD & DPC_PIPEBUSY_REG; uint32_t & DPC_PIPEBUSY_REG;
DWORD & DPC_TMEM_REG; uint32_t & DPC_TMEM_REG;
private:
DisplayControlReg(); // Disable default constructor
DisplayControlReg(const DisplayControlReg&); // Disable copy constructor
DisplayControlReg& operator=(const DisplayControlReg&); // Disable assignment
}; };
enum enum
{ {
DPC_CLR_XBUS_DMEM_DMA = 0x0001, /* Bit 0: clear xbus_dmem_dma */ DPC_CLR_XBUS_DMEM_DMA = 0x0001, /* Bit 0: clear xbus_dmem_dma */
DPC_SET_XBUS_DMEM_DMA = 0x0002, /* Bit 1: set xbus_dmem_dma */ DPC_SET_XBUS_DMEM_DMA = 0x0002, /* Bit 1: set xbus_dmem_dma */
DPC_CLR_FREEZE = 0x0004, /* Bit 2: clear freeze */ DPC_CLR_FREEZE = 0x0004, /* Bit 2: clear freeze */
DPC_SET_FREEZE = 0x0008, /* Bit 3: set freeze */ DPC_SET_FREEZE = 0x0008, /* Bit 3: set freeze */
DPC_CLR_FLUSH = 0x0010, /* Bit 4: clear flush */ DPC_CLR_FLUSH = 0x0010, /* Bit 4: clear flush */
DPC_SET_FLUSH = 0x0020, /* Bit 5: set flush */ DPC_SET_FLUSH = 0x0020, /* Bit 5: set flush */
DPC_CLR_TMEM_CTR = 0x0040, /* Bit 6: clear tmem ctr */ DPC_CLR_TMEM_CTR = 0x0040, /* Bit 6: clear tmem ctr */
DPC_CLR_PIPE_CTR = 0x0080, /* Bit 7: clear pipe ctr */ DPC_CLR_PIPE_CTR = 0x0080, /* Bit 7: clear pipe ctr */
DPC_CLR_CMD_CTR = 0x0100, /* Bit 8: clear cmd ctr */ DPC_CLR_CMD_CTR = 0x0100, /* Bit 8: clear cmd ctr */
DPC_CLR_CLOCK_CTR = 0x0200, /* Bit 9: clear clock ctr */ DPC_CLR_CLOCK_CTR = 0x0200, /* Bit 9: clear clock ctr */
DPC_STATUS_XBUS_DMEM_DMA = 0x001, /* Bit 0: xbus_dmem_dma */ DPC_STATUS_XBUS_DMEM_DMA = 0x001, /* Bit 0: xbus_dmem_dma */
DPC_STATUS_FREEZE = 0x002, /* Bit 1: freeze */ DPC_STATUS_FREEZE = 0x002, /* Bit 1: freeze */
DPC_STATUS_FLUSH = 0x004, /* Bit 2: flush */ DPC_STATUS_FLUSH = 0x004, /* Bit 2: flush */
DPC_STATUS_START_GCLK = 0x008, /* Bit 3: start gclk */ DPC_STATUS_START_GCLK = 0x008, /* Bit 3: start gclk */
DPC_STATUS_TMEM_BUSY = 0x010, /* Bit 4: tmem busy */ DPC_STATUS_TMEM_BUSY = 0x010, /* Bit 4: tmem busy */
DPC_STATUS_PIPE_BUSY = 0x020, /* Bit 5: pipe busy */ DPC_STATUS_PIPE_BUSY = 0x020, /* Bit 5: pipe busy */
DPC_STATUS_CMD_BUSY = 0x040, /* Bit 6: cmd busy */ DPC_STATUS_CMD_BUSY = 0x040, /* Bit 6: cmd busy */
DPC_STATUS_CBUF_READY = 0x080, /* Bit 7: cbuf ready */ DPC_STATUS_CBUF_READY = 0x080, /* Bit 7: cbuf ready */
DPC_STATUS_DMA_BUSY = 0x100, /* Bit 8: dma busy */ DPC_STATUS_DMA_BUSY = 0x100, /* Bit 8: dma busy */
DPC_STATUS_END_VALID = 0x200, /* Bit 9: end valid */ DPC_STATUS_END_VALID = 0x200, /* Bit 9: end valid */
DPC_STATUS_START_VALID = 0x400, /* Bit 10: start valid */ DPC_STATUS_START_VALID = 0x400, /* Bit 10: start valid */
}; };
/* /*
@ -279,275 +294,290 @@ enum
*/ */
class AudioInterfaceReg class AudioInterfaceReg
{ {
AudioInterfaceReg();
protected: protected:
AudioInterfaceReg (DWORD * _AudioInterface); AudioInterfaceReg (uint32_t * _AudioInterface);
public: public:
DWORD & AI_DRAM_ADDR_REG; uint32_t & AI_DRAM_ADDR_REG;
DWORD & AI_LEN_REG; uint32_t & AI_LEN_REG;
DWORD & AI_CONTROL_REG; uint32_t & AI_CONTROL_REG;
DWORD & AI_STATUS_REG; uint32_t & AI_STATUS_REG;
DWORD & AI_DACRATE_REG; uint32_t & AI_DACRATE_REG;
DWORD & AI_BITRATE_REG; uint32_t & AI_BITRATE_REG;
private:
AudioInterfaceReg(); // Disable default constructor
AudioInterfaceReg(const AudioInterfaceReg&); // Disable copy constructor
AudioInterfaceReg& operator=(const AudioInterfaceReg&); // Disable assignment
}; };
enum enum
{ {
AI_STATUS_FIFO_FULL = 0x80000000, /* Bit 31: full */ AI_STATUS_FIFO_FULL = 0x80000000, /* Bit 31: full */
AI_STATUS_DMA_BUSY = 0x40000000, /* Bit 30: busy */ AI_STATUS_DMA_BUSY = 0x40000000, /* Bit 30: busy */
}; };
//Audio Interface registers; //Audio Interface registers;
class PeripheralInterfaceReg class PeripheralInterfaceReg
{ {
PeripheralInterfaceReg();
protected: protected:
PeripheralInterfaceReg (DWORD * PeripheralInterface); PeripheralInterfaceReg (uint32_t * PeripheralInterface);
public: public:
DWORD & PI_DRAM_ADDR_REG; uint32_t & PI_DRAM_ADDR_REG;
DWORD & PI_CART_ADDR_REG; uint32_t & PI_CART_ADDR_REG;
DWORD & PI_RD_LEN_REG; uint32_t & PI_RD_LEN_REG;
DWORD & PI_WR_LEN_REG; uint32_t & PI_WR_LEN_REG;
DWORD & PI_STATUS_REG; uint32_t & PI_STATUS_REG;
DWORD & PI_BSD_DOM1_LAT_REG; uint32_t & PI_BSD_DOM1_LAT_REG;
DWORD & PI_DOMAIN1_REG; uint32_t & PI_DOMAIN1_REG;
DWORD & PI_BSD_DOM1_PWD_REG; uint32_t & PI_BSD_DOM1_PWD_REG;
DWORD & PI_BSD_DOM1_PGS_REG; uint32_t & PI_BSD_DOM1_PGS_REG;
DWORD & PI_BSD_DOM1_RLS_REG; uint32_t & PI_BSD_DOM1_RLS_REG;
DWORD & PI_BSD_DOM2_LAT_REG; uint32_t & PI_BSD_DOM2_LAT_REG;
DWORD & PI_DOMAIN2_REG; uint32_t & PI_DOMAIN2_REG;
DWORD & PI_BSD_DOM2_PWD_REG; uint32_t & PI_BSD_DOM2_PWD_REG;
DWORD & PI_BSD_DOM2_PGS_REG; uint32_t & PI_BSD_DOM2_PGS_REG;
DWORD & PI_BSD_DOM2_RLS_REG; uint32_t & PI_BSD_DOM2_RLS_REG;
private:
PeripheralInterfaceReg(); // Disable default constructor
PeripheralInterfaceReg(const PeripheralInterfaceReg&); // Disable copy constructor
PeripheralInterfaceReg& operator=(const PeripheralInterfaceReg&); // Disable assignment
}; };
class RDRAMInt_InterfaceReg class RDRAMInt_InterfaceReg
{ {
RDRAMInt_InterfaceReg();
protected: protected:
RDRAMInt_InterfaceReg (DWORD * RdramInterface); RDRAMInt_InterfaceReg (uint32_t * RdramInterface);
public: public:
DWORD & RI_MODE_REG; uint32_t & RI_MODE_REG;
DWORD & RI_CONFIG_REG; uint32_t & RI_CONFIG_REG;
DWORD & RI_CURRENT_LOAD_REG; uint32_t & RI_CURRENT_LOAD_REG;
DWORD & RI_SELECT_REG; uint32_t & RI_SELECT_REG;
DWORD & RI_COUNT_REG; uint32_t & RI_COUNT_REG;
DWORD & RI_REFRESH_REG; uint32_t & RI_REFRESH_REG;
DWORD & RI_LATENCY_REG; uint32_t & RI_LATENCY_REG;
DWORD & RI_RERROR_REG; uint32_t & RI_RERROR_REG;
DWORD & RI_WERROR_REG; uint32_t & RI_WERROR_REG;
private:
RDRAMInt_InterfaceReg(); // Disable default constructor
RDRAMInt_InterfaceReg(const RDRAMInt_InterfaceReg&); // Disable copy constructor
RDRAMInt_InterfaceReg& operator=(const RDRAMInt_InterfaceReg&); // Disable assignment
}; };
//Signal Processor Interface; //Signal Processor Interface;
class SigProcessor_InterfaceReg class SigProcessor_InterfaceReg
{ {
protected: protected:
SigProcessor_InterfaceReg (DWORD * _SignalProcessorInterface); SigProcessor_InterfaceReg (uint32_t * _SignalProcessorInterface);
public: public:
DWORD & SP_MEM_ADDR_REG; uint32_t & SP_MEM_ADDR_REG;
DWORD & SP_DRAM_ADDR_REG; uint32_t & SP_DRAM_ADDR_REG;
DWORD & SP_RD_LEN_REG; uint32_t & SP_RD_LEN_REG;
DWORD & SP_WR_LEN_REG; uint32_t & SP_WR_LEN_REG;
DWORD & SP_STATUS_REG; uint32_t & SP_STATUS_REG;
DWORD & SP_DMA_FULL_REG; uint32_t & SP_DMA_FULL_REG;
DWORD & SP_DMA_BUSY_REG; uint32_t & SP_DMA_BUSY_REG;
DWORD & SP_SEMAPHORE_REG; uint32_t & SP_SEMAPHORE_REG;
DWORD & SP_PC_REG; uint32_t & SP_PC_REG;
DWORD & SP_IBIST_REG; uint32_t & SP_IBIST_REG;
private:
SigProcessor_InterfaceReg(); // Disable default constructor
SigProcessor_InterfaceReg(const SigProcessor_InterfaceReg&); // Disable copy constructor
SigProcessor_InterfaceReg& operator=(const SigProcessor_InterfaceReg&); // Disable assignment
}; };
//Signal Processor interface flags //Signal Processor interface flags
enum enum
{ {
SP_CLR_HALT = 0x00001, /* Bit 0: clear halt */ SP_CLR_HALT = 0x00001, /* Bit 0: clear halt */
SP_SET_HALT = 0x00002, /* Bit 1: set halt */ SP_SET_HALT = 0x00002, /* Bit 1: set halt */
SP_CLR_BROKE = 0x00004, /* Bit 2: clear broke */ SP_CLR_BROKE = 0x00004, /* Bit 2: clear broke */
SP_CLR_INTR = 0x00008, /* Bit 3: clear intr */ SP_CLR_INTR = 0x00008, /* Bit 3: clear intr */
SP_SET_INTR = 0x00010, /* Bit 4: set intr */ SP_SET_INTR = 0x00010, /* Bit 4: set intr */
SP_CLR_SSTEP = 0x00020, /* Bit 5: clear sstep */ SP_CLR_SSTEP = 0x00020, /* Bit 5: clear sstep */
SP_SET_SSTEP = 0x00040, /* Bit 6: set sstep */ SP_SET_SSTEP = 0x00040, /* Bit 6: set sstep */
SP_CLR_INTR_BREAK = 0x00080, /* Bit 7: clear intr on break */ SP_CLR_INTR_BREAK = 0x00080, /* Bit 7: clear intr on break */
SP_SET_INTR_BREAK = 0x00100, /* Bit 8: set intr on break */ SP_SET_INTR_BREAK = 0x00100, /* Bit 8: set intr on break */
SP_CLR_SIG0 = 0x00200, /* Bit 9: clear signal 0 */ SP_CLR_SIG0 = 0x00200, /* Bit 9: clear signal 0 */
SP_SET_SIG0 = 0x00400, /* Bit 10: set signal 0 */ SP_SET_SIG0 = 0x00400, /* Bit 10: set signal 0 */
SP_CLR_SIG1 = 0x00800, /* Bit 11: clear signal 1 */ SP_CLR_SIG1 = 0x00800, /* Bit 11: clear signal 1 */
SP_SET_SIG1 = 0x01000, /* Bit 12: set signal 1 */ SP_SET_SIG1 = 0x01000, /* Bit 12: set signal 1 */
SP_CLR_SIG2 = 0x02000, /* Bit 13: clear signal 2 */ SP_CLR_SIG2 = 0x02000, /* Bit 13: clear signal 2 */
SP_SET_SIG2 = 0x04000, /* Bit 14: set signal 2 */ SP_SET_SIG2 = 0x04000, /* Bit 14: set signal 2 */
SP_CLR_SIG3 = 0x08000, /* Bit 15: clear signal 3 */ SP_CLR_SIG3 = 0x08000, /* Bit 15: clear signal 3 */
SP_SET_SIG3 = 0x10000, /* Bit 16: set signal 3 */ SP_SET_SIG3 = 0x10000, /* Bit 16: set signal 3 */
SP_CLR_SIG4 = 0x20000, /* Bit 17: clear signal 4 */ SP_CLR_SIG4 = 0x20000, /* Bit 17: clear signal 4 */
SP_SET_SIG4 = 0x40000, /* Bit 18: set signal 4 */ SP_SET_SIG4 = 0x40000, /* Bit 18: set signal 4 */
SP_CLR_SIG5 = 0x80000, /* Bit 19: clear signal 5 */ SP_CLR_SIG5 = 0x80000, /* Bit 19: clear signal 5 */
SP_SET_SIG5 = 0x100000, /* Bit 20: set signal 5 */ SP_SET_SIG5 = 0x100000, /* Bit 20: set signal 5 */
SP_CLR_SIG6 = 0x200000, /* Bit 21: clear signal 6 */ SP_CLR_SIG6 = 0x200000, /* Bit 21: clear signal 6 */
SP_SET_SIG6 = 0x400000, /* Bit 22: set signal 6 */ SP_SET_SIG6 = 0x400000, /* Bit 22: set signal 6 */
SP_CLR_SIG7 = 0x800000, /* Bit 23: clear signal 7 */ SP_CLR_SIG7 = 0x800000, /* Bit 23: clear signal 7 */
SP_SET_SIG7 = 0x1000000, /* Bit 24: set signal 7 */ SP_SET_SIG7 = 0x1000000, /* Bit 24: set signal 7 */
SP_STATUS_HALT = 0x001, /* Bit 0: halt */ SP_STATUS_HALT = 0x001, /* Bit 0: halt */
SP_STATUS_BROKE = 0x002, /* Bit 1: broke */ SP_STATUS_BROKE = 0x002, /* Bit 1: broke */
SP_STATUS_DMA_BUSY = 0x004, /* Bit 2: dma busy */ SP_STATUS_DMA_BUSY = 0x004, /* Bit 2: dma busy */
SP_STATUS_DMA_FULL = 0x008, /* Bit 3: dma full */ SP_STATUS_DMA_FULL = 0x008, /* Bit 3: dma full */
SP_STATUS_IO_FULL = 0x010, /* Bit 4: io full */ SP_STATUS_IO_FULL = 0x010, /* Bit 4: io full */
SP_STATUS_SSTEP = 0x020, /* Bit 5: single step */ SP_STATUS_SSTEP = 0x020, /* Bit 5: single step */
SP_STATUS_INTR_BREAK = 0x040, /* Bit 6: interrupt on break */ SP_STATUS_INTR_BREAK = 0x040, /* Bit 6: interrupt on break */
SP_STATUS_SIG0 = 0x080, /* Bit 7: signal 0 set */ SP_STATUS_SIG0 = 0x080, /* Bit 7: signal 0 set */
SP_STATUS_SIG1 = 0x100, /* Bit 8: signal 1 set */ SP_STATUS_SIG1 = 0x100, /* Bit 8: signal 1 set */
SP_STATUS_SIG2 = 0x200, /* Bit 9: signal 2 set */ SP_STATUS_SIG2 = 0x200, /* Bit 9: signal 2 set */
SP_STATUS_SIG3 = 0x400, /* Bit 10: signal 3 set */ SP_STATUS_SIG3 = 0x400, /* Bit 10: signal 3 set */
SP_STATUS_SIG4 = 0x800, /* Bit 11: signal 4 set */ SP_STATUS_SIG4 = 0x800, /* Bit 11: signal 4 set */
SP_STATUS_SIG5 = 0x1000, /* Bit 12: signal 5 set */ SP_STATUS_SIG5 = 0x1000, /* Bit 12: signal 5 set */
SP_STATUS_SIG6 = 0x2000, /* Bit 13: signal 6 set */ SP_STATUS_SIG6 = 0x2000, /* Bit 13: signal 6 set */
SP_STATUS_SIG7 = 0x4000, /* Bit 14: signal 7 set */ SP_STATUS_SIG7 = 0x4000, /* Bit 14: signal 7 set */
}; };
//Peripheral Interface flags //Peripheral Interface flags
enum enum
{ {
PI_STATUS_DMA_BUSY = 0x01, PI_STATUS_DMA_BUSY = 0x01,
PI_STATUS_IO_BUSY = 0x02, PI_STATUS_IO_BUSY = 0x02,
PI_STATUS_ERROR = 0x04, PI_STATUS_ERROR = 0x04,
PI_SET_RESET = 0x01, PI_SET_RESET = 0x01,
PI_CLR_INTR = 0x02, PI_CLR_INTR = 0x02,
}; };
class Serial_InterfaceReg class Serial_InterfaceReg
{ {
Serial_InterfaceReg();
protected: protected:
Serial_InterfaceReg (DWORD * SerialInterface); Serial_InterfaceReg (uint32_t * SerialInterface);
public: public:
DWORD & SI_DRAM_ADDR_REG; uint32_t & SI_DRAM_ADDR_REG;
DWORD & SI_PIF_ADDR_RD64B_REG; uint32_t & SI_PIF_ADDR_RD64B_REG;
DWORD & SI_PIF_ADDR_WR64B_REG; uint32_t & SI_PIF_ADDR_WR64B_REG;
DWORD & SI_STATUS_REG; uint32_t & SI_STATUS_REG;
private:
Serial_InterfaceReg(); // Disable default constructor
Serial_InterfaceReg(const Serial_InterfaceReg&); // Disable copy constructor
Serial_InterfaceReg& operator=(const Serial_InterfaceReg&); // Disable assignment
}; };
//Serial Interface flags //Serial Interface flags
enum enum
{ {
SI_STATUS_DMA_BUSY = 0x0001, SI_STATUS_DMA_BUSY = 0x0001,
SI_STATUS_RD_BUSY = 0x0002, SI_STATUS_RD_BUSY = 0x0002,
SI_STATUS_DMA_ERROR = 0x0008, SI_STATUS_DMA_ERROR = 0x0008,
SI_STATUS_INTERRUPT = 0x1000, SI_STATUS_INTERRUPT = 0x1000,
}; };
enum ROUNDING_MODE enum ROUNDING_MODE
{ {
ROUND_NEAR = _RC_NEAR, ROUND_NEAR = 0x00000000, // _RC_NEAR
ROUND_DOWN = _RC_DOWN, ROUND_DOWN = 0x00000100, // _RC_DOWN
ROUND_UP = _RC_UP, ROUND_UP = 0x00000200, // _RC_UP
ROUND_CHOP = _RC_CHOP, ROUND_CHOP = 0x00000300, // _RC_CHOP
}; };
class CRegName { class CRegName
{
public: public:
static const char *GPR[32]; static const char *GPR[32];
static const char *GPR_Hi[32]; static const char *GPR_Hi[32];
static const char *GPR_Lo[32]; static const char *GPR_Lo[32];
static const char *Cop0[32]; static const char *Cop0[32];
static const char *FPR[32]; static const char *FPR[32];
static const char *FPR_Ctrl[32]; static const char *FPR_Ctrl[32];
}; };
class CSystemRegisters class CSystemRegisters
{ {
protected: protected:
static DWORD * _PROGRAM_COUNTER; static uint32_t * _PROGRAM_COUNTER;
static MIPS_DWORD * _GPR; static MIPS_DWORD * _GPR;
static MIPS_DWORD * _FPR; static MIPS_DWORD * _FPR;
static DWORD * _CP0; static uint32_t * _CP0;
static MIPS_DWORD * _RegHI; static MIPS_DWORD * _RegHI;
static MIPS_DWORD * _RegLO; static MIPS_DWORD * _RegLO;
static float ** _FPR_S; static float ** _FPR_S;
static double ** _FPR_D; static double ** _FPR_D;
static DWORD * _FPCR; static uint32_t * _FPCR;
static DWORD * _LLBit; static uint32_t * _LLBit;
static ROUNDING_MODE * _RoundingModel; static ROUNDING_MODE * _RoundingModel;
}; };
class CN64System; class CN64System;
class CSystemEvents; class CSystemEvents;
class CRegisters : class CRegisters :
private CDebugSettings, private CDebugSettings,
private CGameSettings, private CGameSettings,
protected CSystemRegisters, protected CSystemRegisters,
public CP0registers, public CP0registers,
public Rdram_InterfaceReg, public Rdram_InterfaceReg,
public Mips_InterfaceReg, public Mips_InterfaceReg,
public Video_InterfaceReg, public Video_InterfaceReg,
public AudioInterfaceReg, public AudioInterfaceReg,
public PeripheralInterfaceReg, public PeripheralInterfaceReg,
public RDRAMInt_InterfaceReg, public RDRAMInt_InterfaceReg,
public SigProcessor_InterfaceReg, public SigProcessor_InterfaceReg,
public DisplayControlReg, public DisplayControlReg,
public Serial_InterfaceReg public Serial_InterfaceReg
{ {
public: public:
CRegisters(CN64System * System, CSystemEvents * SystemEvents); CRegisters(CN64System * System, CSystemEvents * SystemEvents);
//General Registers //General Registers
DWORD m_PROGRAM_COUNTER; uint32_t m_PROGRAM_COUNTER;
MIPS_DWORD m_GPR[32]; MIPS_DWORD m_GPR[32];
DWORD m_CP0[33]; uint32_t m_CP0[33];
MIPS_DWORD m_HI; MIPS_DWORD m_HI;
MIPS_DWORD m_LO; MIPS_DWORD m_LO;
DWORD m_LLBit; uint32_t m_LLBit;
//Floating point registers/information
DWORD m_FPCR[32];
ROUNDING_MODE m_RoundingModel;
MIPS_DWORD m_FPR[32];
float * m_FPR_S[32];
double * m_FPR_D[32];
//Memory Mapped N64 registers //Floating point registers/information
DWORD m_RDRAM_Registers[10]; uint32_t m_FPCR[32];
DWORD m_SigProcessor_Interface[10]; ROUNDING_MODE m_RoundingModel;
DWORD m_Display_ControlReg[10]; MIPS_DWORD m_FPR[32];
DWORD m_Mips_Interface[4]; float * m_FPR_S[32];
DWORD m_Video_Interface[14]; double * m_FPR_D[32];
DWORD m_Audio_Interface[6];
DWORD m_Peripheral_Interface[13];
DWORD m_RDRAM_Interface[8];
DWORD m_SerialInterface[4];
DWORD m_AudioIntrReg;
DWORD m_GfxIntrReg;
DWORD m_RspIntrReg;
//Memory Mapped N64 registers
uint32_t m_RDRAM_Registers[10];
uint32_t m_SigProcessor_Interface[10];
uint32_t m_Display_ControlReg[10];
uint32_t m_Mips_Interface[4];
uint32_t m_Video_Interface[14];
uint32_t m_Audio_Interface[6];
uint32_t m_Peripheral_Interface[13];
uint32_t m_RDRAM_Interface[8];
uint32_t m_SerialInterface[4];
uint32_t m_AudioIntrReg;
uint32_t m_GfxIntrReg;
uint32_t m_RspIntrReg;
void CheckInterrupts (); void CheckInterrupts ();
void DoAddressError ( bool DelaySlot, DWORD BadVaddr, bool FromRead ); void DoAddressError ( bool DelaySlot, uint32_t BadVaddr, bool FromRead );
void DoBreakException ( bool DelaySlot ); void DoBreakException ( bool DelaySlot );
void DoCopUnusableException ( bool DelaySlot, int Coprocessor ); void DoCopUnusableException ( bool DelaySlot, int32_t Coprocessor );
bool DoIntrException ( bool DelaySlot ); bool DoIntrException ( bool DelaySlot );
void DoTLBReadMiss ( bool DelaySlot, DWORD BadVaddr ); void DoTLBReadMiss ( bool DelaySlot, uint32_t BadVaddr );
void DoSysCallException ( bool DelaySlot); void DoSysCallException ( bool DelaySlot);
void FixFpuLocations (); void FixFpuLocations ();
void Reset (); void Reset ();
void SetAsCurrentSystem (); void SetAsCurrentSystem ();
private: private:
CRegisters(); // Disable default constructor CRegisters(); // Disable default constructor
CRegisters(const CRegisters&); // Disable copy constructor CRegisters(const CRegisters&); // Disable copy constructor
CRegisters& operator=(const CRegisters&); // Disable assignment CRegisters& operator=(const CRegisters&); // Disable assignment
bool m_FirstInterupt; bool m_FirstInterupt;
CN64System * m_System; CN64System * m_System;
CSystemEvents * m_SystemEvents; CSystemEvents * m_SystemEvents;
}; };

2
Source/Project64/N64 System/Recompiler/Recompiler Class.cpp
View File

@ -93,7 +93,7 @@ void CRecompiler::Run()
void CRecompiler::RecompilerMain_VirtualTable() void CRecompiler::RecompilerMain_VirtualTable()
{ {
bool & Done = m_EndEmulation; bool & Done = m_EndEmulation;
DWORD & PC = PROGRAM_COUNTER; uint32_t & PC = PROGRAM_COUNTER;
while(!Done) while(!Done)
{ {

2
Source/Project64/N64 System/Recompiler/Recompiler Class.h
View File

@ -70,5 +70,5 @@ private:
DWORD m_MemoryStack; DWORD m_MemoryStack;
//Quick access to registers //Quick access to registers
DWORD & PROGRAM_COUNTER; uint32_t & PROGRAM_COUNTER;
}; };