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[Android] Add Arm32Opcode handling for AndArmRegToArmReg

This commit is contained in:
zilmar 2016-09-29 22:03:06 +10:00
parent b15a8b1fbc
commit 17f740911c
2 changed files with 28 additions and 8 deletions
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34
Source/Project64-core/N64System/Recompiler/Arm/ArmOps.cpp
View File

@ -131,14 +131,34 @@ void CArmOps::AddConstToArmReg(ArmReg DestReg, ArmReg SourceReg, uint32_t Const)
}
}
void CArmOps::AndArmRegToArmReg(ArmReg SourceReg, ArmReg DestReg)
void CArmOps::AndArmRegToArmReg(ArmReg DestReg, ArmReg SourceReg)
{
CPU_Message(" and\t%s, %s", ArmRegName(DestReg), ArmRegName(SourceReg));
ArmThumbOpcode op = {0};
op.Reg2.rn = DestReg;
op.Reg2.rm = SourceReg;
op.Reg2.opcode = 0x100;
AddCode16(op.Hex);
if (DestReg <= 0x7 && SourceReg <= 0x7 )
{
CPU_Message(" ands\t%s, %s", ArmRegName(DestReg), ArmRegName(SourceReg));
ArmThumbOpcode op = {0};
op.Reg2.rn = DestReg;
op.Reg2.rm = SourceReg;
op.Reg2.opcode = 0x100;
AddCode16(op.Hex);
}
else
{
CPU_Message(" and.w\t%s, %s, %s", ArmRegName(DestReg), ArmRegName(DestReg), ArmRegName(SourceReg));
Arm32Opcode op = {0};
op.imm5.rn = DestReg;
op.imm5.s = 0;
op.imm5.opcode = 0x750;
op.imm5.rm = SourceReg;
op.imm5.type = 0;
op.imm5.imm2 = 0;
op.imm5.rd = DestReg;
op.imm5.imm3 = 0;
op.imm5.opcode2 = 0;
AddCode32(op.Hex);
}
}
void CArmOps::BranchLabel8(ArmBranchCompare CompareType, const char * Label)

2
Source/Project64-core/N64System/Recompiler/Arm/ArmOps.h
View File

@ -135,7 +135,7 @@ protected:
static void AddArmRegToArmReg(ArmReg DestReg, ArmReg SourceReg1, ArmReg SourceReg2);
static void AddConstToArmReg(ArmReg DestReg, uint32_t Const);
static void AddConstToArmReg(ArmReg DestReg, ArmReg SourceReg, uint32_t Const);
static void AndArmRegToArmReg(ArmReg SourceReg, ArmReg DestReg);
static void AndArmRegToArmReg(ArmReg DestReg, ArmReg SourceReg);
static void BranchLabel8(ArmBranchCompare CompareType, const char * Label);
static void BranchLabel20(ArmBranchCompare CompareType, const char * Label);
static void CallFunction(void * Function, const char * FunctionName);