ShuriZma
/
project64
mirror of https://github.com/project64/project64.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fixed some mistakes in GetInstructionInfo 

Not only were certain instructions missing, but also some were in the
wrong place or had the wrong attributes.

Also VSUB needed to be added to IsNextInstructionMmx.
This commit is contained in:
LegendOfDragoon 2015-01-31 04:35:43 -08:00
parent 15e389cbe2
commit 1741623482
1 changed files with 19 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
Source/RSP/Recompiler Analysis.c
View File

@ -102,6 +102,7 @@ BOOL IsNextInstructionMmx(DWORD PC) {
return TRUE;
case RSP_VECTOR_VADD:
case RSP_VECTOR_VSUB:
/* Requires no accumulator write! & No flags! */
if (WriteToAccum(Low16BitAccum, CompilePC) == TRUE) {
return FALSE;
@ -1421,16 +1422,25 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
break;
case RSP_VECTOR_VMULF:
case RSP_VECTOR_VMULU:
case RSP_VECTOR_VMUDL:
case RSP_VECTOR_VMUDM:
case RSP_VECTOR_VMUDN:
case RSP_VECTOR_VMUDH:
case RSP_VECTOR_VABS:
case RSP_VECTOR_VAND:
case RSP_VECTOR_VOR:
case RSP_VECTOR_VXOR:
case RSP_VECTOR_VNAND:
case RSP_VECTOR_VNOR:
case RSP_VECTOR_VNXOR:
info->DestReg = RspOp->sa;
info->SourceReg0 = RspOp->rd;
info->SourceReg1 = RspOp->rt;
info->flags = VEC_Instruction | VEC_ResetAccum | Accum_Operation;
break;
case RSP_VECTOR_VMACF:
case RSP_VECTOR_VMACU:
case RSP_VECTOR_VMADL:
case RSP_VECTOR_VMADM:
case RSP_VECTOR_VMADN:
@ -1440,23 +1450,13 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
info->SourceReg1 = RspOp->rt;
info->flags = VEC_Instruction | VEC_Accumulate | Accum_Operation;
break;
case RSP_VECTOR_VABS:
case RSP_VECTOR_VADD:
case RSP_VECTOR_VADDC:
case RSP_VECTOR_VSUB:
case RSP_VECTOR_VSUBC:
case RSP_VECTOR_VAND:
case RSP_VECTOR_VOR:
case RSP_VECTOR_VXOR:
case RSP_VECTOR_VNXOR:
case RSP_VECTOR_VCR:
case RSP_VECTOR_VCH:
case RSP_VECTOR_VCL:
case RSP_VECTOR_VRCP:
case RSP_VECTOR_VRCPL:
case RSP_VECTOR_VRCPH:
case RSP_VECTOR_VRSQL:
case RSP_VECTOR_VRSQH:
case RSP_VECTOR_VLT:
case RSP_VECTOR_VEQ:
case RSP_VECTOR_VGE:
@ -1468,19 +1468,22 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
break;
case RSP_VECTOR_VMOV:
info->flags = InvalidOpcode;
/* info->DestReg = RspOp->sa;
case RSP_VECTOR_VRCP:
case RSP_VECTOR_VRCPL:
case RSP_VECTOR_VRCPH:
case RSP_VECTOR_VRSQL:
case RSP_VECTOR_VRSQH:
info->DestReg = RspOp->sa;
info->SourceReg0 = RspOp->rt;
info->SourceReg1 = -1;
info->flags = VEC_Instruction; /* Assume reset? */
info->flags = VEC_Instruction | VEC_ResetAccum | Accum_Operation; /* Assume reset? */
break;
case RSP_VECTOR_VMRG:
info->flags = InvalidOpcode;
/* info->DestReg = RspOp->sa;
info->DestReg = RspOp->sa;
info->SourceReg0 = RspOp->rt;
info->SourceReg1 = RspOp->rd;
info->flags = VEC_Instruction; /* Assum reset? */
info->flags = VEC_Instruction | VEC_ResetAccum | Accum_Operation | Flag_Instruction; /* Assum reset? */
break;
case RSP_VECTOR_VSAW: