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Merge pull request #26 from LegendOfDragoon/master 

Improve Recompiler Analysis for Vector Destination and Accumulators
This commit is contained in:
project64 2015-01-31 18:10:04 +11:00
parent 0f58c6ccaa ab30871f57
commit 15e389cbe2
1 changed files with 22 additions and 8 deletions
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30
Source/RSP/Recompiler Analysis.c
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@ -182,6 +182,9 @@ DWORD WriteToAccum2 (int Location, int PC, BOOL RecursiveCall) {
case RSP_SPECIAL_SLTU: case RSP_SPECIAL_SLTU:
case RSP_SPECIAL_BREAK: case RSP_SPECIAL_BREAK:
break; break;
case RSP_SPECIAL_JALR:
return TRUE;
case RSP_SPECIAL_JR: case RSP_SPECIAL_JR:
Instruction_State = DO_DELAY_SLOT; Instruction_State = DO_DELAY_SLOT;
@ -242,12 +245,14 @@ DWORD WriteToAccum2 (int Location, int PC, BOOL RecursiveCall) {
if ((RspOp.rs & 0x10) != 0) { if ((RspOp.rs & 0x10) != 0) {
switch (RspOp.funct) { switch (RspOp.funct) {
case RSP_VECTOR_VMULF: case RSP_VECTOR_VMULF:
case RSP_VECTOR_VMULU:
case RSP_VECTOR_VMUDL: case RSP_VECTOR_VMUDL:
case RSP_VECTOR_VMUDM: case RSP_VECTOR_VMUDM:
case RSP_VECTOR_VMUDN: case RSP_VECTOR_VMUDN:
case RSP_VECTOR_VMUDH: case RSP_VECTOR_VMUDH:
return FALSE; return FALSE;
case RSP_VECTOR_VMACF: case RSP_VECTOR_VMACF:
case RSP_VECTOR_VMACU:
case RSP_VECTOR_VMADL: case RSP_VECTOR_VMADL:
case RSP_VECTOR_VMADM: case RSP_VECTOR_VMADM:
case RSP_VECTOR_VMADN: case RSP_VECTOR_VMADN:
@ -281,6 +286,7 @@ DWORD WriteToAccum2 (int Location, int PC, BOOL RecursiveCall) {
case RSP_VECTOR_VLT: case RSP_VECTOR_VLT:
case RSP_VECTOR_VEQ: case RSP_VECTOR_VEQ:
case RSP_VECTOR_VGE: case RSP_VECTOR_VGE:
case RSP_VECTOR_VNE:
case RSP_VECTOR_VMRG: case RSP_VECTOR_VMRG:
case RSP_VECTOR_VMOV: case RSP_VECTOR_VMOV:
if (Location == Low16BitAccum) { return FALSE; } if (Location == Low16BitAccum) { return FALSE; }
@ -289,7 +295,7 @@ DWORD WriteToAccum2 (int Location, int PC, BOOL RecursiveCall) {
case RSP_VECTOR_VSAW: case RSP_VECTOR_VSAW:
return TRUE; return TRUE;
default: default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC)); CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE; return TRUE;
} }
} else { } else {
@ -300,7 +306,7 @@ DWORD WriteToAccum2 (int Location, int PC, BOOL RecursiveCall) {
case RSP_COP2_MF: case RSP_COP2_MF:
break; break;
default: default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC)); CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
return TRUE; return TRUE;
} }
} }
@ -483,6 +489,9 @@ BOOL WriteToVectorDest2 (DWORD DestReg, int PC, BOOL RecursiveCall) {
case RSP_SPECIAL_BREAK: case RSP_SPECIAL_BREAK:
break; break;
case RSP_SPECIAL_JALR:
return TRUE;
case RSP_SPECIAL_JR: case RSP_SPECIAL_JR:
Instruction_State = DO_DELAY_SLOT; Instruction_State = DO_DELAY_SLOT;
break; break;
@ -541,11 +550,13 @@ BOOL WriteToVectorDest2 (DWORD DestReg, int PC, BOOL RecursiveCall) {
if ((RspOp.rs & 0x10) != 0) { if ((RspOp.rs & 0x10) != 0) {
switch (RspOp.funct) { switch (RspOp.funct) {
case RSP_VECTOR_VMULF: case RSP_VECTOR_VMULF:
case RSP_VECTOR_VMULU:
case RSP_VECTOR_VMUDL: case RSP_VECTOR_VMUDL:
case RSP_VECTOR_VMUDM: case RSP_VECTOR_VMUDM:
case RSP_VECTOR_VMUDN: case RSP_VECTOR_VMUDN:
case RSP_VECTOR_VMUDH: case RSP_VECTOR_VMUDH:
case RSP_VECTOR_VMACF: case RSP_VECTOR_VMACF:
case RSP_VECTOR_VMACU:
case RSP_VECTOR_VMADL: case RSP_VECTOR_VMADL:
case RSP_VECTOR_VMADM: case RSP_VECTOR_VMADM:
case RSP_VECTOR_VMADN: case RSP_VECTOR_VMADN:
@ -555,7 +566,9 @@ BOOL WriteToVectorDest2 (DWORD DestReg, int PC, BOOL RecursiveCall) {
case RSP_VECTOR_VSUB: case RSP_VECTOR_VSUB:
case RSP_VECTOR_VSUBC: case RSP_VECTOR_VSUBC:
case RSP_VECTOR_VAND: case RSP_VECTOR_VAND:
case RSP_VECTOR_VNAND:
case RSP_VECTOR_VOR: case RSP_VECTOR_VOR:
case RSP_VECTOR_VNOR:
case RSP_VECTOR_VXOR: case RSP_VECTOR_VXOR:
case RSP_VECTOR_VNXOR: case RSP_VECTOR_VNXOR:
case RSP_VECTOR_VABS: case RSP_VECTOR_VABS:
@ -565,21 +578,22 @@ BOOL WriteToVectorDest2 (DWORD DestReg, int PC, BOOL RecursiveCall) {
break; break;
case RSP_VECTOR_VMOV: case RSP_VECTOR_VMOV:
case RSP_VECTOR_VRCP:
case RSP_VECTOR_VRCPL:
case RSP_VECTOR_VRCPH:
case RSP_VECTOR_VRSQL:
case RSP_VECTOR_VRSQH:
if (DestReg == RspOp.rt) { return TRUE; } if (DestReg == RspOp.rt) { return TRUE; }
break; break;
case RSP_VECTOR_VCR:
case RSP_VECTOR_VRCP:
case RSP_VECTOR_VRCPH:
case RSP_VECTOR_VRSQH:
case RSP_VECTOR_VCH: case RSP_VECTOR_VCH:
case RSP_VECTOR_VCL: case RSP_VECTOR_VCL:
return TRUE; case RSP_VECTOR_VCR:
case RSP_VECTOR_VMRG: case RSP_VECTOR_VMRG:
case RSP_VECTOR_VLT: case RSP_VECTOR_VLT:
case RSP_VECTOR_VEQ: case RSP_VECTOR_VEQ:
case RSP_VECTOR_VGE: case RSP_VECTOR_VGE:
case RSP_VECTOR_VNE:
if (DestReg == RspOp.rd) { return TRUE; } if (DestReg == RspOp.rd) { return TRUE; }
if (DestReg == RspOp.rt) { return TRUE; } if (DestReg == RspOp.rt) { return TRUE; }
if (DestReg == RspOp.sa) { return FALSE; } if (DestReg == RspOp.sa) { return FALSE; }