ShuriZma
/
project64
mirror of https://github.com/project64/project64.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #45 from LegendOfDragoon/master 

looks fine, but only did a basic look over it, if it fixes a game great. I guess when we get to more testing if there are problems then we will see what is happening then.
This commit is contained in:
project64 2015-02-02 15:02:34 +11:00
parent 89db569322 0f1010379f
commit 0c51379af8
1 changed files with 24 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
Source/RSP/Recompiler Analysis.c
View File

@ -102,6 +102,7 @@ BOOL IsNextInstructionMmx(DWORD PC) {
return TRUE;
case RSP_VECTOR_VADD:
case RSP_VECTOR_VSUB:
/* Requires no accumulator write! & No flags! */
if (WriteToAccum(Low16BitAccum, CompilePC) == TRUE) {
return FALSE;
@ -1398,7 +1399,11 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
info->DestReg = RspOp->rt;
info->SourceReg0 = (DWORD)-1;
info->SourceReg1 = (DWORD)-1;
if (RspOp->rd == 0x4 || RspOp->rd == 0x7){
info->flags = InvalidOpcode;
} else{
info->flags = COPO_MF_Instruction | GPR_Instruction | Load_Operation;
}
break;
case RSP_COP0_MT:
@ -1421,16 +1426,25 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
break;
case RSP_VECTOR_VMULF:
case RSP_VECTOR_VMULU:
case RSP_VECTOR_VMUDL:
case RSP_VECTOR_VMUDM:
case RSP_VECTOR_VMUDN:
case RSP_VECTOR_VMUDH:
case RSP_VECTOR_VABS:
case RSP_VECTOR_VAND:
case RSP_VECTOR_VOR:
case RSP_VECTOR_VXOR:
case RSP_VECTOR_VNAND:
case RSP_VECTOR_VNOR:
case RSP_VECTOR_VNXOR:
info->DestReg = RspOp->sa;
info->SourceReg0 = RspOp->rd;
info->SourceReg1 = RspOp->rt;
info->flags = VEC_Instruction | VEC_ResetAccum | Accum_Operation;
break;
case RSP_VECTOR_VMACF:
case RSP_VECTOR_VMACU:
case RSP_VECTOR_VMADL:
case RSP_VECTOR_VMADM:
case RSP_VECTOR_VMADN:
@ -1440,23 +1454,13 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
info->SourceReg1 = RspOp->rt;
info->flags = VEC_Instruction | VEC_Accumulate | Accum_Operation;
break;
case RSP_VECTOR_VABS:
case RSP_VECTOR_VADD:
case RSP_VECTOR_VADDC:
case RSP_VECTOR_VSUB:
case RSP_VECTOR_VSUBC:
case RSP_VECTOR_VAND:
case RSP_VECTOR_VOR:
case RSP_VECTOR_VXOR:
case RSP_VECTOR_VNXOR:
case RSP_VECTOR_VCR:
case RSP_VECTOR_VCH:
case RSP_VECTOR_VCL:
case RSP_VECTOR_VRCP:
case RSP_VECTOR_VRCPL:
case RSP_VECTOR_VRCPH:
case RSP_VECTOR_VRSQL:
case RSP_VECTOR_VRSQH:
case RSP_VECTOR_VLT:
case RSP_VECTOR_VEQ:
case RSP_VECTOR_VGE:
@ -1468,19 +1472,22 @@ void GetInstructionInfo(DWORD PC, OPCODE * RspOp, OPCODE_INFO * info) {
break;
case RSP_VECTOR_VMOV:
info->flags = InvalidOpcode;
/* info->DestReg = RspOp->sa;
case RSP_VECTOR_VRCP:
case RSP_VECTOR_VRCPL:
case RSP_VECTOR_VRCPH:
case RSP_VECTOR_VRSQL:
case RSP_VECTOR_VRSQH:
info->DestReg = RspOp->sa;
info->SourceReg0 = RspOp->rt;
info->SourceReg1 = -1;
info->flags = VEC_Instruction; /* Assume reset? */
info->flags = VEC_Instruction | VEC_ResetAccum | Accum_Operation; /* Assume reset? */
break;
case RSP_VECTOR_VMRG:
info->flags = InvalidOpcode;
/* info->DestReg = RspOp->sa;
info->DestReg = RspOp->sa;
info->SourceReg0 = RspOp->rt;
info->SourceReg1 = RspOp->rd;
info->flags = VEC_Instruction; /* Assum reset? */
info->flags = VEC_Instruction | VEC_ResetAccum | Accum_Operation | Flag_Instruction; /* Assum reset? */
break;
case RSP_VECTOR_VSAW: