JALR now handles delay slot over 4k boundary
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4a52f9182c
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@ -1967,7 +1967,8 @@ void CRecompilerOps::SPECIAL_SRAV (void) {
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}
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void CRecompilerOps::SPECIAL_JR (void) {
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if ( m_NextInstruction == NORMAL ) {
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if ( m_NextInstruction == NORMAL )
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{
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CPU_Message(" %X %s",m_CompilePC,R4300iOpcodeName(m_Opcode.Hex,m_CompilePC));
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if ((m_CompilePC & 0xFFC) == 0xFFC)
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{
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@ -2048,26 +2049,28 @@ void CRecompilerOps::SPECIAL_JR (void) {
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}
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}
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void CRecompilerOps::SPECIAL_JALR (void) {
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if ( m_NextInstruction == NORMAL ) {
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void CRecompilerOps::SPECIAL_JALR (void)
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{
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if ( m_NextInstruction == NORMAL )
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{
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CPU_Message(" %X %s",m_CompilePC,R4300iOpcodeName(m_Opcode.Hex,m_CompilePC));
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if (DelaySlotEffectsCompare(m_CompilePC,m_Opcode.rs,0)) {
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if (DelaySlotEffectsCompare(m_CompilePC,m_Opcode.rs,0))
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{
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CRecompilerOps::UnknownOpcode();
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}
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UnMap_GPR( m_Opcode.rd, FALSE);
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MipsRegLo(m_Opcode.rd) = m_CompilePC + 8;
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MipsRegState(m_Opcode.rd) = CRegInfo::STATE_CONST_32;
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if ((m_CompilePC & 0xFFC) == 0xFFC) {
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_Notify->BreakPoint(__FILE__,__LINE__);
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#ifdef tofix
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if ((m_CompilePC & 0xFFC) == 0xFFC)
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{
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if (IsMapped(m_Opcode.rs)) {
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Push(cMipsRegMapLo(m_Opcode.rs));
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MoveX86regToVariable(cMipsRegMapLo(m_Opcode.rs),&R4300iOp::m_JumpToLocation,"R4300iOp::m_JumpToLocation");
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m_RegWorkingSet.WriteBackRegisters();
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} else {
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Push(Map_TempReg(x86_Any,m_Opcode.rs,FALSE));
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m_RegWorkingSet.WriteBackRegisters();
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MoveX86regToVariable(Map_TempReg(x86_Any,m_Opcode.rs,FALSE),&R4300iOp::m_JumpToLocation,"R4300iOp::m_JumpToLocation");
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}
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m_Section->GenerateSectionLinkage();
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m_NextInstruction = END_BLOCK;
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#endif
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OverflowDelaySlot(true);
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return;
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}
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m_NextInstruction = DO_DELAY_SLOT;
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