From 00a978ca1b3d2bd6db28edb310ed40389888edc8 Mon Sep 17 00:00:00 2001 From: zilmar Date: Fri, 31 Jan 2025 06:18:36 +1030 Subject: [PATCH] Core: add edge condition test to DDIV in interpter --- .../N64System/Interpreter/InterpreterOps.cpp | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/Source/Project64-core/N64System/Interpreter/InterpreterOps.cpp b/Source/Project64-core/N64System/Interpreter/InterpreterOps.cpp index ffe5d940b..ceaf83ad6 100644 --- a/Source/Project64-core/N64System/Interpreter/InterpreterOps.cpp +++ b/Source/Project64-core/N64System/Interpreter/InterpreterOps.cpp @@ -1900,10 +1900,19 @@ void R4300iOp::SPECIAL_DMULTU() void R4300iOp::SPECIAL_DDIV() { + if (m_GPR[m_Opcode.rt].UDW != 0) { - m_RegLO.DW = m_GPR[m_Opcode.rs].DW / m_GPR[m_Opcode.rt].DW; - m_RegHI.DW = m_GPR[m_Opcode.rs].DW % m_GPR[m_Opcode.rt].DW; + if (m_GPR[m_Opcode.rs].DW != 0x8000000000000000) + { + m_RegLO.DW = m_GPR[m_Opcode.rs].DW / m_GPR[m_Opcode.rt].DW; + m_RegHI.DW = m_GPR[m_Opcode.rs].DW % m_GPR[m_Opcode.rt].DW; + } + else + { + m_RegLO.DW = m_GPR[m_Opcode.rs].DW; + m_RegHI.DW = 0; + } } else {