diff --git a/Source/RSP/Cpu.c b/Source/RSP/Cpu.c
index 7d8bb7722..5d09ce355 100644
--- a/Source/RSP/Cpu.c
+++ b/Source/RSP/Cpu.c
@@ -41,7 +41,7 @@
 
 UDWORD EleSpec[32], Indx[32];
 OPCODE RSPOpC;
-DWORD *PrgCount, NextInstruction, RSP_Running;
+DWORD *PrgCount, NextInstruction, RSP_Running, RSP_MfStatusCount;
 
 void * RSP_Opcode[64];
 void * RSP_RegImm[32];
@@ -244,6 +244,7 @@ __declspec(dllexport) DWORD DoRspCycles ( DWORD Cycles ) {
 	{
 		Enter_RSP_Commands_Window();
 	}
+	RSP_MfStatusCount = 0;
 
 	switch (CPUCore) {
 	case RecompilerCPU:
diff --git a/Source/RSP/Interpreter CPU.h b/Source/RSP/Interpreter CPU.h
index 7430dfa48..520a70ec1 100644
--- a/Source/RSP/Interpreter CPU.h	
+++ b/Source/RSP/Interpreter CPU.h	
@@ -28,7 +28,7 @@
 #define DELAY_SLOT 		1
 #define JUMP	 		2
 
-extern DWORD RSP_NextInstruction, RSP_JumpTo;
+extern DWORD RSP_NextInstruction, RSP_JumpTo, RSP_MfStatusCount;
 
 void BuildInterpreterCPU(void);
 DWORD RunInterpreterCPU(DWORD Cycles);
\ No newline at end of file
diff --git a/Source/RSP/Interpreter Ops.c b/Source/RSP/Interpreter Ops.c
index e9a8d81d8..fb7a6a429 100644
--- a/Source/RSP/Interpreter Ops.c	
+++ b/Source/RSP/Interpreter Ops.c	
@@ -378,7 +378,14 @@ void RSP_Cop0_MF (void) {
 	switch (RSPOpC.rd) {
 	case 0: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.SP_MEM_ADDR_REG; break;
 	case 1: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.SP_DRAM_ADDR_REG; break;
-	case 4: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.SP_STATUS_REG; break;
+	case 4: 
+		RSP_MfStatusCount += 1;
+		RSP_GPR[RSPOpC.rt].UW = *RSPInfo.SP_STATUS_REG; 
+		if (RSP_MfStatusCount > 10)
+		{
+			RSP_Running = FALSE;
+		}
+		break;
 	case 5: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.SP_DMA_FULL_REG; break;
 	case 6: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.SP_DMA_BUSY_REG; break;
 	case 7: 
@@ -417,7 +424,12 @@ void RSP_Cop0_MT (void) {
 		if ( ( RSP_GPR[RSPOpC.rt].W & SP_SET_HALT ) != 0) { *RSPInfo.SP_STATUS_REG |= SP_STATUS_HALT;  }
 		if ( ( RSP_GPR[RSPOpC.rt].W & SP_CLR_BROKE ) != 0) { *RSPInfo.SP_STATUS_REG &= ~SP_STATUS_BROKE; }
 		if ( ( RSP_GPR[RSPOpC.rt].W & SP_CLR_INTR ) != 0) { *RSPInfo.MI_INTR_REG &= ~R4300i_SP_Intr; }
-		if ( ( RSP_GPR[RSPOpC.rt].W & SP_SET_INTR ) != 0) { DisplayError("SP_SET_INTR");  }
+		if ( ( RSP_GPR[RSPOpC.rt].W & SP_SET_INTR ) != 0) 
+		{
+			*RSPInfo.MI_INTR_REG |= R4300i_SP_Intr;
+			RSPInfo.CheckInterrupts();
+			RSP_Running = FALSE;
+		}
 		if ( ( RSP_GPR[RSPOpC.rt].W & SP_CLR_SSTEP ) != 0) { *RSPInfo.SP_STATUS_REG &= ~SP_STATUS_SSTEP; }
 		if ( ( RSP_GPR[RSPOpC.rt].W & SP_SET_SSTEP ) != 0) { *RSPInfo.SP_STATUS_REG |= SP_STATUS_SSTEP;  }
 		if ( ( RSP_GPR[RSPOpC.rt].W & SP_CLR_INTR_BREAK ) != 0) { *RSPInfo.SP_STATUS_REG &= ~SP_STATUS_INTR_BREAK; }