811 lines
21 KiB
C++
811 lines
21 KiB
C++
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/****************************************************************************
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* *
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* Project64 - A Nintendo 64 emulator. *
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* http://www.pj64-emu.com/ *
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* Copyright (C) 2012 Project64. All rights reserved. *
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* *
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* License: *
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* GNU/GPLv2 http://www.gnu.org/licenses/gpl-2.0.html *
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* *
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****************************************************************************/
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#include "stdafx.h"
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#include "GBCart.h"
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#include <Project64-core/N64System/SystemGlobals.h>
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//--------------------------------------------------------------------------------------
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bool read_from_file(const char *filename, void *data, size_t size)
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{
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FILE *f = fopen(filename, "rb");
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if (f == NULL)
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{
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return false;
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}
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if (fread(data, 1, size, f) != size)
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{
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fclose(f);
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return false;
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}
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fclose(f);
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return true;
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}
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bool load_file(const char* filename, void** buffer, size_t* size)
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{
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FILE* fd;
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size_t l_size;
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void* l_buffer;
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int err;
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bool ret;
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/* open file */
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ret = false;
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fd = fopen(filename, "rb");
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if (fd == NULL)
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{
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return false;
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}
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/* obtain file size */
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ret = false;
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err = fseek(fd, 0, SEEK_END);
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if (err != 0)
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{
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goto close_file;
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}
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err = ftell(fd);
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if (err == -1)
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{
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goto close_file;
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}
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l_size = (size_t)err;
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err = fseek(fd, 0, SEEK_SET);
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if (err != 0)
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{
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goto close_file;
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}
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/* allocate buffer */
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l_buffer = malloc(l_size);
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if (l_buffer == NULL)
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{
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goto close_file;
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}
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/* copy file content to buffer */
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ret = false;
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err = fread(l_buffer, 1, l_size, fd);
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if (err != l_size)
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{
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free(l_buffer);
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goto close_file;
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}
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/* commit buffer,size */
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ret = true;
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*buffer = l_buffer;
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*size = l_size;
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/* close file */
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close_file:
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fclose(fd);
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return ret;
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}
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//--------------------------------------------------------------------------------------
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static void read_gb_cart_normal(struct gb_cart* gb_cart, uint16_t address, uint8_t* data)
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{
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uint16_t offset;
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if ((address >= 0x0000) && (address <= 0x7FFF))
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{
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//Read GB Cart
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if (address >= gb_cart->rom_size)
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{
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//If address is larger then our rome size, bail out
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return;
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}
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memcpy(data, &gb_cart->rom[address], 0x20);
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}
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else if ((address >= 0xA000) && (address <= 0xBFFF))
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{
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//Read from RAM
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if (gb_cart->ram == NULL)
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{
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//No RAM to write to
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return;
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}
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offset = address - 0xA000;
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if (offset >= gb_cart->ram_size)
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{
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//Offset is larger then our ram size
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return;
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}
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memcpy(&gb_cart->ram[offset], data, 0x20);
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memcpy(data, &gb_cart->ram[offset], 0x20);
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}
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}
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static void write_gb_cart_normal(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data)
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{
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uint16_t offset;
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if ((address >= 0xA000) && (address <= 0xBFFF))
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{
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//Write to RAM
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if (gb_cart->ram == NULL)
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{
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//No RAM to write to
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return;
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}
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offset = address - 0xa000;
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if (offset >= gb_cart->ram_size)
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{
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//Offset is larger then our ram size
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return;
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}
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memcpy(&gb_cart->ram[offset], data, 0x20);
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}
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}
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static void read_gb_cart_mbc1(struct gb_cart* gb_cart, uint16_t address, uint8_t* data)
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{
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size_t offset;
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if ((address >= 0x0000) && (address <= 0x3FFF)) //No nbanked memory
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{
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memcpy(data, &gb_cart->rom[address], 0x20);
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}
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else if ((address >= 0x4000) && (address <= 0x7FFF)) //Read from ROM
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{
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offset = (address - 0x4000) + (gb_cart->rom_bank * 0x4000);
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if (offset < gb_cart->rom_size)
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{
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memcpy(data, &gb_cart->rom[offset], 0x20);
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}
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}
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else if ((address >= 0xA000) && (address <= 0xBFFF)) //Read from RAM
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{
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if (gb_cart->ram != NULL)
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{
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offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000);
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if (offset < gb_cart->ram_size)
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{
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memcpy(data, &gb_cart->ram[offset], 0x20);
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}
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}
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}
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}
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static void write_gb_cart_mbc1(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data)
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{
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size_t offset;
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if ((address >= 0x0000) && (address <= 0x1FFF)) // RAM enable
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{
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//Enable/disable RAM
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gb_cart->ram_enabled = (data[0] & 0x0F) == 0x0A;
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}
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else if ((address >= 0x2000) && (address <= 0x3FFF)) // ROM bank select
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{
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gb_cart->rom_bank &= 0x60; // keep MSB
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gb_cart->rom_bank |= data[0] & 0x1F;
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// emulate quirk: 0x00 -> 0x01, 0x20 -> 0x21, 0x40->0x41, 0x60 -> 0x61
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if ((gb_cart->rom_bank & 0x1F) == 0)
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{
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gb_cart->rom_bank |= 0x01;
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}
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}
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else if ((address >= 0x4000) && (address <= 0x5FFF)) // RAM bank select
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{
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if (gb_cart->ram_bank_mode)
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{
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gb_cart->ram_bank = data[0] & 0x03;
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}
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else
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{
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gb_cart->rom_bank &= 0x1F;
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gb_cart->rom_bank |= ((data[0] & 0x03) << 5); // set bits 5 and 6 of ROM bank
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}
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}
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else if ((address >= 0x6000) && (address <= 0x7FFF)) // MBC1 mode select
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{
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// this is overly complicated, but it keeps us from having to do bitwise math later
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// Basically we shuffle the 2 "magic bits" between rom_bank and ram_bank as necessary.
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if (gb_cart->ram_bank_mode != (data[0] & 0x01))
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{
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// we should only alter the ROM and RAM bank numbers if we have changed modes
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gb_cart->ram_bank_mode = data[0] & 0x01;
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if (gb_cart->ram_bank_mode)
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{
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gb_cart->ram_bank = gb_cart->rom_bank >> 5; // set the ram bank to the "magic bits"
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gb_cart->rom_bank &= 0x1F; // zero out bits 5 and 6 to keep consistency
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}
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else
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{
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gb_cart->rom_bank &= 0x1F;
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gb_cart->rom_bank |= (gb_cart->ram_bank << 5);
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gb_cart->ram_bank = 0x00; // we can only reach RAM page 0
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}
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}
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}
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else if ((address >= 0xA000) && (address <= 0xBFFF)) // Write to RAM
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{
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if (gb_cart->ram != NULL)
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{
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offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000);
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if (offset < gb_cart->ram_size)
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{
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memcpy(&gb_cart->ram[offset], data, 0x20);
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}
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}
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}
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}
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static void read_gb_cart_mbc2(struct gb_cart* gb_cart, uint16_t address, uint8_t* data)
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{
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size_t offset;
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if ((address < 0x4000)) //Rom Bank 0
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{
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memcpy(data, &gb_cart->rom[address], 0x20);
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}
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else if ((address >= 0x4000) && (address < 0x8000)) //Switchable Rom Bank
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{
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offset = (address - 0x4000) + (gb_cart->rom_bank * 0x4000);
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if (offset < gb_cart->rom_size)
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{
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memcpy(data, &gb_cart->rom[offset], 0x20);
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}
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}
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else if ((address >= 0xA000) && (address <= 0xC000)) //Upper Bounds of memory map
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{
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if (gb_cart->ram != NULL)
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{
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offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000);
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if (offset < gb_cart->ram_size)
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{
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memcpy(data, &gb_cart->ram[offset], 0x20);
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}
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}
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}
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}
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static void write_gb_cart_mbc2(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data)
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{
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size_t offset;
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if ((address >= 0x0000) && (address <= 0x1FFF)) // We shouldn't be able to read/write to RAM unless this is toggled on
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{
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gb_cart->ram_enabled = (data[0] & 0x0F) == 0x0A;
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}
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else if ((address >= 0x2000) && (address <= 0x3FFF)) // ROM bank select
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{
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gb_cart->rom_bank = data[0] & 0x0F;
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if (gb_cart->rom_bank == 0)
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{
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gb_cart->rom_bank = 1;
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}
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}
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else if ((address >= 0x4000) && (address <= 0x5FFF)) // RAM bank select
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{
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if (gb_cart->ram != NULL)
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{
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gb_cart->ram_bank = data[0] & 0x07;
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}
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}
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else if ((address >= 0xA000) && (address <= 0xBFFF)) // Write to RAM
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{
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if (gb_cart->ram != NULL)
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{
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offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000);
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if (offset < gb_cart->ram_size)
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{
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memcpy(&gb_cart->ram[offset], data, 0x20);
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}
|
||
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}
|
||
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}
|
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}
|
||
|
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|
||
|
|
|
||
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static void read_gb_cart_mbc3(struct gb_cart* gb_cart, uint16_t address, uint8_t* data)
|
||
|
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{
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||
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size_t offset;
|
||
|
|
|
||
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if ((address < 0x4000)) //Rom Bank 0
|
||
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{
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memcpy(data, &gb_cart->rom[address], 0x20);
|
||
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}
|
||
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else if ((address >= 0x4000) && (address < 0x8000)) //Switchable Rom Bank
|
||
|
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{
|
||
|
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offset = (address - 0x4000) + (gb_cart->rom_bank * 0x4000);
|
||
|
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if (offset < gb_cart->rom_size)
|
||
|
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{
|
||
|
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memcpy(data, &gb_cart->rom[offset], 0x20);
|
||
|
|
}
|
||
|
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else
|
||
|
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{
|
||
|
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memset(data, 0x00, 0x20);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else if ((address >= 0xA000) && (address <= 0xC000)) //Upper Bounds of memory map
|
||
|
|
{
|
||
|
|
if (gb_cart->ram != NULL)
|
||
|
|
{
|
||
|
|
if (gb_cart->has_rtc && (gb_cart->ram_bank >= 0x08 && gb_cart->ram_bank <= 0x0c))
|
||
|
|
{
|
||
|
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/* XXX: implement RTC read */
|
||
|
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memset(data, 0, 0x20);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000);
|
||
|
|
if (offset < gb_cart->ram_size)
|
||
|
|
{
|
||
|
|
memcpy(data, &gb_cart->ram[offset], 0x20);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void write_gb_cart_mbc3(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data)
|
||
|
|
{
|
||
|
|
uint8_t bank;
|
||
|
|
size_t offset;
|
||
|
|
|
||
|
|
if ((address >= 0x0000) && (address <= 0x1FFF)) // We shouldn't be able to read/write to RAM unless this is toggled on
|
||
|
|
{
|
||
|
|
//Enable / Disable RAM -- NOT WORKING -- FIXME
|
||
|
|
gb_cart->ram_enabled = (data[0] & 0x0F) == 0x0A;
|
||
|
|
}
|
||
|
|
else if ((address >= 0x2000) && (address <= 0x3FFF)) // ROM bank select
|
||
|
|
{
|
||
|
|
bank = data[0] & 0x7f;
|
||
|
|
gb_cart->rom_bank = (bank == 0) ? 1 : bank;
|
||
|
|
}
|
||
|
|
else if ((address >= 0x4000) && (address <= 0x5FFF)) // RAM/Clock bank select
|
||
|
|
{
|
||
|
|
if (gb_cart->ram != NULL)
|
||
|
|
{
|
||
|
|
bank = data[0];
|
||
|
|
if (gb_cart->has_rtc && (bank >= 0x8 && bank <= 0xc))
|
||
|
|
{
|
||
|
|
//Set the bank for the timer
|
||
|
|
gb_cart->ram_bank = bank;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
gb_cart->ram_bank = bank & 0x03;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else if ((address >= 0x6000) && (address <= 0x7FFF)) // Latch timer data
|
||
|
|
{
|
||
|
|
//Implement RTC timer / latch
|
||
|
|
}
|
||
|
|
else if ((address >= 0xA000) && (address <= 0xBFFF)) // Write to RAM
|
||
|
|
{
|
||
|
|
if (gb_cart->ram != NULL)
|
||
|
|
{
|
||
|
|
if (gb_cart->has_rtc && (gb_cart->ram_bank >= 0x8 && gb_cart->ram_bank <= 0xC))
|
||
|
|
{
|
||
|
|
/* XXX: implement RTC write */
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000);
|
||
|
|
if (offset < gb_cart->ram_size)
|
||
|
|
{
|
||
|
|
memcpy(&gb_cart->ram[offset], data, 0x20);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void read_gb_cart_mbc4(struct gb_cart* gb_cart, uint16_t address, uint8_t* data)
|
||
|
|
{
|
||
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void write_gb_cart_mbc4(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data)
|
||
|
|
{
|
||
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void read_gb_cart_mbc5(struct gb_cart* gb_cart, uint16_t address, uint8_t* data)
|
||
|
|
{
|
||
|
|
size_t offset;
|
||
|
|
|
||
|
|
if ((address < 0x4000)) //Rom Bank 0
|
||
|
|
{
|
||
|
|
memcpy(data, &gb_cart->rom[address], 0x20);
|
||
|
|
}
|
||
|
|
else if ((address >= 0x4000) && (address < 0x8000)) //Switchable ROM BANK
|
||
|
|
{
|
||
|
|
offset = (address - 0x4000) + (gb_cart->rom_bank * 0x4000);
|
||
|
|
if (offset < gb_cart->rom_size)
|
||
|
|
{
|
||
|
|
memcpy(data, &gb_cart->rom[offset], 0x20);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else if ((address >= 0xA000) && (address <= 0xC000)) //Upper bounds of memory map
|
||
|
|
{
|
||
|
|
if (gb_cart->ram != NULL)
|
||
|
|
{
|
||
|
|
offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000);
|
||
|
|
if (offset < gb_cart->ram_size)
|
||
|
|
{
|
||
|
|
memcpy(data, &gb_cart->ram[offset], 0x20);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void write_gb_cart_mbc5(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data)
|
||
|
|
{
|
||
|
|
size_t offset;
|
||
|
|
|
||
|
|
if ((address >= 0x0000) && (address <= 0x1FFF)) // We shouldn't be able to read/write to RAM unless this is toggled on
|
||
|
|
{
|
||
|
|
//Enable / Disable RAM -- NOT WORKING -- CHECK ME
|
||
|
|
gb_cart->ram_enabled = (data[0] & 0x0F) == 0x0A;
|
||
|
|
}
|
||
|
|
else if ((address >= 0x2000) && (address <= 0x2FFF)) // ROM bank select, low bits
|
||
|
|
{
|
||
|
|
gb_cart->rom_bank &= 0xff00;
|
||
|
|
gb_cart->rom_bank |= data[0];
|
||
|
|
}
|
||
|
|
else if ((address >= 0x3000) && (address <= 0x3FFF)) // ROM bank select, high bit
|
||
|
|
{
|
||
|
|
gb_cart->rom_bank &= 0x00ff;
|
||
|
|
gb_cart->rom_bank |= (data[0] & 0x01) << 8;
|
||
|
|
}
|
||
|
|
else if ((address >= 0x4000) && (address <= 0x5FFF)) // RAM bank select
|
||
|
|
{
|
||
|
|
if (gb_cart->ram != NULL)
|
||
|
|
{
|
||
|
|
gb_cart->ram_bank = data[0] & 0x0f;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else if ((address >= 0xA000) && (address <= 0xBFFF)) // Write to RAM
|
||
|
|
{
|
||
|
|
if (gb_cart->ram != NULL)
|
||
|
|
{
|
||
|
|
offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000);
|
||
|
|
if (offset < gb_cart->ram_size)
|
||
|
|
{
|
||
|
|
memcpy(&gb_cart->ram[offset], data, 0x20);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
static void read_gb_cart_mmm01(struct gb_cart* gb_cart, uint16_t address, uint8_t* data)
|
||
|
|
{
|
||
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void write_gb_cart_mmm01(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data)
|
||
|
|
{
|
||
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void read_gb_cart_pocket_cam(struct gb_cart* gb_cart, uint16_t address, uint8_t* data)
|
||
|
|
{
|
||
|
|
size_t offset;
|
||
|
|
|
||
|
|
if ((address < 0x4000)) //Rom Bank 0
|
||
|
|
{
|
||
|
|
memcpy(data, &gb_cart->rom[address], 0x20);
|
||
|
|
}
|
||
|
|
else if ((address >= 0x4000) && (address < 0x8000)) //Switchable ROM BANK
|
||
|
|
{
|
||
|
|
offset = (address - 0x4000) + (gb_cart->rom_bank * 0x4000);
|
||
|
|
if (offset < gb_cart->rom_size)
|
||
|
|
{
|
||
|
|
memcpy(data, &gb_cart->rom[offset], 0x20);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else if ((address >= 0xA000) && (address <= 0xC000)) //Upper bounds of memory map
|
||
|
|
{
|
||
|
|
//Check to see if where currently in register mode
|
||
|
|
if (gb_cart->ram != NULL)
|
||
|
|
{
|
||
|
|
if (gb_cart->ram_bank & 0x10)
|
||
|
|
{
|
||
|
|
//Where in register mode, based off NRAGE we just fill the memory with Zeroes.
|
||
|
|
//Seems to be incorrect behaviour but need to find more doccumentation
|
||
|
|
memset(data, 0x00, 0x20);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
//Read RAM normally
|
||
|
|
offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000);
|
||
|
|
if (offset < gb_cart->ram_size)
|
||
|
|
{
|
||
|
|
memcpy(data, &gb_cart->ram[offset], 0x20);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void write_gb_cart_pocket_cam(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data)
|
||
|
|
{
|
||
|
|
size_t offset;
|
||
|
|
|
||
|
|
if ((address >= 0x0000) && (address <= 0x1FFF)) // We shouldn't be able to read/write to RAM unless this is toggled on
|
||
|
|
{
|
||
|
|
//Enable / Disable RAM
|
||
|
|
gb_cart->ram_enabled = (data[0] & 0x0F) == 0x0A;
|
||
|
|
}
|
||
|
|
else if ((address >= 0x2000) && (address <= 0x2FFF)) // ROM bank select, low bits
|
||
|
|
{
|
||
|
|
gb_cart->rom_bank &= 0xFF00;
|
||
|
|
gb_cart->rom_bank |= data[0];
|
||
|
|
}
|
||
|
|
else if ((address >= 0x4000) && (address <= 0x4FFF)) // Camera Register & RAM bank select
|
||
|
|
{
|
||
|
|
if (gb_cart->ram != NULL)
|
||
|
|
{
|
||
|
|
if (data[0] & 0x10)
|
||
|
|
{
|
||
|
|
//REGISTER MODE
|
||
|
|
gb_cart->ram_bank = data[0];
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
//RAM MODE
|
||
|
|
gb_cart->ram_bank = data[0] & 0x0F;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else if ((address >= 0xA000) && (address <= 0xBFFF)) // Write to RAM
|
||
|
|
{
|
||
|
|
if (gb_cart->ram != NULL)
|
||
|
|
{
|
||
|
|
if (gb_cart->ram_bank & 0x10)
|
||
|
|
{
|
||
|
|
//REGISTER MODE (DO NOTHING)
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
//RAM MODE
|
||
|
|
offset = (address - 0xA000) + (gb_cart->ram_bank * 0x2000);
|
||
|
|
if (offset < gb_cart->ram_size)
|
||
|
|
{
|
||
|
|
memcpy(&gb_cart->ram[offset], data, 0x20);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void read_gb_cart_bandai_tama5(struct gb_cart* gb_cart, uint16_t address, uint8_t* data)
|
||
|
|
{
|
||
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void write_gb_cart_bandai_tama5(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data)
|
||
|
|
{
|
||
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void read_gb_cart_huc1(struct gb_cart* gb_cart, uint16_t address, uint8_t* data)
|
||
|
|
{
|
||
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void write_gb_cart_huc1(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data)
|
||
|
|
{
|
||
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void read_gb_cart_huc3(struct gb_cart* gb_cart, uint16_t address, uint8_t* data)
|
||
|
|
{
|
||
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void write_gb_cart_huc3(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data)
|
||
|
|
{
|
||
|
|
g_Notify->BreakPoint(__FILE__, __LINE__);
|
||
|
|
}
|
||
|
|
|
||
|
|
enum gbcart_extra_devices
|
||
|
|
{
|
||
|
|
GED_NONE = 0x00,
|
||
|
|
GED_RAM = 0x01,
|
||
|
|
GED_BATTERY = 0x02,
|
||
|
|
GED_RTC = 0x04,
|
||
|
|
GED_RUMBLE = 0x08
|
||
|
|
};
|
||
|
|
|
||
|
|
struct parsed_cart_type
|
||
|
|
{
|
||
|
|
void(*read_gb_cart)(struct gb_cart*, uint16_t, uint8_t*);
|
||
|
|
void(*write_gb_cart)(struct gb_cart*, uint16_t, const uint8_t*);
|
||
|
|
unsigned int extra_devices;
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct parsed_cart_type* parse_cart_type(uint8_t cart_type)
|
||
|
|
{
|
||
|
|
#define MBC(x) read_gb_cart_ ## x, write_gb_cart_ ## x
|
||
|
|
static const struct parsed_cart_type GB_CART_TYPES[] =
|
||
|
|
{
|
||
|
|
{ MBC(normal), GED_NONE },
|
||
|
|
{ MBC(mbc1), GED_NONE },
|
||
|
|
{ MBC(mbc1), GED_RAM },
|
||
|
|
{ MBC(mbc1), GED_RAM | GED_BATTERY },
|
||
|
|
{ MBC(mbc2), GED_NONE },
|
||
|
|
{ MBC(mbc2), GED_BATTERY },
|
||
|
|
{ MBC(normal), GED_RAM },
|
||
|
|
{ MBC(normal), GED_RAM | GED_BATTERY },
|
||
|
|
{ MBC(mmm01), GED_NONE },
|
||
|
|
{ MBC(mmm01), GED_RAM },
|
||
|
|
{ MBC(mmm01), GED_RAM | GED_BATTERY },
|
||
|
|
{ MBC(mbc3), GED_BATTERY | GED_RTC },
|
||
|
|
{ MBC(mbc3), GED_RAM | GED_BATTERY | GED_RTC },
|
||
|
|
{ MBC(mbc3), GED_NONE },
|
||
|
|
{ MBC(mbc3), GED_RAM },
|
||
|
|
{ MBC(mbc3), GED_RAM | GED_BATTERY },
|
||
|
|
{ MBC(mbc4), GED_NONE },
|
||
|
|
{ MBC(mbc4), GED_RAM },
|
||
|
|
{ MBC(mbc4), GED_RAM | GED_BATTERY },
|
||
|
|
{ MBC(mbc5), GED_NONE },
|
||
|
|
{ MBC(mbc5), GED_RAM },
|
||
|
|
{ MBC(mbc5), GED_RAM | GED_BATTERY },
|
||
|
|
{ MBC(mbc5), GED_RUMBLE },
|
||
|
|
{ MBC(mbc5), GED_RAM | GED_RUMBLE },
|
||
|
|
{ MBC(mbc5), GED_RAM | GED_BATTERY | GED_RUMBLE },
|
||
|
|
{ MBC(pocket_cam), GED_NONE },
|
||
|
|
{ MBC(bandai_tama5), GED_NONE },
|
||
|
|
{ MBC(huc3), GED_NONE },
|
||
|
|
{ MBC(huc1), GED_RAM | GED_BATTERY }
|
||
|
|
};
|
||
|
|
#undef MBC
|
||
|
|
|
||
|
|
|
||
|
|
switch (cart_type)
|
||
|
|
{
|
||
|
|
case 0x00: return &GB_CART_TYPES[0];
|
||
|
|
case 0x01: return &GB_CART_TYPES[1];
|
||
|
|
case 0x02: return &GB_CART_TYPES[2];
|
||
|
|
case 0x03: return &GB_CART_TYPES[3];
|
||
|
|
case 0x05: return &GB_CART_TYPES[4];
|
||
|
|
case 0x06: return &GB_CART_TYPES[5];
|
||
|
|
case 0x08: return &GB_CART_TYPES[6];
|
||
|
|
case 0x09: return &GB_CART_TYPES[7];
|
||
|
|
case 0x0b: return &GB_CART_TYPES[8];
|
||
|
|
case 0x0c: return &GB_CART_TYPES[9];
|
||
|
|
case 0x0d: return &GB_CART_TYPES[10];
|
||
|
|
case 0x0f: return &GB_CART_TYPES[11];
|
||
|
|
case 0x10: return &GB_CART_TYPES[12];
|
||
|
|
case 0x11: return &GB_CART_TYPES[13];
|
||
|
|
case 0x12: return &GB_CART_TYPES[14];
|
||
|
|
case 0x13: return &GB_CART_TYPES[15];
|
||
|
|
case 0x15: return &GB_CART_TYPES[16];
|
||
|
|
case 0x16: return &GB_CART_TYPES[17];
|
||
|
|
case 0x17: return &GB_CART_TYPES[18];
|
||
|
|
case 0x19: return &GB_CART_TYPES[19];
|
||
|
|
case 0x1a: return &GB_CART_TYPES[20];
|
||
|
|
case 0x1b: return &GB_CART_TYPES[21];
|
||
|
|
case 0x1c: return &GB_CART_TYPES[22];
|
||
|
|
case 0x1d: return &GB_CART_TYPES[23];
|
||
|
|
case 0x1e: return &GB_CART_TYPES[24];
|
||
|
|
case 0xfc: return &GB_CART_TYPES[25];
|
||
|
|
case 0xfd: return &GB_CART_TYPES[26];
|
||
|
|
case 0xfe: return &GB_CART_TYPES[27];
|
||
|
|
case 0xff: return &GB_CART_TYPES[28];
|
||
|
|
default: return NULL;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
int GBCart::init_gb_cart(struct gb_cart* gb_cart, const char* gb_file)
|
||
|
|
{
|
||
|
|
int err;
|
||
|
|
const struct parsed_cart_type* type;
|
||
|
|
uint8_t* rom = NULL;
|
||
|
|
size_t rom_size = 0;
|
||
|
|
uint8_t* ram = NULL;
|
||
|
|
size_t ram_size = 0;
|
||
|
|
|
||
|
|
/* load GB cart ROM */
|
||
|
|
err = load_file(gb_file, (void**)&rom, &rom_size);
|
||
|
|
if (err == 0)
|
||
|
|
{
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (rom_size < 0x8000)
|
||
|
|
{
|
||
|
|
err = 0;
|
||
|
|
goto free_rom;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* get and parse cart type */
|
||
|
|
uint8_t cart_type = rom[0x147];
|
||
|
|
type = parse_cart_type(cart_type);
|
||
|
|
if (type == NULL)
|
||
|
|
{
|
||
|
|
err = 0;
|
||
|
|
goto free_rom;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* load ram (if present) */
|
||
|
|
if (type->extra_devices & GED_RAM)
|
||
|
|
{
|
||
|
|
ram_size = 0;
|
||
|
|
switch (rom[0x149])
|
||
|
|
{
|
||
|
|
case 0x01: ram_size = 1 * 0x800; break;
|
||
|
|
case 0x02: ram_size = 4 * 0x800; break;
|
||
|
|
case 0x03: ram_size = 16 * 0x800; break;
|
||
|
|
case 0x04: ram_size = 64 * 0x800; break;
|
||
|
|
case 0x05: ram_size = 32 * 0x800; break;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (ram_size != 0)
|
||
|
|
{
|
||
|
|
ram = (uint8_t*)malloc(ram_size);
|
||
|
|
if (ram == NULL)
|
||
|
|
{
|
||
|
|
err = 0;
|
||
|
|
goto free_rom;
|
||
|
|
}
|
||
|
|
|
||
|
|
read_from_file("C:/Users/death/Desktop/pkmgb.sav", ram, ram_size);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* update gb_cart */
|
||
|
|
gb_cart->ram = ram;
|
||
|
|
gb_cart->rom = rom;
|
||
|
|
gb_cart->rom_size = rom_size;
|
||
|
|
gb_cart->ram_size = ram_size;
|
||
|
|
gb_cart->rom_bank = 1;
|
||
|
|
gb_cart->ram_bank = 0;
|
||
|
|
gb_cart->has_rtc = (type->extra_devices & GED_RTC) ? 1 : 0;
|
||
|
|
gb_cart->read_gb_cart = type->read_gb_cart;
|
||
|
|
gb_cart->write_gb_cart = type->write_gb_cart;
|
||
|
|
return 1;
|
||
|
|
|
||
|
|
free_rom:
|
||
|
|
free(rom);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
void GBCart::release_gb_cart(struct gb_cart* gb_cart)
|
||
|
|
{
|
||
|
|
if (gb_cart->rom != NULL)
|
||
|
|
free(gb_cart->rom);
|
||
|
|
|
||
|
|
if (gb_cart->ram != NULL)
|
||
|
|
free(gb_cart->ram);
|
||
|
|
|
||
|
|
memset(gb_cart, 0, sizeof(*gb_cart));
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
void GBCart::read_gb_cart(struct gb_cart* gb_cart, uint16_t address, uint8_t* data)
|
||
|
|
{
|
||
|
|
gb_cart->read_gb_cart(gb_cart, address, data);
|
||
|
|
}
|
||
|
|
|
||
|
|
void GBCart::write_gb_cart(struct gb_cart* gb_cart, uint16_t address, const uint8_t* data)
|
||
|
|
{
|
||
|
|
gb_cart->write_gb_cart(gb_cart, address, data);
|
||
|
|
}
|