2016-02-11 08:33:11 +00:00
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#include "Types.h"
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2016-01-27 09:11:59 +00:00
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#define SP_STATUS_HALT 0x001 /* Bit 0: halt */
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#define SP_STATUS_BROKE 0x002 /* Bit 1: broke */
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#define SP_STATUS_DMA_BUSY 0x004 /* Bit 2: dma busy */
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#define SP_STATUS_DMA_FULL 0x008 /* Bit 3: dma full */
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#define SP_STATUS_IO_FULL 0x010 /* Bit 4: io full */
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#define SP_STATUS_SSTEP 0x020 /* Bit 5: single step */
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#define SP_STATUS_INTR_BREAK 0x040 /* Bit 6: interrupt on break */
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#define SP_STATUS_SIG0 0x080 /* Bit 7: signal 0 set */
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#define SP_STATUS_SIG1 0x100 /* Bit 8: signal 1 set */
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#define SP_STATUS_SIG2 0x200 /* Bit 9: signal 2 set */
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#define SP_STATUS_SIG3 0x400 /* Bit 10: signal 3 set */
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#define SP_STATUS_SIG4 0x800 /* Bit 11: signal 4 set */
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#define SP_STATUS_SIG5 0x1000 /* Bit 12: signal 5 set */
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#define SP_STATUS_SIG6 0x2000 /* Bit 13: signal 6 set */
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#define SP_STATUS_SIG7 0x4000 /* Bit 14: signal 7 set */
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#define SP_CLR_HALT 0x00001 /* Bit 0: clear halt */
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#define SP_SET_HALT 0x00002 /* Bit 1: set halt */
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#define SP_CLR_BROKE 0x00004 /* Bit 2: clear broke */
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#define SP_CLR_INTR 0x00008 /* Bit 3: clear intr */
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#define SP_SET_INTR 0x00010 /* Bit 4: set intr */
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#define SP_CLR_SSTEP 0x00020 /* Bit 5: clear sstep */
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#define SP_SET_SSTEP 0x00040 /* Bit 6: set sstep */
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#define SP_CLR_INTR_BREAK 0x00080 /* Bit 7: clear intr on break */
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#define SP_SET_INTR_BREAK 0x00100 /* Bit 8: set intr on break */
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#define SP_CLR_SIG0 0x00200 /* Bit 9: clear signal 0 */
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#define SP_SET_SIG0 0x00400 /* Bit 10: set signal 0 */
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#define SP_CLR_SIG1 0x00800 /* Bit 11: clear signal 1 */
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#define SP_SET_SIG1 0x01000 /* Bit 12: set signal 1 */
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#define SP_CLR_SIG2 0x02000 /* Bit 13: clear signal 2 */
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#define SP_SET_SIG2 0x04000 /* Bit 14: set signal 2 */
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#define SP_CLR_SIG3 0x08000 /* Bit 15: clear signal 3 */
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#define SP_SET_SIG3 0x10000 /* Bit 16: set signal 3 */
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#define SP_CLR_SIG4 0x20000 /* Bit 17: clear signal 4 */
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#define SP_SET_SIG4 0x40000 /* Bit 18: set signal 4 */
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#define SP_CLR_SIG5 0x80000 /* Bit 19: clear signal 5 */
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#define SP_SET_SIG5 0x100000 /* Bit 20: set signal 5 */
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#define SP_CLR_SIG6 0x200000 /* Bit 21: clear signal 6 */
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#define SP_SET_SIG6 0x400000 /* Bit 22: set signal 6 */
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#define SP_CLR_SIG7 0x800000 /* Bit 23: clear signal 7 */
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#define SP_SET_SIG7 0x1000000 /* Bit 24: set signal 7 */
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#define DPC_CLR_XBUS_DMEM_DMA 0x0001 /* Bit 0: clear xbus_dmem_dma */
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#define DPC_SET_XBUS_DMEM_DMA 0x0002 /* Bit 1: set xbus_dmem_dma */
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#define DPC_CLR_FREEZE 0x0004 /* Bit 2: clear freeze */
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#define DPC_SET_FREEZE 0x0008 /* Bit 3: set freeze */
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#define DPC_CLR_FLUSH 0x0010 /* Bit 4: clear flush */
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#define DPC_SET_FLUSH 0x0020 /* Bit 5: set flush */
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#define DPC_CLR_TMEM_CTR 0x0040 /* Bit 6: clear tmem ctr */
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#define DPC_CLR_PIPE_CTR 0x0080 /* Bit 7: clear pipe ctr */
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#define DPC_CLR_CMD_CTR 0x0100 /* Bit 8: clear cmd ctr */
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#define DPC_CLR_CLOCK_CTR 0x0200 /* Bit 9: clear clock ctr */
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#define DPC_STATUS_XBUS_DMEM_DMA 0x001 /* Bit 0: xbus_dmem_dma */
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#define DPC_STATUS_FREEZE 0x002 /* Bit 1: freeze */
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#define DPC_STATUS_FLUSH 0x004 /* Bit 2: flush */
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#define DPC_STATUS_START_GCLK 0x008 /* Bit 3: start gclk */
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#define DPC_STATUS_TMEM_BUSY 0x010 /* Bit 4: tmem busy */
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#define DPC_STATUS_PIPE_BUSY 0x020 /* Bit 5: pipe busy */
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#define DPC_STATUS_CMD_BUSY 0x040 /* Bit 6: cmd busy */
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#define DPC_STATUS_CBUF_READY 0x080 /* Bit 7: cbuf ready */
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#define DPC_STATUS_DMA_BUSY 0x100 /* Bit 8: dma busy */
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#define DPC_STATUS_END_VALID 0x200 /* Bit 9: end valid */
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#define DPC_STATUS_START_VALID 0x400 /* Bit 10: start valid */
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#define R4300i_SP_Intr 0x1
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extern char * x86_Strings[8];
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extern char * GPR_Strings[32];
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#define x86_Name(Reg) (x86_Strings[(Reg)])
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#define GPR_Name(Reg) (GPR_Strings[(Reg)])
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/*
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#define GPR_Name(Reg)\
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(Reg) == 0 ? "R0" : (Reg) == 1 ? "AT" : (Reg) == 2 ? "V0" : (Reg) == 3 ? "V1" :\
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(Reg) == 4 ? "A0" : (Reg) == 5 ? "A1" : (Reg) == 6 ? "A2" : (Reg) == 7 ? "A3" :\
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(Reg) == 8 ? "T0" : (Reg) == 9 ? "T1" : (Reg) == 10 ? "T2" : (Reg) == 11 ? "T3" :\
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(Reg) == 12 ? "T4" : (Reg) == 13 ? "T5" : (Reg) == 14 ? "T6" : (Reg) == 15 ? "T7" :\
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(Reg) == 16 ? "S0" : (Reg) == 17 ? "S1" : (Reg) == 18 ? "S2" : (Reg) == 19 ? "S3" :\
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(Reg) == 20 ? "S4" : (Reg) == 21 ? "S5" : (Reg) == 22 ? "S6" : (Reg) == 23 ? "S7" :\
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(Reg) == 24 ? "T8" : (Reg) == 25 ? "T9" : (Reg) == 26 ? "K0" : (Reg) == 27 ? "K1" :\
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(Reg) == 28 ? "GP" : (Reg) == 29 ? "SP" : (Reg) == 30 ? "S8" :\
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(Reg) == 31 ? "RA" : "Unknown Register"
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*/
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#define COP0_Name(Reg)\
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(Reg) == 0 ? "SP memory address" :\
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(Reg) == 1 ? "SP DRAM DMA address" :\
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(Reg) == 2 ? "SP read DMA length" :\
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(Reg) == 3 ? "SP write DMA length" :\
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(Reg) == 4 ? "SP status" :\
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(Reg) == 5 ? "SP DMA full" :\
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(Reg) == 6 ? "SP DMA busy" :\
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(Reg) == 7 ? "SP semaphore" :\
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(Reg) == 8 ? "DP CMD DMA start" :\
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(Reg) == 9 ? "DP CMD DMA end" :\
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(Reg) == 10 ? "DP CMD DMA current" :\
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(Reg) == 11 ? "DP CMD status" :\
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(Reg) == 12 ? "DP clock counter" :\
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(Reg) == 13 ? "DP buffer busy counter" :\
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(Reg) == 14 ? "DP pipe busy counter" :\
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(Reg) == 15 ? "DP TMEM load counter" :\
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"Unknown Register"
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#define ElementSpecifier(Elem)\
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(Elem) == 0 ? "" : (Elem) == 1 ? "" : (Elem) == 2 ? " [0q]" :\
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(Elem) == 3 ? " [1q]" : (Elem) == 4 ? " [0h]" : (Elem) == 5 ? " [1h]" :\
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(Elem) == 6 ? " [2h]" : (Elem) == 7 ? " [3h]" : (Elem) == 8 ? " [0]" :\
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(Elem) == 9 ? " [1]" : (Elem) == 10 ? " [2]" : (Elem) == 11 ? " [3]" :\
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(Elem) == 12 ? " [4]" : (Elem) == 13 ? " [5]" : (Elem) == 14 ? " [6]" :\
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(Elem) == 15 ? " [7]" : "Unknown Element"
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void Enter_RSP_Register_Window ( void );
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void InitilizeRSPRegisters (void);
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void UpdateRSPRegistersScreen ( void );
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/*** RSP Registers ***/
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extern UWORD32 RSP_GPR[32], RSP_Flags[4];
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extern UDWORD RSP_ACCUM[8];
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extern VECTOR RSP_Vect[32];
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