2016-07-06 20:14:12 +00:00
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/****************************************************************************
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* *
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* Project64 - A Nintendo 64 emulator. *
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* http://www.pj64-emu.com/ *
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* Copyright (C) 2012 Project64. All rights reserved. *
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* *
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* License: *
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* GNU/GPLv2 http://www.gnu.org/licenses/gpl-2.0.html *
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* *
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****************************************************************************/
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#pragma once
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#include <Project64-core/N64System/N64Types.h>
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class CRegBase
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{
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public:
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CRegBase();
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//enums
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enum REG_STATE
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{
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STATE_UNKNOWN = 0x00,
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STATE_KNOWN_VALUE = 0x01,
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STATE_X86_MAPPED = 0x02,
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STATE_SIGN = 0x04,
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STATE_32BIT = 0x08,
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STATE_MODIFIED = 0x10,
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STATE_MAPPED_64 = (STATE_KNOWN_VALUE | STATE_X86_MAPPED), // = 3
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STATE_MAPPED_32_ZERO = (STATE_KNOWN_VALUE | STATE_X86_MAPPED | STATE_32BIT), // = 11
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STATE_MAPPED_32_SIGN = (STATE_KNOWN_VALUE | STATE_X86_MAPPED | STATE_32BIT | STATE_SIGN), // = 15
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STATE_CONST_32_ZERO = (STATE_KNOWN_VALUE | STATE_32BIT), // = 9
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STATE_CONST_32_SIGN = (STATE_KNOWN_VALUE | STATE_32BIT | STATE_SIGN), // = 13
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STATE_CONST_64 = (STATE_KNOWN_VALUE), // = 1
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};
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void SetMipsRegState(int32_t GetMipsReg, REG_STATE State) { m_MIPS_RegState[GetMipsReg] = State; }
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REG_STATE GetMipsRegState(int32_t Reg) const { return m_MIPS_RegState[Reg]; }
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bool IsKnown(int32_t Reg) const { return ((GetMipsRegState(Reg) & STATE_KNOWN_VALUE) != 0); }
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bool IsUnknown(int32_t Reg) const { return ((GetMipsRegState(Reg) & STATE_KNOWN_VALUE) == 0); }
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bool IsModified(int32_t Reg) const { return ((GetMipsRegState(Reg) & STATE_MODIFIED) != 0); }
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bool IsMapped(int32_t Reg) const { return ((GetMipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_X86_MAPPED)) == (STATE_KNOWN_VALUE | STATE_X86_MAPPED)); }
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bool IsConst(int32_t Reg) const { return ((GetMipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_X86_MAPPED)) == STATE_KNOWN_VALUE); }
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bool IsSigned(int32_t Reg) const { return ((GetMipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_SIGN)) == (STATE_KNOWN_VALUE | STATE_SIGN)); }
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bool IsUnsigned(int32_t Reg) const { return ((GetMipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_SIGN)) == STATE_KNOWN_VALUE); }
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bool Is32Bit(int32_t Reg) const { return ((GetMipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_32BIT)) == (STATE_KNOWN_VALUE | STATE_32BIT)); }
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bool Is64Bit(int32_t Reg) const { return ((GetMipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_32BIT)) == STATE_KNOWN_VALUE); }
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bool Is32BitMapped(int32_t Reg) const { return ((GetMipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_32BIT | STATE_X86_MAPPED)) == (STATE_KNOWN_VALUE | STATE_32BIT | STATE_X86_MAPPED)); }
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bool Is64BitMapped(int32_t Reg) const { return ((GetMipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_32BIT | STATE_X86_MAPPED)) == (STATE_KNOWN_VALUE | STATE_X86_MAPPED)); }
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uint64_t GetMipsReg(int32_t Reg) const { return m_MIPS_RegVal[Reg].UDW; }
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int64_t GetMipsReg_S(int32_t Reg) const { return m_MIPS_RegVal[Reg].DW; }
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uint32_t GetMipsRegLo(int32_t Reg) const { return m_MIPS_RegVal[Reg].UW[0]; }
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int32_t GetMipsRegLo_S(int32_t Reg) const { return m_MIPS_RegVal[Reg].W[0]; }
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uint32_t GetMipsRegHi(int32_t Reg) const { return m_MIPS_RegVal[Reg].UW[1]; }
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int32_t GetMipsRegHi_S(int32_t Reg) const { return m_MIPS_RegVal[Reg].W[1]; }
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void SetMipsRegLo(int32_t Reg, uint32_t Value) { m_MIPS_RegVal[Reg].UW[0] = Value; }
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void SetMipsRegHi(int32_t Reg, uint32_t Value) { m_MIPS_RegVal[Reg].UW[1] = Value; }
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void SetMipsReg(int32_t Reg, uint64_t Value) { m_MIPS_RegVal[Reg].UDW = Value; }
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void SetMipsReg_S(int32_t Reg, int64_t Value) { m_MIPS_RegVal[Reg].DW = Value; }
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void SetBlockCycleCount(uint32_t CyleCount) { m_CycleCount = CyleCount; }
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uint32_t GetBlockCycleCount() const { return m_CycleCount; }
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2016-07-20 12:22:56 +00:00
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void SetFpuBeenUsed(bool FpuUsed) { m_Fpu_Used = FpuUsed; }
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bool GetFpuBeenUsed() const { return m_Fpu_Used; }
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CRegBase& operator=(const CRegBase&);
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bool operator==(const CRegBase& right) const;
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bool operator!=(const CRegBase& right) const;
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2016-07-06 20:14:12 +00:00
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protected:
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REG_STATE m_MIPS_RegState[32];
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MIPS_DWORD m_MIPS_RegVal[32];
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uint32_t m_CycleCount;
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2016-07-20 12:22:56 +00:00
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bool m_Fpu_Used;
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2016-07-06 20:14:12 +00:00
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};
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