2023-08-10 04:46:57 +00:00
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#include "RSPCpu.h"
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#include <Common/CriticalSection.h>
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2023-11-02 09:36:58 +00:00
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#include <Project64-rsp-core/Hle/hle.h>
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2023-08-10 04:46:57 +00:00
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#include <Project64-rsp-core/RSPDebugger.h>
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#include <Project64-rsp-core/RSPInfo.h>
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#include <Project64-rsp-core/Recompiler/RspRecompilerCPU.h>
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#include <Project64-rsp-core/Settings/RspSettings.h>
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#include <Project64-rsp-core/cpu/RSPRegisters.h>
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#include <Project64-rsp-core/cpu/RspSystem.h>
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#include <memory>
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class RSPRegisterHandler;
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UDWORD EleSpec[16], Indx[16];
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uint32_t *PrgCount, NextInstruction, RSP_Running;
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void BuildRecompilerCPU(void);
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CriticalSection g_CPUCriticalSection;
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uint32_t Mfc0Count, SemaphoreExit = 0;
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RSPCpuType g_CPUCore = InterpreterCPU;
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std::unique_ptr<RSPRegisterHandlerPlugin> g_RSPRegisterHandler;
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void SetCPU(RSPCpuType core)
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{
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CGuard Guard(g_CPUCriticalSection);
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g_CPUCore = core;
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switch (core)
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{
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case RecompilerCPU:
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BuildRecompilerCPU();
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break;
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case InterpreterCPU:
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break;
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}
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}
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void Build_RSP(void)
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{
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extern UWORD32 Recp, RecpResult, SQroot, SQrootResult;
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Recp.UW = 0;
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RecpResult.UW = 0;
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SQroot.UW = 0;
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SQrootResult.UW = 0;
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SetCPU(g_CPUCore);
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if (g_RSPDebugger != nullptr)
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{
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g_RSPDebugger->ResetTimerList();
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}
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EleSpec[0].DW = 0x0001020304050607; // None
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EleSpec[1].DW = 0x0001020304050607; // None
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EleSpec[2].DW = 0x0000020204040606; // 0q
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EleSpec[3].DW = 0x0101030305050707; // 1q
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EleSpec[4].DW = 0x0000000004040404; // 0h
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EleSpec[5].DW = 0x0101010105050505; // 1h
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EleSpec[6].DW = 0x0202020206060606; // 2h
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EleSpec[7].DW = 0x0303030307070707; // 3h
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EleSpec[8].DW = 0x0000000000000000; // 0
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EleSpec[9].DW = 0x0101010101010101; // 1
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EleSpec[10].DW = 0x0202020202020202; // 2
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EleSpec[11].DW = 0x0303030303030303; // 3
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EleSpec[12].DW = 0x0404040404040404; // 4
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EleSpec[13].DW = 0x0505050505050505; // 5
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EleSpec[14].DW = 0x0606060606060606; // 6
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EleSpec[15].DW = 0x0707070707070707; // 7
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Indx[0].DW = 0x0001020304050607; // None
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Indx[1].DW = 0x0001020304050607; // None
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Indx[2].DW = 0x0103050700020406; // 0q
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Indx[3].DW = 0x0002040601030507; // 1q
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Indx[4].DW = 0x0102030506070004; // 0h
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Indx[5].DW = 0x0002030406070105; // 1h
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Indx[6].DW = 0x0001030405070206; // 2h
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Indx[7].DW = 0x0001020405060307; // 3h
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Indx[8].DW = 0x0102030405060700; // 0
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Indx[9].DW = 0x0002030405060701; // 1
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Indx[10].DW = 0x0001030405060702; // 2
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Indx[11].DW = 0x0001020405060703; // 3
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Indx[12].DW = 0x0001020305060704; // 4
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Indx[13].DW = 0x0001020304060705; // 5
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Indx[14].DW = 0x0001020304050706; // 6
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Indx[15].DW = 0x0001020304050607; // 7
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for (uint8_t i = 0, n = sizeof(EleSpec) / sizeof(EleSpec[0]); i < n; i++)
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{
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for (uint8_t z = 0; z < 8; z++)
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{
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Indx[i].B[z] = 7 - Indx[i].B[z];
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EleSpec[i].B[z] = 7 - EleSpec[i].B[z];
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}
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for (uint8_t z = 0; z < 4; z++)
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{
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uint8_t Temp = Indx[i].B[z];
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Indx[i].B[z] = Indx[i].B[7 - z];
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Indx[i].B[7 - z] = Temp;
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}
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}
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PrgCount = RSPInfo.SP_PC_REG;
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}
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2021-05-18 11:51:36 +00:00
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/*
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Function: DoRspCycles
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Purpose: This function is to allow the RSP to run in parallel with
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the r4300i switching control back to the r4300i once the
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function ends.
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Input: The number of cycles that is meant to be executed.
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Output: The number of cycles that was executed. This value can
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be greater than the number of cycles that the RSP should have performed.
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(this value is ignored if the RSP has been stopped)
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*/
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#define MI_INTR_SP 0x01 /* Bit 0: SP intr */
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uint32_t DoRspCycles(uint32_t Cycles)
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{
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extern bool AudioHle, GraphicsHle;
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uint32_t TaskType = *(uint32_t *)(RSPInfo.DMEM + 0xFC0);
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if (TaskType == 1 && GraphicsHle && *(uint32_t *)(RSPInfo.DMEM + 0x0ff0) != 0)
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{
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if (RSPInfo.ProcessDList != NULL)
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{
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RSPInfo.ProcessDList();
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}
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*RSPInfo.SP_STATUS_REG |= (0x0203);
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if ((*RSPInfo.SP_STATUS_REG & SP_STATUS_INTR_BREAK) != 0)
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{
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*RSPInfo.MI_INTR_REG |= MI_INTR_SP;
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RSPInfo.CheckInterrupts();
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}
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*RSPInfo.DPC_STATUS_REG &= ~0x0002;
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return Cycles;
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}
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else if (TaskType == 2 && HleAlistTask)
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{
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if (g_hle == nullptr)
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{
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g_hle = new CHle(RSPInfo);
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}
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if (g_hle != nullptr)
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{
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g_hle->try_fast_audio_dispatching();
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*RSPInfo.SP_STATUS_REG |= SP_STATUS_SIG2 | SP_STATUS_BROKE | SP_STATUS_HALT;
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if ((*RSPInfo.SP_STATUS_REG & SP_STATUS_INTR_BREAK) != 0)
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{
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*RSPInfo.MI_INTR_REG |= MI_INTR_SP;
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RSPInfo.CheckInterrupts();
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}
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}
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}
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else if (TaskType == 2 && AudioHle)
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{
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if (RSPInfo.ProcessAList != NULL)
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{
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RSPInfo.ProcessAList();
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}
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*RSPInfo.SP_STATUS_REG |= SP_STATUS_SIG2 | SP_STATUS_BROKE | SP_STATUS_HALT;
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if ((*RSPInfo.SP_STATUS_REG & SP_STATUS_INTR_BREAK) != 0)
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{
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*RSPInfo.MI_INTR_REG |= MI_INTR_SP;
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RSPInfo.CheckInterrupts();
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}
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return Cycles;
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}
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else if (TaskType == 7)
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{
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RSPInfo.ShowCFB();
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}
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2016-01-27 09:11:59 +00:00
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2023-11-02 09:36:58 +00:00
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if (g_RSPDebugger != nullptr)
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{
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g_RSPDebugger->RspCyclesStart();
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}
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CGuard Guard(g_CPUCriticalSection);
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2016-01-27 09:11:59 +00:00
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2023-08-10 04:46:57 +00:00
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switch (g_CPUCore)
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{
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case RecompilerCPU:
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CRSPRecompiler(RSPSystem).RunCPU(Cycles);
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break;
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case InterpreterCPU:
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RSPSystem.RunInterpreterCPU(Cycles);
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break;
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}
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if (g_RSPDebugger != nullptr)
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{
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g_RSPDebugger->RspCyclesStop();
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}
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return Cycles;
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2016-01-27 09:11:59 +00:00
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}
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