mirror of https://github.com/PCSX2/pcsx2.git
639 lines
17 KiB
C++
639 lines
17 KiB
C++
// SPDX-FileCopyrightText: 2002-2023 PCSX2 Dev Team
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// SPDX-License-Identifier: LGPL-3.0+
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#include "Common.h"
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#include "COP0.h"
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// Updates the CPU's mode of operation (either, Kernel, Supervisor, or User modes).
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// Currently the different modes are not implemented.
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// Given this function is called so much, it's commented out for now. (rama)
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__ri void cpuUpdateOperationMode()
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{
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//u32 value = cpuRegs.CP0.n.Status.val;
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//if (value & 0x06 ||
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// (value & 0x18) == 0) { // Kernel Mode (KSU = 0 | EXL = 1 | ERL = 1)*/
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// memSetKernelMode(); // Kernel memory always
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//} else { // User Mode
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// memSetUserMode();
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//}
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}
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void WriteCP0Status(u32 value)
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{
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COP0_UpdatePCCR();
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cpuRegs.CP0.n.Status.val = value;
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cpuSetNextEventDelta(4);
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}
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void WriteCP0Config(u32 value)
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{
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// Protect the read-only ICacheSize (IC) and DataCacheSize (DC) bits
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cpuRegs.CP0.n.Config = value & ~0xFC0;
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cpuRegs.CP0.n.Config |= 0x440;
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}
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//////////////////////////////////////////////////////////////////////////////////////////
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// Performance Counters Update Stuff!
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//
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// Note regarding updates of PERF and TIMR registers: never allow increment to be 0.
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// That happens when a game loads the MFC0 twice in the same recompiled block (before the
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// cpuRegs.cycles update), and can cause games to lock up since it's an unexpected result.
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//
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// PERF Overflow exceptions: The exception is raised when the MSB of the Performance
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// Counter Register is set. I'm assuming the exception continues to re-raise until the
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// app clears the bit manually (needs testing).
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//
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// PERF Events:
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// * Event 0 on PCR 0 is unused (counter disable)
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// * Event 16 is usable as a specific counter disable bit (since CTE affects both counters)
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// * Events 17-31 are reserved (act as counter disable)
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//
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// Most event mode aren't supported, and issue a warning and do a standard instruction
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// count. But only mode 1 (instruction counter) has been found to be used by games thus far.
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//
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static __fi bool PERF_ShouldCountEvent(uint evt)
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{
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switch (evt)
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{
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// This is a rough table of actions for various PCR modes. Some of these
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// can be implemented more accurately later. Others (WBBs in particular)
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// probably cannot without some severe complications.
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// left sides are PCR0 / right sides are PCR1
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case 1: // cpu cycle counter.
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case 2: // single/dual instruction issued
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case 3: // Branch issued / Branch mispredicated
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return true;
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case 4: // BTAC/TLB miss
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case 5: // ITLB/DTLB miss
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case 6: // Data/Instruction cache miss
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return false;
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case 7: // Access to DTLB / WBB single request fail
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case 8: // Non-blocking load / WBB burst request fail
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case 9:
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case 10:
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return false;
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case 11: // CPU address bus busy / CPU data bus busy
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return false;
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case 12: // Instruction completed
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case 13: // non-delayslot instruction completed
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case 14: // COP2/COP1 instruction complete
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case 15: // Load/Store completed
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return true;
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}
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return false;
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}
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// Diagnostics for event modes that we just ignore for now. Using these perf units could
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// cause compat issues in some very odd/rare games, so if this msg comes up who knows,
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// might save some debugging effort. :)
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void COP0_DiagnosticPCCR()
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{
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if (cpuRegs.PERF.n.pccr.b.Event0 >= 7 && cpuRegs.PERF.n.pccr.b.Event0 <= 10)
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Console.Warning("PERF/PCR0 Unsupported Update Event Mode = 0x%x", cpuRegs.PERF.n.pccr.b.Event0);
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if (cpuRegs.PERF.n.pccr.b.Event1 >= 7 && cpuRegs.PERF.n.pccr.b.Event1 <= 10)
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Console.Warning("PERF/PCR1 Unsupported Update Event Mode = 0x%x", cpuRegs.PERF.n.pccr.b.Event1);
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}
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extern int branch;
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__fi void COP0_UpdatePCCR()
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{
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// Counting and counter exceptions are not performed if we are currently executing a Level 2 exception (ERL)
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// or the counting function is not enabled (CTE)
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if (cpuRegs.CP0.n.Status.b.ERL || !cpuRegs.PERF.n.pccr.b.CTE)
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{
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cpuRegs.lastPERFCycle[0] = cpuRegs.cycle;
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cpuRegs.lastPERFCycle[1] = cpuRegs.lastPERFCycle[0];
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return;
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}
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// Implemented memory mode check (kernel/super/user)
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if (cpuRegs.PERF.n.pccr.val & ((1 << (cpuRegs.CP0.n.Status.b.KSU + 2)) | (cpuRegs.CP0.n.Status.b.EXL << 1)))
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{
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// ----------------------------------
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// Update Performance Counter 0
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// ----------------------------------
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if (PERF_ShouldCountEvent(cpuRegs.PERF.n.pccr.b.Event0))
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{
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u32 incr = cpuRegs.cycle - cpuRegs.lastPERFCycle[0];
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if (incr == 0)
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incr++;
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// use prev/XOR method for one-time exceptions (but likely less correct)
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//u32 prev = cpuRegs.PERF.n.pcr0;
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cpuRegs.PERF.n.pcr0 += incr;
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//DevCon.Warning("PCR VAL %x", cpuRegs.PERF.n.pccr.val);
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//prev ^= (1UL<<31); // XOR is fun!
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//if( (prev & cpuRegs.PERF.n.pcr0) & (1UL<<31) )
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if ((cpuRegs.PERF.n.pcr0 & 0x80000000))
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{
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// TODO: Vector to the appropriate exception here.
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// This code *should* be correct, but is untested (and other parts of the emu are
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// not prepared to handle proper Level 2 exception vectors yet)
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//branch == 1 is probably not the best way to check for the delay slot, but it beats nothing! (Refraction)
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/* if( branch == 1 )
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{
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cpuRegs.CP0.n.ErrorEPC = cpuRegs.pc - 4;
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cpuRegs.CP0.n.Cause |= 0x40000000;
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}
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else
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{
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cpuRegs.CP0.n.ErrorEPC = cpuRegs.pc;
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cpuRegs.CP0.n.Cause &= ~0x40000000;
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}
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if( cpuRegs.CP0.n.Status.b.DEV )
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{
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// Bootstrap vector
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cpuRegs.pc = 0xbfc00280;
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}
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else
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{
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cpuRegs.pc = 0x80000080;
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}
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cpuRegs.CP0.n.Status.b.ERL = 1;
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cpuRegs.CP0.n.Cause |= 0x20000;*/
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}
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}
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}
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if (cpuRegs.PERF.n.pccr.val & ((1 << (cpuRegs.CP0.n.Status.b.KSU + 12)) | (cpuRegs.CP0.n.Status.b.EXL << 11)))
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{
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// ----------------------------------
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// Update Performance Counter 1
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// ----------------------------------
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if (PERF_ShouldCountEvent(cpuRegs.PERF.n.pccr.b.Event1))
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{
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u32 incr = cpuRegs.cycle - cpuRegs.lastPERFCycle[1];
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if (incr == 0)
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incr++;
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cpuRegs.PERF.n.pcr1 += incr;
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if ((cpuRegs.PERF.n.pcr1 & 0x80000000))
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{
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// TODO: Vector to the appropriate exception here.
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// This code *should* be correct, but is untested (and other parts of the emu are
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// not prepared to handle proper Level 2 exception vectors yet)
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//branch == 1 is probably not the best way to check for the delay slot, but it beats nothing! (Refraction)
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/*if( branch == 1 )
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{
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cpuRegs.CP0.n.ErrorEPC = cpuRegs.pc - 4;
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cpuRegs.CP0.n.Cause |= 0x40000000;
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}
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else
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{
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cpuRegs.CP0.n.ErrorEPC = cpuRegs.pc;
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cpuRegs.CP0.n.Cause &= ~0x40000000;
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}
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if( cpuRegs.CP0.n.Status.b.DEV )
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{
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// Bootstrap vector
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cpuRegs.pc = 0xbfc00280;
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}
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else
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{
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cpuRegs.pc = 0x80000080;
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}
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cpuRegs.CP0.n.Status.b.ERL = 1;
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cpuRegs.CP0.n.Cause |= 0x20000;*/
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}
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}
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}
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cpuRegs.lastPERFCycle[0] = cpuRegs.cycle;
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cpuRegs.lastPERFCycle[1] = cpuRegs.cycle;
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}
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//////////////////////////////////////////////////////////////////////////////////////////
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//
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void MapTLB(const tlbs& t, int i)
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{
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u32 mask, addr;
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u32 saddr, eaddr;
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COP0_LOG("MAP TLB %d: 0x%08X-> [0x%08X 0x%08X] S=%d G=%d ASID=%d Mask=0x%03X EntryLo0 PFN=%x EntryLo0 Cache=%x EntryLo1 PFN=%x EntryLo1 Cache=%x VPN2=%x",
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i, t.VPN2, t.PFN0, t.PFN1, t.S >> 31, t.G, t.ASID,
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t.Mask, t.EntryLo0 >> 6, (t.EntryLo0 & 0x38) >> 3, t.EntryLo1 >> 6, (t.EntryLo1 & 0x38) >> 3, t.VPN2);
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// According to the manual
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// 'It [SPR] must be mapped into a contiguous 16 KB of virtual address space that is
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// aligned on a 16KB boundary.Results are not guaranteed if this restriction is not followed.'
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// Assume that the game isn't doing anything less-than-ideal with the scratchpad mapping and map it directly to eeMem->Scratch.
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if (t.S)
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{
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if (t.VPN2 != 0x70000000)
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Console.Warning("COP0: Mapping Scratchpad to non-default address 0x%08X", t.VPN2);
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vtlb_VMapBuffer(t.VPN2, eeMem->Scratch, Ps2MemSize::Scratch);
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}
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else
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{
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if (t.EntryLo0 & 0x2)
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{
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mask = ((~t.Mask) << 1) & 0xfffff;
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saddr = t.VPN2 >> 12;
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eaddr = saddr + t.Mask + 1;
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for (addr = saddr; addr < eaddr; addr++)
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{
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if ((addr & mask) == ((t.VPN2 >> 12) & mask))
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{ //match
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memSetPageAddr(addr << 12, t.PFN0 + ((addr - saddr) << 12));
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Cpu->Clear(addr << 12, 0x400);
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}
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}
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}
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if (t.EntryLo1 & 0x2)
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{
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mask = ((~t.Mask) << 1) & 0xfffff;
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saddr = (t.VPN2 >> 12) + t.Mask + 1;
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eaddr = saddr + t.Mask + 1;
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for (addr = saddr; addr < eaddr; addr++)
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{
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if ((addr & mask) == ((t.VPN2 >> 12) & mask))
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{ //match
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memSetPageAddr(addr << 12, t.PFN1 + ((addr - saddr) << 12));
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Cpu->Clear(addr << 12, 0x400);
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}
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}
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}
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}
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}
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void UnmapTLB(const tlbs& t, int i)
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{
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//Console.WriteLn("Clear TLB %d: %08x-> [%08x %08x] S=%d G=%d ASID=%d Mask= %03X", i,t.VPN2,t.PFN0,t.PFN1,t.S,t.G,t.ASID,t.Mask);
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u32 mask, addr;
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u32 saddr, eaddr;
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if (t.S)
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{
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vtlb_VMapUnmap(t.VPN2, 0x4000);
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return;
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}
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if (t.EntryLo0 & 0x2)
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{
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mask = ((~t.Mask) << 1) & 0xfffff;
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saddr = t.VPN2 >> 12;
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eaddr = saddr + t.Mask + 1;
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// Console.WriteLn("Clear TLB: %08x ~ %08x",saddr,eaddr-1);
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for (addr = saddr; addr < eaddr; addr++)
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{
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if ((addr & mask) == ((t.VPN2 >> 12) & mask))
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{ //match
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memClearPageAddr(addr << 12);
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Cpu->Clear(addr << 12, 0x400);
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}
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}
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}
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if (t.EntryLo1 & 0x2)
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{
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mask = ((~t.Mask) << 1) & 0xfffff;
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saddr = (t.VPN2 >> 12) + t.Mask + 1;
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eaddr = saddr + t.Mask + 1;
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// Console.WriteLn("Clear TLB: %08x ~ %08x",saddr,eaddr-1);
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for (addr = saddr; addr < eaddr; addr++)
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{
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if ((addr & mask) == ((t.VPN2 >> 12) & mask))
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{ //match
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memClearPageAddr(addr << 12);
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Cpu->Clear(addr << 12, 0x400);
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}
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}
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}
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}
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void WriteTLB(int i)
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{
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tlb[i].PageMask = cpuRegs.CP0.n.PageMask;
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tlb[i].EntryHi = cpuRegs.CP0.n.EntryHi;
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tlb[i].EntryLo0 = cpuRegs.CP0.n.EntryLo0;
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tlb[i].EntryLo1 = cpuRegs.CP0.n.EntryLo1;
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tlb[i].Mask = (cpuRegs.CP0.n.PageMask >> 13) & 0xfff;
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tlb[i].nMask = (~tlb[i].Mask) & 0xfff;
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tlb[i].VPN2 = ((cpuRegs.CP0.n.EntryHi >> 13) & (~tlb[i].Mask)) << 13;
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tlb[i].ASID = cpuRegs.CP0.n.EntryHi & 0xfff;
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tlb[i].G = cpuRegs.CP0.n.EntryLo0 & cpuRegs.CP0.n.EntryLo1 & 0x1;
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tlb[i].PFN0 = (((cpuRegs.CP0.n.EntryLo0 >> 6) & 0xFFFFF) & (~tlb[i].Mask)) << 12;
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tlb[i].PFN1 = (((cpuRegs.CP0.n.EntryLo1 >> 6) & 0xFFFFF) & (~tlb[i].Mask)) << 12;
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tlb[i].S = cpuRegs.CP0.n.EntryLo0 & 0x80000000;
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MapTLB(tlb[i], i);
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}
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namespace R5900 {
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namespace Interpreter {
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namespace OpcodeImpl {
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namespace COP0 {
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void TLBR()
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{
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COP0_LOG("COP0_TLBR %d:%x,%x,%x,%x",
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cpuRegs.CP0.n.Index, cpuRegs.CP0.n.PageMask, cpuRegs.CP0.n.EntryHi,
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cpuRegs.CP0.n.EntryLo0, cpuRegs.CP0.n.EntryLo1);
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int i = cpuRegs.CP0.n.Index & 0x3f;
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cpuRegs.CP0.n.PageMask = tlb[i].PageMask;
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cpuRegs.CP0.n.EntryHi = tlb[i].EntryHi & ~(tlb[i].PageMask | 0x1f00);
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cpuRegs.CP0.n.EntryLo0 = (tlb[i].EntryLo0 & ~1) | ((tlb[i].EntryHi >> 12) & 1);
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cpuRegs.CP0.n.EntryLo1 = (tlb[i].EntryLo1 & ~1) | ((tlb[i].EntryHi >> 12) & 1);
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}
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void TLBWI()
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{
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int j = cpuRegs.CP0.n.Index & 0x3f;
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//if (j > 48) return;
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COP0_LOG("COP0_TLBWI %d:%x,%x,%x,%x",
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cpuRegs.CP0.n.Index, cpuRegs.CP0.n.PageMask, cpuRegs.CP0.n.EntryHi,
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cpuRegs.CP0.n.EntryLo0, cpuRegs.CP0.n.EntryLo1);
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UnmapTLB(tlb[j], j);
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tlb[j].PageMask = cpuRegs.CP0.n.PageMask;
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tlb[j].EntryHi = cpuRegs.CP0.n.EntryHi;
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tlb[j].EntryLo0 = cpuRegs.CP0.n.EntryLo0;
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tlb[j].EntryLo1 = cpuRegs.CP0.n.EntryLo1;
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WriteTLB(j);
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}
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void TLBWR()
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{
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int j = cpuRegs.CP0.n.Random & 0x3f;
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//if (j > 48) return;
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DevCon.Warning("COP0_TLBWR %d:%x,%x,%x,%x\n",
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cpuRegs.CP0.n.Random, cpuRegs.CP0.n.PageMask, cpuRegs.CP0.n.EntryHi,
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cpuRegs.CP0.n.EntryLo0, cpuRegs.CP0.n.EntryLo1);
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//if (j > 48) return;
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UnmapTLB(tlb[j], j);
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tlb[j].PageMask = cpuRegs.CP0.n.PageMask;
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tlb[j].EntryHi = cpuRegs.CP0.n.EntryHi;
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tlb[j].EntryLo0 = cpuRegs.CP0.n.EntryLo0;
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tlb[j].EntryLo1 = cpuRegs.CP0.n.EntryLo1;
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WriteTLB(j);
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}
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void TLBP()
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{
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int i;
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union
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{
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struct
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{
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u32 VPN2 : 19;
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u32 VPN2X : 2;
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u32 G : 3;
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u32 ASID : 8;
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} s;
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u32 u;
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} EntryHi32;
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EntryHi32.u = cpuRegs.CP0.n.EntryHi;
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cpuRegs.CP0.n.Index = 0xFFFFFFFF;
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for (i = 0; i < 48; i++)
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{
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if (tlb[i].VPN2 == ((~tlb[i].Mask) & (EntryHi32.s.VPN2)) && ((tlb[i].G & 1) || ((tlb[i].ASID & 0xff) == EntryHi32.s.ASID)))
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{
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cpuRegs.CP0.n.Index = i;
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break;
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}
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}
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if (cpuRegs.CP0.n.Index == 0xFFFFFFFF)
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cpuRegs.CP0.n.Index = 0x80000000;
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}
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void MFC0()
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{
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// Note on _Rd_ Condition 9: CP0.Count should be updated even if _Rt_ is 0.
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if ((_Rd_ != 9) && !_Rt_)
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return;
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//if(bExecBIOS == FALSE && _Rd_ == 25) Console.WriteLn("MFC0 _Rd_ %x = %x", _Rd_, cpuRegs.CP0.r[_Rd_]);
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switch (_Rd_)
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{
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case 12:
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cpuRegs.GPR.r[_Rt_].SD[0] = (s32)(cpuRegs.CP0.r[_Rd_] & 0xf0c79c1f);
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break;
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case 25:
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if (0 == (_Imm_ & 1)) // MFPS, register value ignored
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{
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cpuRegs.GPR.r[_Rt_].SD[0] = (s32)cpuRegs.PERF.n.pccr.val;
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}
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else if (0 == (_Imm_ & 2)) // MFPC 0, only LSB of register matters
|
|
{
|
|
COP0_UpdatePCCR();
|
|
cpuRegs.GPR.r[_Rt_].SD[0] = (s32)cpuRegs.PERF.n.pcr0;
|
|
}
|
|
else // MFPC 1
|
|
{
|
|
COP0_UpdatePCCR();
|
|
cpuRegs.GPR.r[_Rt_].SD[0] = (s32)cpuRegs.PERF.n.pcr1;
|
|
}
|
|
/*Console.WriteLn("MFC0 PCCR = %x PCR0 = %x PCR1 = %x IMM= %x", params
|
|
cpuRegs.PERF.n.pccr, cpuRegs.PERF.n.pcr0, cpuRegs.PERF.n.pcr1, _Imm_ & 0x3F);*/
|
|
break;
|
|
|
|
case 24:
|
|
COP0_LOG("MFC0 Breakpoint debug Registers code = %x", cpuRegs.code & 0x3FF);
|
|
break;
|
|
|
|
case 9:
|
|
{
|
|
u32 incr = cpuRegs.cycle - cpuRegs.lastCOP0Cycle;
|
|
if (incr == 0)
|
|
incr++;
|
|
cpuRegs.CP0.n.Count += incr;
|
|
cpuRegs.lastCOP0Cycle = cpuRegs.cycle;
|
|
if (!_Rt_)
|
|
break;
|
|
}
|
|
[[fallthrough]];
|
|
|
|
default:
|
|
cpuRegs.GPR.r[_Rt_].SD[0] = (s32)cpuRegs.CP0.r[_Rd_];
|
|
}
|
|
}
|
|
|
|
void MTC0()
|
|
{
|
|
//if(bExecBIOS == FALSE && _Rd_ == 25) Console.WriteLn("MTC0 _Rd_ %x = %x", _Rd_, cpuRegs.CP0.r[_Rd_]);
|
|
switch (_Rd_)
|
|
{
|
|
case 9:
|
|
cpuRegs.lastCOP0Cycle = cpuRegs.cycle;
|
|
cpuRegs.CP0.r[9] = cpuRegs.GPR.r[_Rt_].UL[0];
|
|
break;
|
|
|
|
case 12:
|
|
WriteCP0Status(cpuRegs.GPR.r[_Rt_].UL[0]);
|
|
break;
|
|
|
|
case 16:
|
|
WriteCP0Config(cpuRegs.GPR.r[_Rt_].UL[0]);
|
|
break;
|
|
|
|
case 24:
|
|
COP0_LOG("MTC0 Breakpoint debug Registers code = %x", cpuRegs.code & 0x3FF);
|
|
break;
|
|
|
|
case 25:
|
|
/*if(bExecBIOS == FALSE && _Rd_ == 25) Console.WriteLn("MTC0 PCCR = %x PCR0 = %x PCR1 = %x IMM= %x", params
|
|
cpuRegs.PERF.n.pccr, cpuRegs.PERF.n.pcr0, cpuRegs.PERF.n.pcr1, _Imm_ & 0x3F);*/
|
|
if (0 == (_Imm_ & 1)) // MTPS
|
|
{
|
|
if (0 != (_Imm_ & 0x3E)) // only effective when the register is 0
|
|
break;
|
|
// Updates PCRs and sets the PCCR.
|
|
COP0_UpdatePCCR();
|
|
cpuRegs.PERF.n.pccr.val = cpuRegs.GPR.r[_Rt_].UL[0];
|
|
COP0_DiagnosticPCCR();
|
|
}
|
|
else if (0 == (_Imm_ & 2)) // MTPC 0, only LSB of register matters
|
|
{
|
|
cpuRegs.PERF.n.pcr0 = cpuRegs.GPR.r[_Rt_].UL[0];
|
|
cpuRegs.lastPERFCycle[0] = cpuRegs.cycle;
|
|
}
|
|
else // MTPC 1
|
|
{
|
|
cpuRegs.PERF.n.pcr1 = cpuRegs.GPR.r[_Rt_].UL[0];
|
|
cpuRegs.lastPERFCycle[1] = cpuRegs.cycle;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
cpuRegs.CP0.r[_Rd_] = cpuRegs.GPR.r[_Rt_].UL[0];
|
|
break;
|
|
}
|
|
}
|
|
|
|
int CPCOND0()
|
|
{
|
|
return (((dmacRegs.stat.CIS | ~dmacRegs.pcr.CPC) & 0x3FF) == 0x3ff);
|
|
}
|
|
|
|
//#define CPCOND0 1
|
|
|
|
void BC0F()
|
|
{
|
|
if (CPCOND0() == 0)
|
|
intDoBranch(_BranchTarget_);
|
|
}
|
|
|
|
void BC0T()
|
|
{
|
|
if (CPCOND0() == 1)
|
|
intDoBranch(_BranchTarget_);
|
|
}
|
|
|
|
void BC0FL()
|
|
{
|
|
if (CPCOND0() == 0)
|
|
intDoBranch(_BranchTarget_);
|
|
else
|
|
cpuRegs.pc += 4;
|
|
}
|
|
|
|
void BC0TL()
|
|
{
|
|
if (CPCOND0() == 1)
|
|
intDoBranch(_BranchTarget_);
|
|
else
|
|
cpuRegs.pc += 4;
|
|
}
|
|
|
|
void ERET()
|
|
{
|
|
#ifdef ENABLE_VTUNE
|
|
// Allow to stop vtune in a predictable way to compare runs
|
|
// Of course, the limit will depend on the game.
|
|
const u32 million = 1000 * 1000;
|
|
static u32 vtune = 0;
|
|
vtune++;
|
|
|
|
// quick_exit vs exit: quick_exit won't call static storage destructor (OS will manage). It helps
|
|
// avoiding the race condition between threads destruction.
|
|
if (vtune > 30 * million)
|
|
{
|
|
Console.WriteLn("VTUNE: quick_exit");
|
|
std::quick_exit(EXIT_SUCCESS);
|
|
}
|
|
else if (!(vtune % million))
|
|
{
|
|
Console.WriteLn("VTUNE: ERET was called %uM times", vtune / million);
|
|
}
|
|
|
|
#endif
|
|
|
|
if (cpuRegs.CP0.n.Status.b.ERL)
|
|
{
|
|
cpuRegs.pc = cpuRegs.CP0.n.ErrorEPC;
|
|
cpuRegs.CP0.n.Status.b.ERL = 0;
|
|
}
|
|
else
|
|
{
|
|
cpuRegs.pc = cpuRegs.CP0.n.EPC;
|
|
cpuRegs.CP0.n.Status.b.EXL = 0;
|
|
}
|
|
cpuUpdateOperationMode();
|
|
cpuSetNextEventDelta(4);
|
|
intSetBranch();
|
|
}
|
|
|
|
void DI()
|
|
{
|
|
if (cpuRegs.CP0.n.Status.b._EDI || cpuRegs.CP0.n.Status.b.EXL ||
|
|
cpuRegs.CP0.n.Status.b.ERL || (cpuRegs.CP0.n.Status.b.KSU == 0))
|
|
{
|
|
cpuRegs.CP0.n.Status.b.EIE = 0;
|
|
// IRQs are disabled so no need to do a cpu exception/event test...
|
|
//cpuSetNextEventDelta();
|
|
}
|
|
}
|
|
|
|
void EI()
|
|
{
|
|
if (cpuRegs.CP0.n.Status.b._EDI || cpuRegs.CP0.n.Status.b.EXL ||
|
|
cpuRegs.CP0.n.Status.b.ERL || (cpuRegs.CP0.n.Status.b.KSU == 0))
|
|
{
|
|
cpuRegs.CP0.n.Status.b.EIE = 1;
|
|
// schedule an event test, which will check for and raise pending IRQs.
|
|
cpuSetNextEventDelta(4);
|
|
}
|
|
}
|
|
|
|
} // namespace COP0
|
|
} // namespace OpcodeImpl
|
|
} // namespace Interpreter
|
|
} // namespace R5900
|