mirror of https://github.com/PCSX2/pcsx2.git
216 lines
6.2 KiB
C
216 lines
6.2 KiB
C
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2009 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#ifndef __R3000A_H__
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#define __R3000A_H__
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#include <stdio.h>
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union GPRRegs {
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struct {
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u32 r0, at, v0, v1, a0, a1, a2, a3,
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t0, t1, t2, t3, t4, t5, t6, t7,
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s0, s1, s2, s3, s4, s5, s6, s7,
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t8, t9, k0, k1, gp, sp, s8, ra, hi, lo; // hi needs to be at index 32! don't change
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} n;
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u32 r[34]; /* Lo, Hi in r[33] and r[32] */
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};
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union CP0Regs {
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struct {
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u32 Index, Random, EntryLo0, EntryLo1,
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Context, PageMask, Wired, Reserved0,
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BadVAddr, Count, EntryHi, Compare,
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Status, Cause, EPC, PRid,
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Config, LLAddr, WatchLO, WatchHI,
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XContext, Reserved1, Reserved2, Reserved3,
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Reserved4, Reserved5, ECC, CacheErr,
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TagLo, TagHi, ErrorEPC, Reserved6;
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} n;
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u32 r[32];
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};
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struct SVector2D {
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short x, y;
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};
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struct SVector2Dz {
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short z, pad;
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};
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struct SVector3D {
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short x, y, z, pad;
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};
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struct LVector3D {
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short x, y, z, pad;
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};
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struct CBGR {
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unsigned char r, g, b, c;
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};
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struct SMatrix3D {
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short m11, m12, m13, m21, m22, m23, m31, m32, m33, pad;
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};
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union CP2Data {
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struct {
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SVector3D v0, v1, v2;
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CBGR rgb;
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s32 otz;
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s32 ir0, ir1, ir2, ir3;
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SVector2D sxy0, sxy1, sxy2, sxyp;
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SVector2Dz sz0, sz1, sz2, sz3;
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CBGR rgb0, rgb1, rgb2;
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s32 reserved;
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s32 mac0, mac1, mac2, mac3;
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u32 irgb, orgb;
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s32 lzcs, lzcr;
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} n;
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u32 r[32];
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};
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union CP2Ctrl {
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struct {
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SMatrix3D rMatrix;
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s32 trX, trY, trZ;
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SMatrix3D lMatrix;
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s32 rbk, gbk, bbk;
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SMatrix3D cMatrix;
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s32 rfc, gfc, bfc;
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s32 ofx, ofy;
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s32 h;
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s32 dqa, dqb;
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s32 zsf3, zsf4;
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s32 flag;
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} n;
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u32 r[32];
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};
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struct psxRegisters {
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GPRRegs GPR; /* General Purpose Registers */
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CP0Regs CP0; /* Coprocessor0 Registers */
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CP2Data CP2D; /* Cop2 data registers */
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CP2Ctrl CP2C; /* Cop2 control registers */
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u32 pc; /* Program counter */
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u32 code; /* The instruction */
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u32 cycle;
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u32 interrupt;
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u32 sCycle[32]; // start cycle for signaled ints
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s32 eCycle[32]; // cycle delta for signaled ints (sCycle + eCycle == branch cycle)
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//u32 _msflag[32];
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//u32 _smflag[32];
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};
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PCSX2_ALIGNED16_EXTERN(psxRegisters psxRegs);
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extern u32 g_psxNextBranchCycle;
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extern s32 psxBreak; // used when the IOP execution is broken and control returned to the EE
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extern s32 psxCycleEE; // tracks IOP's current sych status with the EE
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#ifndef _PC_
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#define _i32(x) (s32)x //R3000A
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#define _u32(x) (u32)x //R3000A
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#define _i16(x) (s16)x // Not used
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#define _u16(x) (u16)x // Not used
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#define _i8(x) (s8)x // Not used
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#define _u8(x) (u8)x //R3000A - once
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/**** R3000A Instruction Macros ****/
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#define _PC_ psxRegs.pc // The next PC to be executed
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#define _Funct_ ((psxRegs.code ) & 0x3F) // The funct part of the instruction register
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#define _Rd_ ((psxRegs.code >> 11) & 0x1F) // The rd part of the instruction register
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#define _Rt_ ((psxRegs.code >> 16) & 0x1F) // The rt part of the instruction register
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#define _Rs_ ((psxRegs.code >> 21) & 0x1F) // The rs part of the instruction register
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#define _Sa_ ((psxRegs.code >> 6) & 0x1F) // The sa part of the instruction register
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#define _Im_ ((u16)psxRegs.code) // The immediate part of the instruction register
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#define _Target_ (psxRegs.code & 0x03ffffff) // The target part of the instruction register
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#define _Imm_ ((short)psxRegs.code) // sign-extended immediate
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#define _ImmU_ (psxRegs.code&0xffff) // zero-extended immediate
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#define _rRs_ psxRegs.GPR.r[_Rs_] // Rs register
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#define _rRt_ psxRegs.GPR.r[_Rt_] // Rt register
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#define _rRd_ psxRegs.GPR.r[_Rd_] // Rd register
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#define _rSa_ psxRegs.GPR.r[_Sa_] // Sa register
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#define _rFs_ psxRegs.CP0.r[_Rd_] // Fs register
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#define _c2dRs_ psxRegs.CP2D.r[_Rs_] // Rs cop2 data register
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#define _c2dRt_ psxRegs.CP2D.r[_Rt_] // Rt cop2 data register
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#define _c2dRd_ psxRegs.CP2D.r[_Rd_] // Rd cop2 data register
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#define _c2dSa_ psxRegs.CP2D.r[_Sa_] // Sa cop2 data register
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#define _rHi_ psxRegs.GPR.n.hi // The HI register
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#define _rLo_ psxRegs.GPR.n.lo // The LO register
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#define _JumpTarget_ ((_Target_ << 2) + (_PC_ & 0xf0000000)) // Calculates the target during a jump instruction
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#define _BranchTarget_ (((s32)(s16)_Imm_ * 4) + _PC_) // Calculates the target during a branch instruction
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#define _SetLink(x) psxRegs.GPR.r[x] = _PC_ + 4; // Sets the return address in the link register
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extern s32 EEsCycle;
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extern u32 EEoCycle;
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#endif
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extern s32 psxNextCounter;
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extern u32 psxNextsCounter;
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extern bool iopBranchAction;
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extern bool iopEventTestIsActive;
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// Branching status used when throwing exceptions.
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extern bool iopIsDelaySlot;
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////////////////////////////////////////////////////////////////////
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// R3000A Public Interface / API
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struct R3000Acpu {
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void (*Allocate)();
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void (*Reset)();
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void (*Execute)();
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s32 (*ExecuteBlock)( s32 eeCycles ); // executes the given number of EE cycles.
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void (*Clear)(u32 Addr, u32 Size);
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void (*Shutdown)();
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};
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extern R3000Acpu *psxCpu;
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extern R3000Acpu psxInt;
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extern R3000Acpu psxRec;
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void psxReset();
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void psxShutdown();
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void psxException(u32 code, u32 step);
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extern void psxBranchTest();
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void psxExecuteBios();
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void psxMemReset();
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// Subsets
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extern void (*psxBSC[64])();
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extern void (*psxSPC[64])();
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extern void (*psxREG[32])();
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extern void (*psxCP0[32])();
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extern void (*psxCP2[64])();
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extern void (*psxCP2BSC[32])();
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#endif /* __R3000A_H__ */
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