mirror of https://github.com/PCSX2/pcsx2.git
248 lines
7.2 KiB
C
248 lines
7.2 KiB
C
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2009 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#pragma once
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#include "IopMem.h"
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static const u32
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HW_USB_START = 0x1f801600,
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HW_USB_END = 0x1f801700,
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HW_FW_START = 0x1f808400,
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HW_FW_END = 0x1f808550, // end addr for FW is a guess...
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HW_SPU2_START = 0x1f801c00,
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HW_SPU2_END = 0x1f801e00;
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static const u32
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HW_SSBUS_SPD_ADDR = 0x1f801000,
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HW_SSBUS_PIO_ADDR = 0x1f801004,
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HW_SSBUS_SPD_DELAY = 0x1f801008,
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HW_SSBUS_DEV1_DELAY = 0x1f80100C,
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HW_SSBUS_ROM_DELAY = 0x1f801010,
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HW_SSBUS_SPU_DELAY = 0x1f801014,
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HW_SSBUS_DEV5_DELAY = 0x1f801018,
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HW_SSBUS_PIO_DELAY = 0x1f80101c,
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HW_SSBUS_COM_DELAY = 0x1f801020,
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HW_SIO_DATA = 0x1f801040, // SIO read/write register
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HW_SIO_STAT = 0x1f801044,
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HW_SIO_MODE = 0x1f801048,
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HW_SIO_CTRL = 0x1f80104a,
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HW_SIO_BAUD = 0x1f80104e,
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HW_IREG = 0x1f801070,
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HW_IMASK = 0x1f801074,
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HW_ICTRL = 0x1f801078,
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HW_SSBUS_DEV1_ADDR = 0x1f801400,
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HW_SSBUS_SPU_ADDR = 0x1f801404,
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HW_SSBUS_DEV5_ADDR = 0x1f801408,
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HW_SSBUS_SPU1_ADDR = 0x1f80140c,
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HW_SSBUS_DEV9_ADDR3 = 0x1f801410,
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HW_SSBUS_SPU1_DELAY = 0x1f801414,
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HW_SSBUS_DEV9_DELAY2= 0x1f801418,
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HW_SSBUS_DEV9_DELAY3= 0x1f80141c,
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HW_SSBUS_DEV9_DELAY1= 0x1f801420,
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HW_ICFG = 0x1f801450,
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HW_DEV9_DATA = 0x1f80146e, // DEV9 read/write register
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// CDRom registers are used for various command, status, and data stuff.
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HW_CDR_DATA0 = 0x1f801800, // CDROM multipurpose data register 1
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HW_CDR_DATA1 = 0x1f801801, // CDROM multipurpose data register 2
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HW_CDR_DATA2 = 0x1f801802, // CDROM multipurpose data register 3
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HW_CDR_DATA3 = 0x1f801803, // CDROM multipurpose data register 4
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// SIO2 is a DMA interface for the SIO.
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HW_SIO2_DATAIN = 0x1F808260,
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HW_SIO2_FIFO = 0x1f808264,
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HW_SIO2_CTRL = 0x1f808268,
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HW_SIO2_RECV1 = 0x1f80826c,
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HW_SIO2_RECV2 = 0x1f808270,
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HW_SIO2_RECV3 = 0x1f808274,
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HW_SIO2_INTR = 0x1f808280;
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/* Registers for the IOP Counters */
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enum IOPCountRegs
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{
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IOP_T0_COUNT = 0x1f801100,
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IOP_T1_COUNT = 0x1f801110,
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IOP_T2_COUNT = 0x1f801120,
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IOP_T3_COUNT = 0x1f801480,
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IOP_T4_COUNT = 0x1f801490,
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IOP_T5_COUNT = 0x1f8014a0,
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IOP_T0_MODE = 0x1f801104,
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IOP_T1_MODE = 0x1f801114,
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IOP_T2_MODE = 0x1f801124,
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IOP_T3_MODE = 0x1f801484,
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IOP_T4_MODE = 0x1f801494,
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IOP_T5_MODE = 0x1f8014a4,
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IOP_T0_TARGET = 0x1f801108,
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IOP_T1_TARGET = 0x1f801118,
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IOP_T2_TARGET = 0x1f801128,
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IOP_T3_TARGET = 0x1f801488,
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IOP_T4_TARGET = 0x1f801498,
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IOP_T5_TARGET = 0x1f8014a8
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};
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// fixme: I'm sure there's a better way to do this. --arcum42
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#define DmaExec(n) { \
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if (HW_DMA##n##_CHCR & 0x01000000 && \
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HW_DMA_PCR & (8 << (n * 4))) { \
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psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, HW_DMA##n##_CHCR); \
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} \
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}
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#define DmaExec2(n) { \
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if (HW_DMA##n##_CHCR & 0x01000000 && \
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HW_DMA_PCR2 & (8 << ((n-7) * 4))) { \
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psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, HW_DMA##n##_CHCR); \
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} \
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}
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#ifdef ENABLE_NEW_IOPDMA
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#define DmaExecNew(n) { \
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if (HW_DMA##n##_CHCR & 0x01000000 && \
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HW_DMA_PCR & (8 << (n * 4))) { \
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IopDmaStart(n, HW_DMA##n##_CHCR, HW_DMA##n##_MADR, HW_DMA##n##_BCR); \
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} \
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}
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#define DmaExecNew2(n) { \
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if (HW_DMA##n##_CHCR & 0x01000000 && \
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HW_DMA_PCR2 & (8 << ((n-7) * 4))) { \
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IopDmaStart(n, HW_DMA##n##_CHCR, HW_DMA##n##_MADR, HW_DMA##n##_BCR); \
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} \
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}
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#else
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#define DmaExecNew(n) DmaExec(n)
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#define DmaExecNew2(n) DmaExec2(n)
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#endif
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#define HW_DMA0_MADR (psxHu32(0x1080)) // MDEC in DMA
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#define HW_DMA0_BCR (psxHu32(0x1084))
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#define HW_DMA0_CHCR (psxHu32(0x1088))
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#define HW_DMA1_MADR (psxHu32(0x1090)) // MDEC out DMA
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#define HW_DMA1_BCR (psxHu32(0x1094))
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#define HW_DMA1_CHCR (psxHu32(0x1098))
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#define HW_DMA2_MADR (psxHu32(0x10a0)) // GPU DMA
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#define HW_DMA2_BCR (psxHu32(0x10a4))
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#define HW_DMA2_CHCR (psxHu32(0x10a8))
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#define HW_DMA2_TADR (psxHu32(0x10ac))
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#define HW_DMA3_MADR (psxHu32(0x10b0)) // CDROM DMA
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#define HW_DMA3_BCR (psxHu32(0x10b4))
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#define HW_DMA3_BCR_L16 (psxHu16(0x10b4))
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#define HW_DMA3_BCR_H16 (psxHu16(0x10b6))
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#define HW_DMA3_CHCR (psxHu32(0x10b8))
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#define HW_DMA4_MADR (psxHu32(0x10c0)) // SPU DMA
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#define HW_DMA4_BCR (psxHu32(0x10c4))
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#define HW_DMA4_CHCR (psxHu32(0x10c8))
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#define HW_DMA4_TADR (psxHu32(0x10cc))
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#define HW_DMA6_MADR (psxHu32(0x10e0)) // GPU DMA (OT)
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#define HW_DMA6_BCR (psxHu32(0x10e4))
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#define HW_DMA6_CHCR (psxHu32(0x10e8))
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#define HW_DMA7_MADR (psxHu32(0x1500)) // SPU2 DMA
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#define HW_DMA7_BCR (psxHu32(0x1504))
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#define HW_DMA7_CHCR (psxHu32(0x1508))
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#define HW_DMA8_MADR (psxHu32(0x1510)) // DEV9 DMA
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#define HW_DMA8_BCR (psxHu32(0x1514))
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#define HW_DMA8_CHCR (psxHu32(0x1518))
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#define HW_DMA9_MADR (psxHu32(0x1520)) // SIF0 DMA
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#define HW_DMA9_BCR (psxHu32(0x1524))
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#define HW_DMA9_CHCR (psxHu32(0x1528))
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#define HW_DMA9_TADR (psxHu32(0x152c))
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#define HW_DMA10_MADR (psxHu32(0x1530)) // SIF1 DMA
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#define HW_DMA10_BCR (psxHu32(0x1534))
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#define HW_DMA10_CHCR (psxHu32(0x1538))
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#define HW_DMA11_MADR (psxHu32(0x1540)) // SIO2 in
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#define HW_DMA11_BCR (psxHu32(0x1544))
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#define HW_DMA11_CHCR (psxHu32(0x1548))
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#define HW_DMA12_MADR (psxHu32(0x1550)) // SIO2 out
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#define HW_DMA12_BCR (psxHu32(0x1554))
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#define HW_DMA12_CHCR (psxHu32(0x1558))
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#define HW_DMA_PCR (psxHu32(0x10f0))
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#define HW_DMA_ICR (psxHu32(0x10f4))
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#define HW_DMA_PCR2 (psxHu32(0x1570))
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#define HW_DMA_ICR2 (psxHu32(0x1574))
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enum IopEventId
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{
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IopEvt_Cdvd = 5 // General Cdvd commands (Seek, Standby, Break, etc)
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, IopEvt_SIF0 = 9
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, IopEvt_SIF1 = 10
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, IopEvt_Dma11 = 11
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, IopEvt_Dma12 = 12
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, IopEvt_SIO = 16
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, IopEvt_Cdrom = 17
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, IopEvt_CdromRead = 18
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, IopEvt_CdvdRead = 19
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, IopEvt_DEV9 = 20
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, IopEvt_USB = 21
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};
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extern void PSX_INT( IopEventId n, s32 ecycle);
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extern void psxSetNextBranch( u32 startCycle, s32 delta );
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extern void psxSetNextBranchDelta( s32 delta );
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extern int iopTestCycle( u32 startCycle, s32 delta );
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extern void _iopTestInterrupts();
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void psxHwReset();
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u8 psxHwRead8 (u32 add);
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u16 psxHwRead16(u32 add);
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u32 psxHwRead32(u32 add);
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void psxHwWrite8 (u32 add, u8 value);
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void psxHwWrite16(u32 add, u16 value);
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void psxHwWrite32(u32 add, u32 value);
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u8 psxHw4Read8 (u32 add);
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void psxHw4Write8(u32 add, u8 value);
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void psxDmaInterrupt(int n);
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void psxDmaInterrupt2(int n);
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int psxHwFreeze(gzFile f, int Mode);
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int psxHwConstRead8(u32 x86reg, u32 add, u32 sign);
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int psxHwConstRead16(u32 x86reg, u32 add, u32 sign);
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int psxHwConstRead32(u32 x86reg, u32 add);
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void psxHwConstWrite8(u32 add, int mmreg);
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void psxHwConstWrite16(u32 add, int mmreg);
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void psxHwConstWrite32(u32 add, int mmreg);
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int psxHw4ConstRead8 (u32 x86reg, u32 add, u32 sign);
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void psxHw4ConstWrite8(u32 add, int mmreg);
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