mirror of https://github.com/PCSX2/pcsx2.git
612 lines
12 KiB
C++
612 lines
12 KiB
C++
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#define WINVER 0x0600
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#define _WIN32_WINNT 0x0600
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#include <winsock2.h>
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#include <stdlib.h>
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#include <string.h>
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#include <errno.h>
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#include <Winioctl.h>
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#include <fcntl.h>
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#include <windows.h>
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#include <stdarg.h>
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#define EXTERN
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#include "DEV9.h"
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#undef EXTERN
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#include "Config.h"
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#include "smap.h"
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#include "ata.h"
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#ifdef __WIN32__
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#pragma warning(disable:4244)
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HINSTANCE hInst=NULL;
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#endif
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//#define HDD_48BIT
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u8 eeprom[] = {
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//0x6D, 0x76, 0x63, 0x61, 0x31, 0x30, 0x08, 0x01,
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0x76, 0x6D, 0x61, 0x63, 0x30, 0x31, 0x07, 0x02,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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};
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u32 *iopPC;
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const unsigned char version = PS2E_DEV9_VERSION;
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const unsigned char revision = 0;
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const unsigned char build = 3; // increase that with each version
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static char *libraryName = "GiGaHeRz's DEV9 Driver"
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#ifdef _DEBUG
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"(debug)"
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#endif
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;
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HANDLE hEeprom;
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HANDLE mapping;
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u32 CALLBACK PS2EgetLibType() {
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return PS2E_LT_DEV9;
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}
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char* CALLBACK PS2EgetLibName() {
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return libraryName;
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}
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u32 CALLBACK PS2EgetLibVersion2(u32 type) {
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return (version<<16) | (revision<<8) | build;
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}
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// Warning: The below log function is SLOW. Better fix it before attempting to use it.
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int Log = 0;
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void __Log(char *fmt, ...) {
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if (!Log) return;
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va_list list;
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static int ticks=-1;
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int nticks=GetTickCount();
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if(ticks==-1) ticks=nticks;
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if(iopPC!=NULL)
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{
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fprintf(dev9Log,"[%10d + %4d, IOP PC = %08x] ",nticks,nticks-ticks,*iopPC);
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}
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else
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{
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fprintf(dev9Log,"[%10d + %4d] ",nticks,nticks-ticks);
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}
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ticks=nticks;
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va_start(list, fmt);
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vfprintf(dev9Log, fmt, list);
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va_end(list);
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}
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s32 CALLBACK DEV9init()
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{
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#ifdef DEV9_LOG_ENABLE
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dev9Log = fopen("logs/dev9Log.txt", "w");
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setvbuf(dev9Log, NULL, _IONBF, 0);
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DEV9_LOG("DEV9init\n");
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#endif
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memset(&dev9, 0, sizeof(dev9));
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DEV9_LOG("DEV9init2\n");
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DEV9_LOG("DEV9init3\n");
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FLASHinit();
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hEeprom = CreateFile(
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"eeprom.dat",
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GENERIC_READ|GENERIC_WRITE,
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0,
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NULL,
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OPEN_EXISTING,
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FILE_FLAG_WRITE_THROUGH,
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NULL
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);
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if(hEeprom==INVALID_HANDLE_VALUE)
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{
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dev9.eeprom=(u16*)eeprom;
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}
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else
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{
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mapping=CreateFileMapping(hEeprom,NULL,PAGE_READWRITE,0,0,NULL);
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if(mapping==INVALID_HANDLE_VALUE)
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{
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CloseHandle(hEeprom);
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dev9.eeprom=(u16*)eeprom;
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}
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else
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{
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dev9.eeprom = (u16*)MapViewOfFile(mapping,FILE_MAP_WRITE,0,0,0);
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if(dev9.eeprom==NULL)
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{
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CloseHandle(mapping);
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CloseHandle(hEeprom);
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dev9.eeprom=(u16*)eeprom;
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}
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}
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}
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{
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int rxbi;
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for(rxbi=0;rxbi<(SMAP_BD_SIZE/8);rxbi++)
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{
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smap_bd_t *pbd = (smap_bd_t *)&dev9.dev9R[SMAP_BD_RX_BASE & 0xffff];
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pbd = &pbd[rxbi];
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pbd->ctrl_stat = SMAP_BD_RX_EMPTY;
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pbd->length = 0;
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}
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}
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DEV9_LOG("DEV9init ok\n");
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return 0;
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}
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void CALLBACK DEV9shutdown() {
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DEV9_LOG("DEV9shutdown\n");
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#ifdef DEV9_LOG_ENABLE
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fclose(dev9Log);
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#endif
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}
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s32 CALLBACK DEV9open(void *pDsp)
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{
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DEV9_LOG("DEV9open\n");
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LoadConf();
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DEV9_LOG("open r+: %s\n", config.Hdd);
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config.HddSize = 8*1024;
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iopPC = (u32*)pDsp;
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#ifdef ENABLE_ATA
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ata_init();
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#endif
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return _DEV9open();
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}
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void CALLBACK DEV9close()
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{
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DEV9_LOG("DEV9close\n");
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#ifdef ENABLE_ATA
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ata_term();
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#endif
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_DEV9close();
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}
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int CALLBACK _DEV9irqHandler(void)
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{
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//dev9Ru16(SPD_R_INTR_STAT)|= dev9.irqcause;
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DEV9_LOG("_DEV9irqHandler %x, %x\n", dev9.irqcause, dev9Ru16(SPD_R_INTR_MASK));
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if (dev9.irqcause & dev9Ru16(SPD_R_INTR_MASK))
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return 1;
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return 0;
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}
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DEV9handler CALLBACK DEV9irqHandler(void) {
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return (DEV9handler)_DEV9irqHandler;
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}
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void _DEV9irq(int cause, int cycles)
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{
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DEV9_LOG("_DEV9irq %x, %x\n", cause, dev9Ru16(SPD_R_INTR_MASK));
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dev9.irqcause|= cause;
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if(cycles<1)
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DEV9irq(1);
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else
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DEV9irq(cycles);
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}
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u8 CALLBACK DEV9read8(u32 addr) {
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u8 hard;
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if (addr>=ATA_DEV9_HDD_BASE && addr<ATA_DEV9_HDD_END)
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{
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#ifdef ENABLE_ATA
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return ata_read<1>(addr);
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#else
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return 0;
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#endif
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}
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if (addr>=SMAP_REGBASE && addr<FLASH_REGBASE)
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{
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//smap
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return smap_read8(addr);
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}
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switch (addr)
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{
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case SPD_R_PIO_DATA:
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/*if(dev9.eeprom_dir!=1)
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{
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hard=0;
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break;
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}*/
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if(dev9.eeprom_state==EEPROM_TDATA)
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{
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if(dev9.eeprom_command==2) //read
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{
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if(dev9.eeprom_bit==0xFF)
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hard=0;
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else
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hard=((dev9.eeprom[dev9.eeprom_address]<<dev9.eeprom_bit)&0x8000)>>11;
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dev9.eeprom_bit++;
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if(dev9.eeprom_bit==16)
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{
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dev9.eeprom_address++;
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dev9.eeprom_bit=0;
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}
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}
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else hard=0;
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}
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else hard=0;
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return hard;
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case DEV9_R_REV:
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hard = 0x32; // expansion bay
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break;
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default:
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if ((addr >= FLASH_REGBASE) && (addr < (FLASH_REGBASE + FLASH_REGSIZE))) {
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return (u8)FLASHread32(addr, 1);
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}
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hard = dev9Ru8(addr);
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DEV9_LOG("*Unknown 8bit read at address %lx value %x\n", addr, hard);
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return hard;
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}
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DEV9_LOG("*Known 8bit read at address %lx value %x\n", addr, hard);
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return hard;
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}
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u16 CALLBACK DEV9read16(u32 addr)
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{
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u16 hard;
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if (addr>=ATA_DEV9_HDD_BASE && addr<ATA_DEV9_HDD_END)
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{
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#ifdef ENABLE_ATA
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return ata_read<2>(addr);
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#else
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return 0;
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#endif
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}
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if (addr>=SMAP_REGBASE && addr<FLASH_REGBASE)
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{
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//smap
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return smap_read16(addr);
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}
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switch (addr)
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{
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case SPD_R_INTR_STAT:
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return dev9.irqcause;
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case DEV9_R_REV:
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hard = 0x0030; // expansion bay
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break;
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case SPD_R_REV_1:
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hard = 0x0011;
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DEV9_LOG("STD_R_REV_1 16bit read %x\n", hard);
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return hard;
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case SPD_R_REV_3:
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// bit 0: smap
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// bit 1: hdd
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// bit 5: flash
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hard = 0;
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/*if (config.hddEnable) {
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hard|= 0x2;
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}*/
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if (config.ethEnable) {
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hard|= 0x1;
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}
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hard|= 0x20;//flash
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break;
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case SPD_R_0e:
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hard = 0x0002;
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break;
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default:
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if ((addr >= FLASH_REGBASE) && (addr < (FLASH_REGBASE + FLASH_REGSIZE))) {
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return (u16)FLASHread32(addr, 2);
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}
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hard = dev9Ru16(addr);
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DEV9_LOG("*Unknown 16bit read at address %lx value %x\n", addr, hard);
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return hard;
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}
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DEV9_LOG("*Known 16bit read at address %lx value %x\n", addr, hard);
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return hard;
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}
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u32 CALLBACK DEV9read32(u32 addr)
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{
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u32 hard;
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if (addr>=ATA_DEV9_HDD_BASE && addr<ATA_DEV9_HDD_END)
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{
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#ifdef ENABLE_ATA
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return ata_read<4>(addr);
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#else
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return 0;
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#endif
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}
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if (addr>=SMAP_REGBASE && addr<FLASH_REGBASE)
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{
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//smap
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return smap_read32(addr);
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}
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switch (addr) {
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default:
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if ((addr >= FLASH_REGBASE) && (addr < (FLASH_REGBASE + FLASH_REGSIZE))) {
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return (u32)FLASHread32(addr, 4);
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}
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hard = dev9Ru32(addr);
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DEV9_LOG("*Unknown 32bit read at address %lx value %x\n", addr, hard);
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return hard;
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}
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DEV9_LOG("*Known 32bit read at address %lx: %lx\n", addr, hard);
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return hard;
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}
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void CALLBACK DEV9write8(u32 addr, u8 value)
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{
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if (addr>=ATA_DEV9_HDD_BASE && addr<ATA_DEV9_HDD_END)
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{
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#ifdef ENABLE_ATA
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ata_write<1>(addr,value);
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#endif
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return;
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}
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if (addr>=SMAP_REGBASE && addr<FLASH_REGBASE)
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{
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//smap
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smap_write8(addr,value);
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return;
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}
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switch (addr) {
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case 0x10000020:
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dev9.irqcause = 0xff;
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break;
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case SPD_R_INTR_STAT:
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emu_printf("SPD_R_INTR_STAT , WTFH ?\n");
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dev9.irqcause=value;
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return;
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case SPD_R_INTR_MASK:
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emu_printf("SPD_R_INTR_MASK8 , WTFH ?\n");
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break;
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case SPD_R_PIO_DIR:
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//DEV9_LOG("SPD_R_PIO_DIR 8bit write %x\n", value);
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if((value&0xc0)!=0xc0)
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return;
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if((value&0x30)==0x20)
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{
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dev9.eeprom_state=0;
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}
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dev9.eeprom_dir=(value>>4)&3;
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return;
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case SPD_R_PIO_DATA:
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//DEV9_LOG("SPD_R_PIO_DATA 8bit write %x\n", value);
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if((value&0xc0)!=0xc0)
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return;
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switch(dev9.eeprom_state)
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{
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case EEPROM_READY:
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dev9.eeprom_command=0;
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dev9.eeprom_state++;
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break;
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case EEPROM_OPCD0:
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dev9.eeprom_command = (value>>4)&2;
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dev9.eeprom_state++;
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dev9.eeprom_bit=0xFF;
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break;
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case EEPROM_OPCD1:
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dev9.eeprom_command |= (value>>5)&1;
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dev9.eeprom_state++;
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break;
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case EEPROM_ADDR0:
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case EEPROM_ADDR1:
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case EEPROM_ADDR2:
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case EEPROM_ADDR3:
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case EEPROM_ADDR4:
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case EEPROM_ADDR5:
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dev9.eeprom_address =
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(dev9.eeprom_address&(63^(1<<(dev9.eeprom_state-EEPROM_ADDR0))))|
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((value>>(dev9.eeprom_state-EEPROM_ADDR0))&(0x20>>(dev9.eeprom_state-EEPROM_ADDR0)));
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dev9.eeprom_state++;
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break;
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case EEPROM_TDATA:
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{
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if(dev9.eeprom_command==1) //write
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{
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dev9.eeprom[dev9.eeprom_address] =
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(dev9.eeprom[dev9.eeprom_address]&(63^(1<<dev9.eeprom_bit)))|
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((value>>dev9.eeprom_bit)&(0x8000>>dev9.eeprom_bit));
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dev9.eeprom_bit++;
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if(dev9.eeprom_bit==16)
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{
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dev9.eeprom_address++;
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dev9.eeprom_bit=0;
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}
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}
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}
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break;
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}
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return;
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default:
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if ((addr >= FLASH_REGBASE) && (addr < (FLASH_REGBASE + FLASH_REGSIZE))) {
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FLASHwrite32(addr, (u32)value, 1);
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return;
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}
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dev9Ru8(addr) = value;
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DEV9_LOG("*Unknown 8bit write at address %lx value %x\n", addr, value);
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return;
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}
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dev9Ru8(addr) = value;
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DEV9_LOG("*Known 8bit write at address %lx value %x\n", addr, value);
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}
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void CALLBACK DEV9write16(u32 addr, u16 value)
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{
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if (addr>=ATA_DEV9_HDD_BASE && addr<ATA_DEV9_HDD_END)
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{
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#ifdef ENABLE_ATA
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ata_write<2>(addr,value);
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#endif
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return;
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}
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if (addr>=SMAP_REGBASE && addr<FLASH_REGBASE)
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{
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//smap
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smap_write16(addr,value);
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return;
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}
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switch (addr)
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{
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case SPD_R_INTR_MASK:
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if ((dev9Ru16(SPD_R_INTR_MASK)!=value) && ((dev9Ru16(SPD_R_INTR_MASK)|value) & dev9.irqcause))
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{
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DEV9_LOG("SPD_R_INTR_MASK16=0x%X , checking for masked/unmasked interrupts\n",value);
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DEV9irq(1);
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}
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break;
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default:
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if ((addr >= FLASH_REGBASE) && (addr < (FLASH_REGBASE + FLASH_REGSIZE))) {
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FLASHwrite32(addr, (u32)value, 2);
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return;
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}
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dev9Ru16(addr) = value;
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DEV9_LOG("*Unknown 16bit write at address %lx value %x\n", addr, value);
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return;
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}
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dev9Ru16(addr) = value;
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DEV9_LOG("*Known 16bit write at address %lx value %x\n", addr, value);
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}
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void CALLBACK DEV9write32(u32 addr, u32 value)
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{
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if (addr>=ATA_DEV9_HDD_BASE && addr<ATA_DEV9_HDD_END)
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{
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#ifdef ENABLE_ATA
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ata_write<4>(addr,value);
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#endif
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return;
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}
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if (addr>=SMAP_REGBASE && addr<FLASH_REGBASE)
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{
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//smap
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smap_write32(addr,value);
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return;
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}
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switch (addr)
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{
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case SPD_R_INTR_MASK:
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emu_printf("SPD_R_INTR_MASK , WTFH ?\n");
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break;
|
|
default:
|
|
if ((addr >= FLASH_REGBASE) && (addr < (FLASH_REGBASE + FLASH_REGSIZE))) {
|
|
FLASHwrite32(addr, (u32)value, 4);
|
|
return;
|
|
}
|
|
|
|
dev9Ru32(addr) = value;
|
|
DEV9_LOG("*Unknown 32bit write at address %lx write %x\n", addr, value);
|
|
return;
|
|
}
|
|
dev9Ru32(addr) = value;
|
|
DEV9_LOG("*Known 32bit write at address %lx value %lx\n", addr, value);
|
|
}
|
|
|
|
void CALLBACK DEV9readDMA8Mem(u32 *pMem, int size)
|
|
{
|
|
DEV9_LOG("*DEV9readDMA8Mem: size %x\n", size);
|
|
emu_printf("rDMA\n");
|
|
|
|
smap_readDMA8Mem(pMem,size);
|
|
#ifdef ENABLE_ATA
|
|
ata_readDMA8Mem(pMem,size);
|
|
#endif
|
|
}
|
|
|
|
void CALLBACK DEV9writeDMA8Mem(u32* pMem, int size)
|
|
{
|
|
DEV9_LOG("*DEV9writeDMA8Mem: size %x\n", size);
|
|
emu_printf("wDMA\n");
|
|
|
|
smap_writeDMA8Mem(pMem,size);
|
|
#ifdef ENABLE_ATA
|
|
ata_writeDMA8Mem(pMem,size);
|
|
#endif
|
|
}
|
|
|
|
|
|
//plugin interface
|
|
void CALLBACK DEV9irqCallback(void (*callback)(int cycles)) {
|
|
DEV9irq = callback;
|
|
}
|
|
|
|
|
|
// extended funcs
|
|
|
|
s32 CALLBACK DEV9test() {
|
|
return 0;
|
|
}
|
|
|
|
void CALLBACK DEV9setSettingsDir(const char* dir)
|
|
{
|
|
// Grab the ini directory.
|
|
// TODO: Use
|
|
// s_strIniPath = (dir == NULL) ? "inis" : dir;
|
|
}
|
|
|
|
|
|
int emu_printf(const char *fmt, ...)
|
|
{
|
|
va_list vl;
|
|
int ret;
|
|
va_start(vl,fmt);
|
|
ret = vfprintf(stderr,fmt,vl);
|
|
va_end(vl);
|
|
fflush(stderr);
|
|
return ret;
|
|
} |