mirror of https://github.com/PCSX2/pcsx2.git
126 lines
4.5 KiB
C++
126 lines
4.5 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include "Debug.h"
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#include "VUmicro.h"
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static char ostr[1024];
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#define ostrA (ostr + strlen(ostr))
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// Type deffinition of our functions
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#define DisFInterface (u32 code, u32 pc)
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#define DisFInterfaceT (u32, u32)
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#define DisFInterfaceN (code, pc)
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typedef char* (*TdisR5900F)DisFInterface;
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// These macros are used to assemble the disassembler functions
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#define MakeDisF(fn, b) \
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char* fn DisFInterface { \
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if( !!CpuVU1->IsInterpreter ) sprintf (ostr, "%8.8x %8.8x:", pc, code); \
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else ostr[0] = 0; \
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b; \
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return ostr; \
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}
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//Lower/Upper instructions can use that..
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#define _Ft_ ((code >> 16) & 0x1F) // The rt part of the instruction register
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#define _Fs_ ((code >> 11) & 0x1F) // The rd part of the instruction register
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#define _Fd_ ((code >> 6) & 0x1F) // The sa part of the instruction register
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#define _It_ (_Ft_ & 15)
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#define _Is_ (_Fs_ & 15)
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#define _Id_ (_Fd_ & 15)
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#define dName(i) sprintf(ostrA, " %-12s", i); \
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#define dNameU(i) { \
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char op[256]; sprintf(op, "%s.%s%s%s%s", i, _X ? "x" : "", _Y ? "y" : "", _Z ? "z" : "", _W ? "w" : ""); \
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sprintf(ostrA, " %-12s", op); \
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}
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#define dCP2128f(i) { \
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if( !CpuVU1->IsInterpreter ) sprintf(ostrA, " %s,", R5900::COP2_REG_FP[i]); \
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else sprintf(ostrA, " w=%f (%8.8x) z=%f (%8.8x) y=%f (%8.8xl) x=%f (%8.8x) (%s),", VU1.VF[i].f.w, VU1.VF[i].UL[3], VU1.VF[i].f.z, VU1.VF[i].UL[2], VU1.VF[i].f.y, VU1.VF[i].UL[1], VU1.VF[i].f.x, VU1.VF[i].UL[0], R5900::COP2_REG_FP[i]); \
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} \
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#define dCP232x(i) { \
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if( !CpuVU1->IsInterpreter ) sprintf(ostrA, " %s,", R5900::COP2_REG_FP[i]); \
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else sprintf(ostrA, " x=%f (%s),", VU1.VF[i].f.x, R5900::COP2_REG_FP[i]); \
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} \
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#define dCP232y(i) { \
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if( !CpuVU1->IsInterpreter ) sprintf(ostrA, " %s,", R5900::COP2_REG_FP[i]); \
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else sprintf(ostrA, " y=%f (%s),", VU1.VF[i].f.y, R5900::COP2_REG_FP[i]); \
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} \
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#define dCP232z(i) { \
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if( !CpuVU1->IsInterpreter ) sprintf(ostrA, " %s,", R5900::COP2_REG_FP[i]); \
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else sprintf(ostrA, " z=%f (%s),", VU1.VF[i].f.z, R5900::COP2_REG_FP[i]); \
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}
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#define dCP232w(i) { \
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if( !CpuVU1->IsInterpreter ) sprintf(ostrA, " %s,", R5900::COP2_REG_FP[i]); \
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else sprintf(ostrA, " w=%f (%s),", VU1.VF[i].f.w, R5900::COP2_REG_FP[i]); \
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}
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#define dCP2ACCf() { \
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if( !CpuVU1->IsInterpreter ) sprintf(ostrA, " ACC,"); \
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else sprintf(ostrA, " w=%f z=%f y=%f x=%f (ACC),", VU1.ACC.f.w, VU1.ACC.f.z, VU1.ACC.f.y, VU1.ACC.f.x); \
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} \
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#define dCP232i(i) { \
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if( !CpuVU1->IsInterpreter ) sprintf(ostrA, " %s,", R5900::COP2_REG_CTL[i]); \
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else sprintf(ostrA, " %8.8x (%s),", VU1.VI[i].UL, R5900::COP2_REG_CTL[i]); \
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}
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#define dCP232iF(i) { \
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if( !CpuVU1->IsInterpreter ) sprintf(ostrA, " %s,", R5900::COP2_REG_CTL[i]); \
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else sprintf(ostrA, " %f (%s),", VU1.VI[i].F, R5900::COP2_REG_CTL[i]); \
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}
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#define dCP232f(i, j) { \
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if( !CpuVU1->IsInterpreter ) sprintf(ostrA, " %s%s,", R5900::COP2_REG_FP[i], R5900::COP2_VFnames[j]); \
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else sprintf(ostrA, " %s=%f (%s),", R5900::COP2_VFnames[j], VU1.VF[i].F[j], R5900::COP2_REG_FP[i]); \
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}
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#define dImm5() sprintf(ostrA, " %d,", (s16)((code >> 6) & 0x10 ? 0xfff0 | ((code >> 6) & 0xf) : (code >> 6) & 0xf))
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#define dImm11() sprintf(ostrA, " %d,", (s16)(code & 0x400 ? 0xfc00 | (code & 0x3ff) : code & 0x3ff))
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#define dImm15() sprintf(ostrA, " %d,", ( ( code >> 10 ) & 0x7800 ) | ( code & 0x7ff ))
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#define _X ((code>>24) & 0x1)
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#define _Y ((code>>23) & 0x1)
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#define _Z ((code>>22) & 0x1)
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#define _W ((code>>21) & 0x1)
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#define _Fsf_ ((code >> 21) & 0x03)
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#define _Ftf_ ((code >> 23) & 0x03)
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/*********************************************************
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* Unknown instruction (would generate an exception) *
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* Format: ? *
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*********************************************************/
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//extern char* disNULL DisFInterface;
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static MakeDisF(disNULL, dName("*** Bad OP ***");)
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#include "DisVUmicro.h"
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#include "DisVUops.h"
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_disVUOpcodes(VU1);
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_disVUTables(VU1);
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