mirror of https://github.com/PCSX2/pcsx2.git
127 lines
2.7 KiB
C++
127 lines
2.7 KiB
C++
/*
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* Copyright (C) 2007-2009 Gabest
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* http://www.gabest.org
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*
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* This Program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This Program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNU Make; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA USA.
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* http://www.gnu.org/copyleft/gpl.html
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*
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*/
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#pragma once
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#include "GSdx.h"
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// http://software.intel.com/en-us/blogs/2012/11/06/exploring-intel-transactional-synchronization-extensions-with-intel-software
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#if 0
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class TransactionScope
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{
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public:
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class Lock
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{
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std::atomic<bool> state;
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public:
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Lock()
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: state(false)
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{
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}
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void lock()
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{
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bool expected_value = false;
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while(state.compare_exchange_strong(expected_value, true))
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{
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do {_mm_pause();} while(state);
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}
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}
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void unlock()
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{
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state = false;
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}
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bool isLocked() const
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{
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return state.load();
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}
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};
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private:
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Lock& fallBackLock;
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TransactionScope();
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public:
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TransactionScope(Lock& fallBackLock_, int max_retries = 3)
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: fallBackLock(fallBackLock_)
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{
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// The TSX (RTM/HLE) instructions on Intel AVX2 CPUs may either be
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// absent or disabled (see errata HSD136 and specification change at
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// http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-desktop-specification-update.pdf)
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// This can cause builds for AVX2 CPUs to fail with GCC/Clang on Linux,
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// so check that the RTM instructions are actually available.
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#if (_M_SSE >= 0x501 && !defined(__GNUC__)) || defined(__RTM__)
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int nretries = 0;
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while(1)
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{
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++nretries;
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unsigned status = _xbegin();
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if(status == _XBEGIN_STARTED)
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{
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if(!fallBackLock.isLocked()) return;
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_xabort(0xff);
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}
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if((status & _XABORT_EXPLICIT) && _XABORT_CODE(status) == 0xff && !(status & _XABORT_NESTED))
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{
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while(fallBackLock.isLocked()) _mm_pause();
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}
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else if(!(status & _XABORT_RETRY))
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{
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break;
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}
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if(nretries >= max_retries)
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{
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break;
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}
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}
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#endif
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fallBackLock.lock();
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}
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~TransactionScope()
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{
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if(fallBackLock.isLocked())
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{
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fallBackLock.unlock();
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}
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#if (_M_SSE >= 0x501 && !defined(__GNUC__)) || defined(__RTM__)
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else
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{
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_xend();
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}
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#endif
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}
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};
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#endif
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