mirror of https://github.com/PCSX2/pcsx2.git
326 lines
6.5 KiB
C
326 lines
6.5 KiB
C
//GiGaHeRz's SPU2 Driver
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//Copyright (c) 2003-2008, David Quintana <gigaherz@gmail.com>
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//
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//This library is free software; you can redistribute it and/or
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//modify it under the terms of the GNU Lesser General Public
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//License as published by the Free Software Foundation; either
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//version 2.1 of the License, or (at your option) any later version.
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//
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//This library is distributed in the hope that it will be useful,
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//but WITHOUT ANY WARRANTY; without even the implied warranty of
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//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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//Lesser General Public License for more details.
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//
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//You should have received a copy of the GNU Lesser General Public
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//License along with this library; if not, write to the Free Software
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//Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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//
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#ifndef DEFS_H_INCLUDED
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#define DEFS_H_INCLUDED
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typedef enum {SPU2_VOL_MODE_CONST,SPU2_VOL_MODE_PLIN,SPU2_VOL_MODE_NLIN,SPU2_VOL_MODE_PLOG,SPU2_VOL_MODE_NLOG} V_VolMode;
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typedef struct {
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u16 Reg_VOL;
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s16 Value; //also Reg_VOLX
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s8 Increment;
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s8 Mode;
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} V_Volume;
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typedef struct {
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u16 Reg_ADSR1;
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u16 Reg_ADSR2;
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//also Reg_ENVX
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s32 Value; // [Air] : Ranges from 0 to 0x7fffffff (signed values are clamped to 0)
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// Phase
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u8 Phase;
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//Attack Rate
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u8 Ar;
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//Attack Mode
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u8 Am;
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//Decay Rate
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u8 Dr;
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//Sustain Level
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u8 Sl;
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//Sustain Rate
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u8 Sr;
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//Sustain Mode
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u8 Sm;
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//Release Rate
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u8 Rr;
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//Release Mode
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u8 Rm;
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//Ready To Release
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u8 Releasing;
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} V_ADSR;
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typedef struct {
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// SPU2 cycle where the Playing started
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u32 PlayCycle;
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// Left Volume
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V_Volume VolumeL;
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// Right Volume
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V_Volume VolumeR;
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// Envelope
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V_ADSR ADSR;
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// Pitch (also Reg_PITCH)
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s16 Pitch;
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// Pitch Modulated by previous voice
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s8 Modulated;
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// Source (Wave/Noise)
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s8 Noise;
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// Direct Output for Left Channel
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s8 DryL;
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// Direct Output for Right Channel
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s8 DryR;
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// Effect Output for Left Channel
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s8 WetL;
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// Effect Output for Right Channel
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s8 WetR;
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// Loop Start Adress (also Reg_LSAH/L)
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u32 LoopStartA;
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// Sound Start Adress (also Reg_SSAH/L)
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u32 StartA;
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// Next Read Data Adress (also Reg_NAXH/L)
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u32 NextA;
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// Voice Decoding State
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s32 Prev1;
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s32 Prev2;
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s8 LoopMode;
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s8 LoopFlags;
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// [Air] : Replaced loop flags read from the ADPCM header with
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// a single LoopFlags value (above) -- more cache-friendly.
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//s8 LoopStart;
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//s8 Loop;
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//s8 LoopEnd;
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// Sample pointer (19:12 bit fixed point)
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s32 SP;
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// Sample pointer for Cubic Interpolation
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// Cubic interpolation mixes a sample behind Linear, so that it
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// can have sample data to either side of the end points from which
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// to extrapolate. This SP represents that late sample position.
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s32 SPc;
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// Previous sample values - used for interpolation
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// [Air] : Inverted order of these members to match the access order in the
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// code (might improve cache hits).
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s32 PV4;
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s32 PV3;
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s32 PV2;
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s32 PV1;
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// Last outputted audio value, used for voice modulation.
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s32 OutX;
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// SBuffer now points directly to an ADPCM cache entry.
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s16 *SBuffer;
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// sample position within the current decoded packet.
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s32 SCurrent;
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} V_Voice;
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#ifndef PUBLIC
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// ** Begin Debug-only variables section **
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// Separated from the V_Voice struct to improve cache performance of
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// the Public Release build.
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struct V_VoiceDebug
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{
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s8 FirstBlock;
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s32 SampleData;
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s32 PeakX;
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s32 displayPeak;
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s32 lastSetStartA;
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s32 lastStopReason;
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};
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struct V_CoreDebug
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{
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V_VoiceDebug Voices[24];
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s32 AutoDMAPeak;
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// Last Transfer Size
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u32 lastsize;
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};
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// Debug tracking information - 24 voices and 2 cores.
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extern V_CoreDebug DebugCores[2];
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#endif
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typedef struct {
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u16 IN_COEF_L;
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u16 IN_COEF_R;
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u32 FB_SRC_A;
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u32 FB_SRC_B;
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u16 FB_ALPHA;
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u16 FB_X;
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u32 IIR_SRC_A0;
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u32 IIR_SRC_A1;
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u32 IIR_SRC_B1;
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u32 IIR_SRC_B0;
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u32 IIR_DEST_A0;
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u32 IIR_DEST_A1;
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u32 IIR_DEST_B0;
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u32 IIR_DEST_B1;
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u16 IIR_ALPHA;
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u16 IIR_COEF;
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u32 ACC_SRC_A0;
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u32 ACC_SRC_A1;
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u32 ACC_SRC_B0;
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u32 ACC_SRC_B1;
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u32 ACC_SRC_C0;
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u32 ACC_SRC_C1;
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u32 ACC_SRC_D0;
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u32 ACC_SRC_D1;
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u16 ACC_COEF_A;
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u16 ACC_COEF_B;
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u16 ACC_COEF_C;
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u16 ACC_COEF_D;
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u32 MIX_DEST_A0;
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u32 MIX_DEST_A1;
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u32 MIX_DEST_B0;
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u32 MIX_DEST_B1;
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} V_Reverb;
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typedef struct {
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u16 Out;
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u16 Info;
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u16 Unknown1;
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u16 Mode;
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u16 Media;
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u16 Unknown2;
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u16 Protection;
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} V_SPDIF;
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typedef struct {
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u32 PMON;
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u32 NON;
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u32 VMIXL;
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u32 VMIXR;
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u32 VMIXEL;
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u32 VMIXER;
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u16 MMIX;
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u32 ENDX;
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u16 STATX;
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u16 ATTR;
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u16 _1AC;
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} V_CoreRegs;
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typedef struct {
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// Core Voices
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V_Voice Voices[24];
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// Master Volume for Left Channel
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V_Volume MasterL;
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// Master Volume for Right Channel
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V_Volume MasterR;
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// Volume for External Data Input (Left Channel)
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u16 ExtL;
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// Volume for External Data Input (Right Channel)
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u16 ExtR;
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// Volume for Sound Data Input (Left Channel)
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u16 InpL;
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// Volume for Sound Data Input (Right Channel)
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u16 InpR;
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// Volume for Output from Effects (Left Channel)
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u16 FxL;
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// Volume for Output from Effects (Right Channel)
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u16 FxR;
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// Interrupt Address
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u32 IRQA;
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// DMA Transfer Start Address
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u32 TSA;
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// DMA Transfer Data Address (Internal...)
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u32 TDA;
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// External Input to Direct Output (Left)
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s8 ExtDryL;
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// External Input to Direct Output (Right)
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s8 ExtDryR;
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// External Input to Effects (Left)
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s8 ExtWetL;
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// External Input to Effects (Right)
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s8 ExtWetR;
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// Sound Data Input to Direct Output (Left)
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s8 InpDryL;
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// Sound Data Input to Direct Output (Right)
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s8 InpDryR;
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// Sound Data Input to Effects (Left)
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s8 InpWetL;
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// Sound Data Input to Effects (Right)
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s8 InpWetR;
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// Voice Data to Direct Output (Left)
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s8 SndDryL;
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// Voice Data to Direct Output (Right)
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s8 SndDryR;
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// Voice Data to Effects (Left)
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s8 SndWetL;
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// Voice Data to Effects (Right)
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s8 SndWetR;
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// Interrupt Enable
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s8 IRQEnable;
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// DMA related?
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s8 DMABits;
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// Effect Enable
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s8 FxEnable;
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// Noise Clock
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s8 NoiseClk;
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// AutoDMA Status
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u16 AutoDMACtrl;
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// DMA Interrupt Counter
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s32 DMAICounter;
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// Mute
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s8 Mute;
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// Input Buffer
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u32 InputDataLeft;
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u32 InputPos;
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u32 InputDataProgress;
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u8 AdmaInProgress;
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// Reverb
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V_Reverb Revb;
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u32 EffectsStartA;
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u32 EffectsEndA;
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u32 ReverbX;
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// Registers
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V_CoreRegs Regs;
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u8 InitDelay;
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u8 CoreEnabled;
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u8 AttrBit0;
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u8 AttrBit4;
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u8 AttrBit5;
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u16*DMAPtr;
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u32 MADR;
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u32 TADR;
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s16 ADMATempBuffer[0x1000];
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u32 ADMAPV;
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u32 ADMAPL;
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u32 ADMAPR;
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} V_Core;
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extern V_Core Cores[2];
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extern V_SPDIF Spdif;
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// Output Buffer Writing Position (the same for all data);
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extern s16 OutPos;
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// Input Buffer Reading Position (the same for all data);
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extern s16 InputPos;
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// SPU Mixing Cycles ("Ticks mixed" counter)
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extern u32 Cycles;
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extern u8 InpBuff;
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// 1b0 "hack"
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extern u32 Num;
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#endif // DEFS_H_INCLUDED //
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