mirror of https://github.com/PCSX2/pcsx2.git
271 lines
6.1 KiB
C++
271 lines
6.1 KiB
C++
/* ZeroSPU2
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* Copyright (C) 2006-2007 zerofrog
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "zerospu2.h"
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#include <assert.h>
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#include <stdlib.h>
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#include "SoundTouch/SoundTouch.h"
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#include "SoundTouch/WavFile.h"
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void CALLBACK SPU2readDMAMem(u16 *pMem, int size, int core)
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{
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u32 spuaddr;
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int i, dma, offset;
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if ( core == 0)
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{
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dma = 4;
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offset = 0;
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}
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else
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{
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dma = 7;
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offset = 0x0400;
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}
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spuaddr = C_SPUADDR(core);
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SPU2_LOG("SPU2 readDMA%dMem size %x, addr: %x\n", dma, size, pMem);
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for (i=0; i < size; i++)
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{
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*pMem++ = *(u16*)(spu2mem + spuaddr);
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if ((spu2Rs16(REG_C0_CTRL + offset) & 0x40) && (C_IRQA(core) == spuaddr))
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{
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C_SPUADDR_SET(spuaddr, core);
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IRQINFO |= (4 * (core + 1));
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SPU2_LOG("SPU2readDMA%dMem:interrupt\n", dma);
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irqCallbackSPU2();
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}
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spuaddr++; // inc spu addr
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if (spuaddr > 0x0fffff) spuaddr=0; // wrap at 2Mb
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}
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spuaddr += 19; //Transfer Local To Host TSAH/L + Data Size + 20 (already +1'd)
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C_SPUADDR_SET(spuaddr, core);
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// DMA complete
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spu2Ru16(REG_C0_SPUSTAT + offset) &= ~0x80;
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SPUStartCycle[core] = SPUCycles;
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SPUTargetCycle[core] = size;
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interrupt |= (1 << (1 + core));
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}
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void CALLBACK SPU2readDMA4Mem(u16 *pMem, int size)
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{
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LOG_CALLBACK("SPU2readDMA4Mem()\n");
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return SPU2readDMAMem(pMem, size, 0);
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}
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void CALLBACK SPU2readDMA7Mem(u16* pMem, int size)
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{
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LOG_CALLBACK("SPU2readDMA7Mem()\n");
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return SPU2readDMAMem(pMem, size, 1);
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}
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// WRITE
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// AutoDMA's are used to transfer to the DIRECT INPUT area of the spu2 memory
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// Left and Right channels are always interleaved together in the transfer so
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// the AutoDMA's deinterleaves them and transfers them. An interrupt is
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// generated when half of the buffer (256 short-words for left and 256
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// short-words for right ) has been transferred. Another interrupt occurs at
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// the end of the transfer.
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int ADMASWrite(int core)
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{
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u32 spuaddr;
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ADMA *Adma;
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int dma, offset;
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if (core == 0)
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{
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Adma = &Adma4;
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dma = 4;
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offset = 0;
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}
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else
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{
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Adma = &Adma7;
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dma = 7;
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offset = 0x0400;
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}
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if (interrupt & 0x2)
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{
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printf("%d returning for interrupt\n", dma);
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return 0;
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}
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if (Adma->AmountLeft <= 0)
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{
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printf("%d amount left is 0\n", dma);
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return 1;
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}
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assert( Adma->AmountLeft >= 512 );
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spuaddr = C_SPUADDR(core);
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// SPU2 Deinterleaves the Left and Right Channels
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memcpy((s16*)(spu2mem + spuaddr + 0x2000 + offset),(s16*)Adma->MemAddr,512);
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Adma->MemAddr += 256;
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memcpy((s16*)(spu2mem + spuaddr + 0x2200 + offset),(s16*)Adma->MemAddr,512);
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Adma->MemAddr += 256;
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if ((spu2Ru16(REG_C0_CTRL + offset) & 0x40) && ((spuaddr + 0x2400) <= C_IRQA(core) && (spuaddr + 0x2400 + 256) >= C_IRQA(core)))
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{
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IRQINFO |= (4 * (core + 1));
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printf("ADMA %d Mem access:interrupt\n", dma);
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irqCallbackSPU2();
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}
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if ((spu2Ru16(REG_C0_CTRL + offset) & 0x40) && ((spuaddr + 0x2600) <= C_IRQA(core) && (spuaddr + 0x2600 + 256) >= C_IRQA(core)))
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{
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IRQINFO |= (4 * (core + 1));
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printf("ADMA %d Mem access:interrupt\n", dma);
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irqCallbackSPU2();
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}
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spuaddr = (spuaddr + 256) & 511;
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C_SPUADDR_SET(spuaddr, core);
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Adma->AmountLeft -= 512;
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if (Adma->AmountLeft > 0)
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return 0;
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else
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return 1;
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}
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void CALLBACK SPU2writeDMAMem(u16* pMem, int size, int core)
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{
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u32 spuaddr;
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ADMA *Adma;
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int dma, offset;
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if (core == 0)
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{
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Adma = &Adma4;
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dma = 4;
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offset = 0;
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}
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else
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{
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Adma = &Adma7;
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dma = 7;
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offset = 0x0400;
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}
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SPU2_LOG("SPU2 writeDMA%dMem size %x, addr: %x(spu2:%x), ctrl: %x, adma: %x\n", \
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dma, size, pMem, C_SPUADDR(core), spu2Ru16(REG_C0_CTRL + offset), spu2Ru16(REG_C0_ADMAS + offset));
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if ((spu2Ru16(REG_C0_ADMAS + offset) & 0x1 * (core + 1)) && ((spu2Ru16(REG_C0_CTRL + offset) & 0x30) == 0) && size)
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{
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if (!Adma->Enabled ) Adma->Index = 0;
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Adma->MemAddr = pMem;
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Adma->AmountLeft = size;
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SPUTargetCycle[core] = size;
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spu2Ru16(REG_C0_SPUSTAT + offset) &= ~0x80;
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if (!Adma->Enabled || (Adma->Index > 384))
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{
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C_SPUADDR_SET(0, core);
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if (ADMASWrite(core))
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{
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SPUStartCycle[core] = SPUCycles;
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interrupt |= (1 << (1 + core));
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}
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}
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Adma->Enabled = 1;
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return;
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}
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#ifdef _DEBUG
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if ((conf.Log && conf.options & OPTION_RECORDING) && (core == 1))
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LogPacketSound(pMem, 0x8000);
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#endif
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spuaddr = C_SPUADDR(core);
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memcpy((u8*)(spu2mem + spuaddr),(u8*)pMem,size << 1);
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spuaddr += size;
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C_SPUADDR_SET(spuaddr, core);
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if ((spu2Ru16(REG_C0_CTRL + offset)&0x40) && (spuaddr < C_IRQA(core) && (C_IRQA(core) <= (spuaddr+0x20))))
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{
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IRQINFO |= 4 * (core + 1);
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SPU2_LOG("SPU2writeDMA%dMem:interrupt\n", dma);
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irqCallbackSPU2();
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}
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if (spuaddr > 0xFFFFE) spuaddr = 0x2800;
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C_SPUADDR_SET(spuaddr, core);
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MemAddr[core] += size << 1;
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spu2Ru16(REG_C0_SPUSTAT + offset) &= ~0x80;
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SPUStartCycle[core] = SPUCycles;
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SPUTargetCycle[core] = size;
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interrupt |= (1 << (core + 1));
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}
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void CALLBACK SPU2writeDMA4Mem(u16* pMem, int size)
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{
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LOG_CALLBACK("SPU2writeDMA4Mem()\n");
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SPU2writeDMAMem(pMem, size, 0);
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}
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void CALLBACK SPU2writeDMA7Mem(u16* pMem, int size)
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{
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LOG_CALLBACK("SPU2writeDMA7Mem()\n");
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SPU2writeDMAMem(pMem, size, 1);
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}
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void CALLBACK SPU2interruptDMA(int core)
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{
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int dma, offset;
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if (core == 0)
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{
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dma = 4;
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offset = 0;
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}
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else
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{
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dma = 7;
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offset = 0x0400;
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}
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SPU2_LOG("SPU2 interruptDMA%d\n", dma);
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spu2Rs16(REG_C0_CTRL + offset) &= ~0x30;
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spu2Ru16(REG_C0_SPUSTAT + offset) |= 0x80;
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}
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void CALLBACK SPU2interruptDMA4()
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{
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LOG_CALLBACK("SPU2interruptDMA4()\n");
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SPU2interruptDMA(0);
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}
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void CALLBACK SPU2interruptDMA7()
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{
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LOG_CALLBACK("SPU2interruptDMA7()\n");
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SPU2interruptDMA(1);
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} |