mirror of https://github.com/PCSX2/pcsx2.git
424 lines
11 KiB
C++
424 lines
11 KiB
C++
//GiGaHeRz's SPU2 Driver
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//Copyright (c) 2003-2008, David Quintana <gigaherz@gmail.com>
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//
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//This library is free software; you can redistribute it and/or
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//modify it under the terms of the GNU Lesser General Public
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//License as published by the Free Software Foundation; either
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//version 2.1 of the License, or (at your option) any later version.
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//
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//This library is distributed in the hope that it will be useful,
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//but WITHOUT ANY WARRANTY; without even the implied warranty of
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//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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//Lesser General Public License for more details.
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//
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//You should have received a copy of the GNU Lesser General Public
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//License along with this library; if not, write to the Free Software
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//Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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//
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#include "spu2.h"
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extern u8 callirq;
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FILE *DMA4LogFile=0;
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FILE *DMA7LogFile=0;
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FILE *ADMA4LogFile=0;
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FILE *ADMA7LogFile=0;
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FILE *ADMAOutLogFile=0;
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FILE *REGWRTLogFile[2]={0,0};
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int packcount=0;
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u16* MBASE[2] = {0,0};
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u16* DMABaseAddr;
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void DMALogOpen() {
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if(!DMALog()) return;
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DMA4LogFile=fopen(DMA4LogFileName,"wb");
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DMA7LogFile=fopen(DMA7LogFileName,"wb");
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ADMA4LogFile=fopen("logs/adma4.raw","wb");
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ADMA7LogFile=fopen("logs/adma7.raw","wb");
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ADMAOutLogFile=fopen("logs/admaOut.raw","wb");
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//REGWRTLogFile[0]=fopen("logs/RegWrite0.raw","wb");
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//REGWRTLogFile[1]=fopen("logs/RegWrite1.raw","wb");
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}
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void DMA4LogWrite(void *lpData, u32 ulSize) {
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if(!DMALog()) return;
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if (!DMA4LogFile) return;
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fwrite(lpData,ulSize,1,DMA4LogFile);
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}
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void DMA7LogWrite(void *lpData, u32 ulSize) {
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if(!DMALog()) return;
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if (!DMA7LogFile) return;
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fwrite(lpData,ulSize,1,DMA7LogFile);
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}
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void ADMA4LogWrite(void *lpData, u32 ulSize) {
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if(!DMALog()) return;
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if (!ADMA4LogFile) return;
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fwrite(lpData,ulSize,1,ADMA4LogFile);
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}
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void ADMA7LogWrite(void *lpData, u32 ulSize) {
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if(!DMALog()) return;
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if (!ADMA7LogFile) return;
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fwrite(lpData,ulSize,1,ADMA7LogFile);
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}
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void ADMAOutLogWrite(void *lpData, u32 ulSize) {
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if(!DMALog()) return;
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if (!ADMAOutLogFile) return;
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fwrite(lpData,ulSize,1,ADMAOutLogFile);
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}
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void RegWriteLog(u32 core,u16 value)
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{
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if(!DMALog()) return;
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if (!REGWRTLogFile[core]) return;
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fwrite(&value,2,1,REGWRTLogFile[core]);
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}
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void DMALogClose() {
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if(!DMALog()) return;
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if (DMA4LogFile) fclose(DMA4LogFile);
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if (DMA7LogFile) fclose(DMA7LogFile);
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if (REGWRTLogFile[0]) fclose(REGWRTLogFile[0]);
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if (REGWRTLogFile[1]) fclose(REGWRTLogFile[1]);
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if (ADMA4LogFile) fclose(ADMA4LogFile);
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if (ADMA7LogFile) fclose(ADMA7LogFile);
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if (ADMAOutLogFile) fclose(ADMAOutLogFile);
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}
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__forceinline u16 DmaRead(u32 core)
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{
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const u16 ret = (u16)spu2M_Read(Cores[core].TDA);
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Cores[core].TDA++;
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Cores[core].TDA&=0xfffff;
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return ret;
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}
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__forceinline void DmaWrite(u32 core, u16 value)
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{
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spu2M_Write( Cores[core].TSA, value );
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Cores[core].TSA++;
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Cores[core].TSA&=0xfffff;
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}
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void AutoDMAReadBuffer(int core, int mode) //mode: 0= split stereo; 1 = do not split stereo
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{
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int spos=((Cores[core].InputPos+0xff)&0x100); //starting position of the free buffer
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if(core==0)
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ADMA4LogWrite(Cores[core].DMAPtr+Cores[core].InputDataProgress,0x400);
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else
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ADMA7LogWrite(Cores[core].DMAPtr+Cores[core].InputDataProgress,0x400);
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if(mode)
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{
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//hacky :p
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memcpy((Cores[core].ADMATempBuffer+(spos<<1)),Cores[core].DMAPtr+Cores[core].InputDataProgress,0x400);
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Cores[core].MADR+=0x400;
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Cores[core].InputDataLeft-=0x200;
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Cores[core].InputDataProgress+=0x200;
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}
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else
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{
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memcpy((Cores[core].ADMATempBuffer+spos),Cores[core].DMAPtr+Cores[core].InputDataProgress,0x200);
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//memcpy((spu2mem+0x2000+(core<<10)+spos),Cores[core].DMAPtr+Cores[core].InputDataProgress,0x200);
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Cores[core].MADR+=0x200;
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Cores[core].InputDataLeft-=0x100;
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Cores[core].InputDataProgress+=0x100;
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memcpy((Cores[core].ADMATempBuffer+spos+0x200),Cores[core].DMAPtr+Cores[core].InputDataProgress,0x200);
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//memcpy((spu2mem+0x2200+(core<<10)+spos),Cores[core].DMAPtr+Cores[core].InputDataProgress,0x200);
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Cores[core].MADR+=0x200;
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Cores[core].InputDataLeft-=0x100;
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Cores[core].InputDataProgress+=0x100;
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}
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// See ReadInput at mixer.cpp for explanation on the commented out lines
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//
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}
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void StartADMAWrite(int core,u16 *pMem, u32 sz)
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{
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int size=(sz)&(~511);
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if(MsgAutoDMA()) ConLog(" * SPU2: DMA%c AutoDMA Transfer of %d bytes to %x (%02x %x %04x).\n",(core==0)?'4':'7',size<<1,Cores[core].TSA,Cores[core].DMABits,Cores[core].AutoDMACtrl,(~Cores[core].Regs.ATTR)&0x7fff);
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Cores[core].InputDataProgress=0;
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if((Cores[core].AutoDMACtrl&(core+1))==0)
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{
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Cores[core].TSA=0x2000+(core<<10);
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Cores[core].DMAICounter=size;
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}
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else if(size>=512)
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{
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Cores[core].InputDataLeft=size;
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if(Cores[core].AdmaInProgress==0)
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{
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#ifdef PCM24_S1_INTERLEAVE
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if((core==1)&&((PlayMode&8)==8))
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{
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AutoDMAReadBuffer(core,1);
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}
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else
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{
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AutoDMAReadBuffer(core,0);
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}
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#else
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if(((PlayMode&4)==4)&&(core==0))
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Cores[0].InputPos=0;
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AutoDMAReadBuffer(core,0);
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#endif
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if(size==512)
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Cores[core].DMAICounter=size;
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}
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Cores[core].AdmaInProgress=1;
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}
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else
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{
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Cores[core].InputDataLeft=0;
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Cores[core].DMAICounter=1;
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}
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Cores[core].TADR=Cores[core].MADR+(size<<1);
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}
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void DoDMAWrite(int core,u16 *pMem,u32 size)
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{
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// Perform an alignment check.
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// Not really important. Everything should work regardless,
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// but it could be indicative of an emulation foopah elsewhere.
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#ifndef PUBLIC
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uptr pa = ((uptr)pMem)&7;
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uptr pm = Cores[core].TSA&0x7;
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if( pa )
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{
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fprintf(stderr, "* SPU2 DMA Write > Missaligned SOURCE! Core: %d TSA: 0x%x TDA: 0x%x Size: 0x%x\n", core, Cores[core].TSA, Cores[core].TDA, size);
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}
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if( pm )
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{
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fprintf(stderr, "* SPU2 DMA Write > Missaligned TARGET! Core: %d TSA: 0x%x TDA: 0x%x Size: 0x%x\n", core, Cores[core].TSA, Cores[core].TDA, size );
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}
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#endif
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if(core==0)
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DMA4LogWrite(pMem,size<<1);
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else
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DMA7LogWrite(pMem,size<<1);
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if(MsgDMA()) ConLog(" * SPU2: DMA%c Transfer of %d bytes to %x (%02x %x %04x).\n",(core==0)?'4':'7',size<<1,Cores[core].TSA,Cores[core].DMABits,Cores[core].AutoDMACtrl,(~Cores[core].Regs.ATTR)&0x7fff);
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// split the DMA copy into two chunks if needed.
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// Instead of checking the adpcm cache for every word, we check for every ADPCM block.
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// That way we can use the optimized fast write instruction to commit the memory.
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Cores[core].TSA &= 0xfffff;
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u32 buff1end = Cores[core].TSA + size;
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u32 buff2end=0;
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if( buff1end > 0xfffff )
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{
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buff2end = buff1end - 0xfffff;
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buff1end = 0xfffff;
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}
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// Ideally we would only mask bits actually written to, but it's a complex algorithm
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// that is way more work than it's worth. Instead we just mask out entire bytes, which
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// means that in rare cases some games may end up having to re-decode some blocks
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// unnecessarily. To minimize the chance of that, I mask at the byte level instead
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// of the dword level, so at worst there are only 7 extra blocks to the front or back
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// of the DMA transfer that get cleared when they shouldn't be.
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// First Branch needs cleared:
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// It starts at TSA and goes to buff1end.
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const u32 buff1size = (buff1end-Cores[core].TSA);
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memcpy( GetMemPtr( Cores[core].TSA ), pMem, buff1size*2 );
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// Note: When clearing cache flags, the *endpoint* needs to be rounded upward.
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// just rounding the count upward could cause problems if both start and end
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// points are mis-aligned.
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const u32 roundUp = (1<<(3+3))-1;
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const u32 flagTSA = Cores[core].TSA >> (3+3);
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const u32 flagTDA = (buff1end + roundUp) >> (3 + 3); // endpoint, rounded up
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u8* cache = (u8*)pcm_cache_flags;
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memset( &cache[flagTSA], 0, flagTDA - flagTSA );
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if( buff2end > 0 )
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{
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// second branch needs cleared:
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// It starts at the beginning of memory and moves forward to buff2end
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const u32 endpt2 = (buff2end + roundUp) >> (3+3);
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memcpy( GetMemPtr( 0 ), &pMem[buff1size], buff2end*2 );
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memset( pcm_cache_flags, 0, endpt2 );
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Cores[core].TDA = buff2end;
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if(Cores[core].IRQEnable)
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{
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// Flag interrupt?
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// If IRQA occurs between start and dest, flag it.
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// Since the buffer wraps, the conditional might seem odd, but it works.
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if( ( Cores[core].IRQA >= Cores[core].TSA ) ||
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( Cores[core].IRQA <= Cores[core].TDA ) )
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{
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Spdif.Info=4<<core;
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SetIrqCall();
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}
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}
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}
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else
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{
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// Buffer doesn't wrap/overflow!
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// Just set the TDA and check for an IRQ...
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Cores[core].TDA = buff1end;
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if(Cores[core].IRQEnable)
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{
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// Flag interrupt?
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// If IRQA occurs between start and dest, flag it:
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if( ( Cores[core].IRQA >= Cores[core].TSA ) &&
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( Cores[core].IRQA <= Cores[core].TDA ) )
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{
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Spdif.Info=4<<core;
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SetIrqCall();
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}
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}
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}
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Cores[core].TSA=Cores[core].TDA&0xFFFF0;
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Cores[core].DMAICounter=size;
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Cores[core].TADR=Cores[core].MADR+(size<<1);
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}
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void SPU2readDMA(int core, u16* pMem, u32 size)
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{
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if(hasPtr) TimeUpdate(*cPtr);
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u32 i;
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Cores[core].TSA&=~7;
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Cores[core].TDA=Cores[core].TSA;
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for (i=0;i<size;i++)
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pMem[i]=DmaRead(core);
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i=Cores[core].TSA;
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Cores[core].TDA=Cores[core].TSA+size+0x1f;
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Cores[core].TSA=Cores[core].TDA&0xFFFFF;
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if((Cores[core].TDA>0xFFFFF)||((Cores[core].TSA<=Cores[core].IRQA)&&(i>=Cores[core].IRQA))) {
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if(Cores[core].IRQEnable)
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{
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Spdif.Info=4<<core;
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SetIrqCall();
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}
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}
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Cores[core].DMAICounter=size;
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Cores[core].Regs.STATX &= ~0x80;
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//Cores[core].Regs.ATTR |= 0x30;
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Cores[core].TADR=Cores[core].MADR+(size<<1);
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}
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void SPU2writeDMA(int core, u16* pMem, u32 size)
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{
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if(hasPtr) TimeUpdate(*cPtr);
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Cores[core].DMAPtr=pMem;
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if(size<2) {
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//if(dma7callback) dma7callback();
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Cores[core].Regs.STATX &= ~0x80;
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//Cores[core].Regs.ATTR |= 0x30;
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Cores[core].DMAICounter=1;
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return;
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}
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#ifndef PUBLIC
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DebugCores[core].lastsize=size;
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#endif
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Cores[core].TSA&=~7;
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bool adma_enable = ((Cores[core].AutoDMACtrl&(core+1))==(core+1));
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if(adma_enable)
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{
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Cores[core].TSA&=0x1fff;
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StartADMAWrite(core,pMem,size);
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}
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else
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{
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DoDMAWrite(core,pMem,size);
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}
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Cores[core].Regs.STATX &= ~0x80;
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//Cores[core].Regs.ATTR |= 0x30;
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}
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u32 CALLBACK SPU2ReadMemAddr(int core)
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{
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return Cores[core].MADR;
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}
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void CALLBACK SPU2WriteMemAddr(int core,u32 value)
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{
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Cores[core].MADR=value;
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}
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void CALLBACK SPU2setDMABaseAddr(uptr baseaddr)
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{
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DMABaseAddr = (u16*)baseaddr;
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}
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void CALLBACK SPU2readDMA4Mem(u16 *pMem, u32 size) { //size now in 16bit units
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FileLog("[%10d] SPU2 readDMA4Mem size %x\n",Cycles, size<<1);
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SPU2readDMA(0,pMem,size);
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}
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void CALLBACK SPU2writeDMA4Mem(u16* pMem, u32 size) { //size now in 16bit units
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FileLog("[%10d] SPU2 writeDMA4Mem size %x at address %x\n",Cycles, size<<1, Cores[0].TSA);
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#ifdef S2R_ENABLE
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if(!replay_mode)
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s2r_writedma4(Cycles,pMem,size);
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#endif
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SPU2writeDMA(0,pMem,size);
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}
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void CALLBACK SPU2interruptDMA4() {
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FileLog("[%10d] SPU2 interruptDMA4\n",Cycles);
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Cores[0].Regs.STATX |= 0x80;
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//Cores[0].Regs.ATTR &= ~0x30;
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}
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void CALLBACK SPU2readDMA7Mem(u16* pMem, u32 size) {
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FileLog("[%10d] SPU2 readDMA7Mem size %x\n",Cycles, size<<1);
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SPU2readDMA(1,pMem,size);
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}
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void CALLBACK SPU2writeDMA7Mem(u16* pMem, u32 size) {
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FileLog("[%10d] SPU2 writeDMA7Mem size %x at address %x\n",Cycles, size<<1, Cores[1].TSA);
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#ifdef S2R_ENABLE
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if(!replay_mode)
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s2r_writedma7(Cycles,pMem,size);
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#endif
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SPU2writeDMA(1,pMem,size);
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}
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void CALLBACK SPU2interruptDMA7() {
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FileLog("[%10d] SPU2 interruptDMA7\n",Cycles);
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Cores[1].Regs.STATX |= 0x80;
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//Cores[1].Regs.ATTR &= ~0x30;
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}
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