mirror of https://github.com/PCSX2/pcsx2.git
388 lines
11 KiB
C++
388 lines
11 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include "Common.h"
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#include <cmath>
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// Helper Macros
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//****************************************************************
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// IEEE 754 Values
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#define PosInfinity 0x7f800000
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#define NegInfinity 0xff800000
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#define posFmax 0x7F7FFFFF
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#define negFmax 0xFF7FFFFF
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/* Used in compare function to compensate for differences between IEEE 754 and the FPU.
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Setting it to ~0x00000000 = Compares Exact Value. (comment out this macro for faster Exact Compare method)
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Setting it to ~0x00000001 = Discards the least significant bit when comparing.
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Setting it to ~0x00000003 = Discards the least 2 significant bits when comparing... etc.. */
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//#define comparePrecision ~0x00000001
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// Operands
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#define _Ft_ ( ( cpuRegs.code >> 16 ) & 0x1F )
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#define _Fs_ ( ( cpuRegs.code >> 11 ) & 0x1F )
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#define _Fd_ ( ( cpuRegs.code >> 6 ) & 0x1F )
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// Floats
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#define _FtValf_ fpuRegs.fpr[ _Ft_ ].f
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#define _FsValf_ fpuRegs.fpr[ _Fs_ ].f
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#define _FdValf_ fpuRegs.fpr[ _Fd_ ].f
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#define _FAValf_ fpuRegs.ACC.f
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// U32's
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#define _FtValUl_ fpuRegs.fpr[ _Ft_ ].UL
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#define _FsValUl_ fpuRegs.fpr[ _Fs_ ].UL
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#define _FdValUl_ fpuRegs.fpr[ _Fd_ ].UL
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#define _FAValUl_ fpuRegs.ACC.UL
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// S32's - useful for ensuring sign extension when needed.
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#define _FtValSl_ fpuRegs.fpr[ _Ft_ ].SL
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#define _FsValSl_ fpuRegs.fpr[ _Fs_ ].SL
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#define _FdValSl_ fpuRegs.fpr[ _Fd_ ].SL
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#define _FAValSl_ fpuRegs.ACC.SL
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// FPU Control Reg (FCR31)
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#define _ContVal_ fpuRegs.fprc[ 31 ]
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// FCR31 Flags
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#define FPUflagC 0X00800000
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#define FPUflagI 0X00020000
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#define FPUflagD 0X00010000
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#define FPUflagO 0X00008000
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#define FPUflagU 0X00004000
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#define FPUflagSI 0X00000040
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#define FPUflagSD 0X00000020
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#define FPUflagSO 0X00000010
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#define FPUflagSU 0X00000008
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//****************************************************************
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// If we have an infinity value, then Overflow has occured.
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#define checkOverflow(xReg, cFlagsToSet, shouldReturn) { \
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if ( ( xReg & ~0x80000000 ) == PosInfinity ) { \
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/*Console.Warning( "FPU OVERFLOW!: Changing to +/-Fmax!!!!!!!!!!!!\n" );*/ \
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xReg = ( xReg & 0x80000000 ) | posFmax; \
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_ContVal_ |= cFlagsToSet; \
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if ( shouldReturn ) { return; } \
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} \
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}
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// If we have a denormal value, then Underflow has occured.
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#define checkUnderflow(xReg, cFlagsToSet, shouldReturn) { \
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if ( ( ( xReg & 0x7F800000 ) == 0 ) && ( ( xReg & 0x007FFFFF ) != 0 ) ) { \
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/*Console.Warning( "FPU UNDERFLOW!: Changing to +/-0!!!!!!!!!!!!\n" );*/ \
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xReg &= 0x80000000; \
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_ContVal_ |= cFlagsToSet; \
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if ( shouldReturn ) { return; } \
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} \
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}
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/* Checks if Divide by Zero will occur. (z/y = x)
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cFlagsToSet1 = Flags to set if (z != 0)
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cFlagsToSet2 = Flags to set if (z == 0)
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( Denormals are counted as "0" )
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*/
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#define checkDivideByZero(xReg, yDivisorReg, zDividendReg, cFlagsToSet1, cFlagsToSet2, shouldReturn) { \
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if ( ( yDivisorReg & 0x7F800000 ) == 0 ) { \
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_ContVal_ |= ( ( zDividendReg & 0x7F800000 ) == 0 ) ? cFlagsToSet2 : cFlagsToSet1; \
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xReg = ( ( yDivisorReg ^ zDividendReg ) & 0x80000000 ) | posFmax; \
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if ( shouldReturn ) { return; } \
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} \
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}
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/* Clears the "Cause Flags" of the Control/Status Reg
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The "EE Core Users Manual" implies that all the Cause flags are cleared every instruction...
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But, the "EE Core Instruction Set Manual" says that only certain Cause Flags are cleared
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for specific instructions... I'm just setting them to clear when the Instruction Set Manual
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says to... (cottonvibes)
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*/
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#define clearFPUFlags(cFlags) { \
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_ContVal_ &= ~( cFlags ) ; \
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}
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#ifdef comparePrecision
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// This compare discards the least-significant bit(s) in order to solve some rounding issues.
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#define C_cond_S(cond) { \
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FPRreg tempA, tempB; \
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tempA.UL = _FsValUl_ & comparePrecision; \
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tempB.UL = _FtValUl_ & comparePrecision; \
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_ContVal_ = ( ( tempA.f ) cond ( tempB.f ) ) ? \
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( _ContVal_ | FPUflagC ) : \
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( _ContVal_ & ~FPUflagC ); \
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}
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#else
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// Used for Comparing; This compares if the floats are exactly the same.
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#define C_cond_S(cond) { \
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_ContVal_ = ( _FsValf_ cond _FtValf_ ) ? \
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( _ContVal_ | FPUflagC ) : \
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( _ContVal_ & ~FPUflagC ); \
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}
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#endif
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// Conditional Branch
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#define BC1(cond) \
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if ( ( _ContVal_ & FPUflagC ) cond 0 ) { \
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intDoBranch( _BranchTarget_ ); \
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}
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// Conditional Branch
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#define BC1L(cond) \
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if ( ( _ContVal_ & FPUflagC ) cond 0 ) { \
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intDoBranch( _BranchTarget_ ); \
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} else cpuRegs.pc += 4;
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namespace R5900 {
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namespace Interpreter {
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namespace OpcodeImpl {
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namespace COP1 {
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//****************************************************************
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// FPU Opcodes
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//****************************************************************
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float fpuDouble(u32 f)
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{
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switch(f & 0x7f800000){
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case 0x0:
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f &= 0x80000000;
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return *(float*)&f;
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break;
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case 0x7f800000:
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f = (f & 0x80000000)|0x7f7fffff;
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return *(float*)&f;
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break;
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default:
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return *(float*)&f;
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break;
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}
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}
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void ABS_S() {
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_FdValUl_ = _FsValUl_ & 0x7fffffff;
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clearFPUFlags( FPUflagO | FPUflagU );
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}
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void ADD_S() {
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_FdValf_ = fpuDouble( _FsValUl_ ) + fpuDouble( _FtValUl_ );
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checkOverflow( _FdValUl_, FPUflagO | FPUflagSO, 1 );
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checkUnderflow( _FdValUl_, FPUflagU | FPUflagSU, 1 );
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}
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void ADDA_S() {
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_FAValf_ = fpuDouble( _FsValUl_ ) + fpuDouble( _FtValUl_ );
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checkOverflow( _FAValUl_, FPUflagO | FPUflagSO, 1 );
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checkUnderflow( _FAValUl_, FPUflagU | FPUflagSU, 1 );
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}
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void BC1F() {
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BC1(==);
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}
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void BC1FL() {
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BC1L(==); // Equal to 0
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}
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void BC1T() {
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BC1(!=);
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}
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void BC1TL() {
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BC1L(!=); // different from 0
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}
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void C_EQ() {
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C_cond_S(==);
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}
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void C_F() {
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clearFPUFlags( FPUflagC ); //clears C regardless
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}
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void C_LE() {
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C_cond_S(<=);
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}
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void C_LT() {
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C_cond_S(<);
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}
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void CFC1() {
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if ( !_Rt_ || ( (_Fs_ != 0) && (_Fs_ != 31) ) ) return;
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cpuRegs.GPR.r[_Rt_].SD[0] = (s32)fpuRegs.fprc[_Fs_]; // force sign extension to 64 bit
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}
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void CTC1() {
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if ( _Fs_ != 31 ) return;
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fpuRegs.fprc[_Fs_] = cpuRegs.GPR.r[_Rt_].UL[0];
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}
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void CVT_S() {
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_FdValf_ = (float)_FsValSl_;
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_FdValf_ = fpuDouble( _FdValUl_ );
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}
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void CVT_W() {
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if ( ( _FsValUl_ & 0x7F800000 ) <= 0x4E800000 ) { _FdValSl_ = (s32)_FsValf_; }
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else if ( ( _FsValUl_ & 0x80000000 ) == 0 ) { _FdValUl_ = 0x7fffffff; }
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else { _FdValUl_ = 0x80000000; }
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}
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void DIV_S() {
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checkDivideByZero( _FdValUl_, _FtValUl_, _FsValUl_, FPUflagD | FPUflagSD, FPUflagI | FPUflagSI, 1 );
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_FdValf_ = fpuDouble( _FsValUl_ ) / fpuDouble( _FtValUl_ );
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checkOverflow( _FdValUl_, 0, 1);
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checkUnderflow( _FdValUl_, 0, 1 );
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}
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/* The Instruction Set manual has an overly complicated way of
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determining the flags that are set. Hopefully this shorter
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method provides a similar outcome and is faster. (cottonvibes)
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*/
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void MADD_S() {
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FPRreg temp;
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temp.f = fpuDouble( _FsValUl_ ) * fpuDouble( _FtValUl_ );
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_FdValf_ = fpuDouble( _FAValUl_ ) + fpuDouble( temp.UL );
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checkOverflow( _FdValUl_, FPUflagO | FPUflagSO, 1 );
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checkUnderflow( _FdValUl_, FPUflagU | FPUflagSU, 1 );
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}
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void MADDA_S() {
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_FAValf_ += fpuDouble( _FsValUl_ ) * fpuDouble( _FtValUl_ );
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checkOverflow( _FAValUl_, FPUflagO | FPUflagSO, 1 );
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checkUnderflow( _FAValUl_, FPUflagU | FPUflagSU, 1 );
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}
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void MAX_S() {
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_FdValf_ = std::max( _FsValf_, _FtValf_ );
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clearFPUFlags( FPUflagO | FPUflagU );
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}
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void MFC1() {
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if ( !_Rt_ ) return;
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cpuRegs.GPR.r[_Rt_].SD[0] = _FsValSl_; // sign extension into 64bit
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}
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void MIN_S() {
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_FdValf_ = std::min( _FsValf_, _FtValf_ );
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clearFPUFlags( FPUflagO | FPUflagU );
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}
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void MOV_S() {
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_FdValUl_ = _FsValUl_;
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}
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void MSUB_S() {
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FPRreg temp;
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temp.f = fpuDouble( _FsValUl_ ) * fpuDouble( _FtValUl_ );
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_FdValf_ = fpuDouble( _FAValUl_ ) - fpuDouble( temp.UL );
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checkOverflow( _FdValUl_, FPUflagO | FPUflagSO, 1 );
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checkUnderflow( _FdValUl_, FPUflagU | FPUflagSU, 1 );
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}
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void MSUBA_S() {
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_FAValf_ -= fpuDouble( _FsValUl_ ) * fpuDouble( _FtValUl_ );
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checkOverflow( _FAValUl_, FPUflagO | FPUflagSO, 1 );
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checkUnderflow( _FAValUl_, FPUflagU | FPUflagSU, 1 );
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}
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void MTC1() {
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_FsValUl_ = cpuRegs.GPR.r[_Rt_].UL[0];
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}
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void MUL_S() {
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_FdValf_ = fpuDouble( _FsValUl_ ) * fpuDouble( _FtValUl_ );
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checkOverflow( _FdValUl_, FPUflagO | FPUflagSO, 1 );
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checkUnderflow( _FdValUl_, FPUflagU | FPUflagSU, 1 );
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}
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void MULA_S() {
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_FAValf_ = fpuDouble( _FsValUl_ ) * fpuDouble( _FtValUl_ );
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checkOverflow( _FAValUl_, FPUflagO | FPUflagSO, 1 );
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checkUnderflow( _FAValUl_, FPUflagU | FPUflagSU, 1 );
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}
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void NEG_S() {
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_FdValUl_ = (_FsValUl_ ^ 0x80000000);
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clearFPUFlags( FPUflagO | FPUflagU );
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}
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void RSQRT_S() {
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FPRreg temp;
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if ( ( _FtValUl_ & 0x7F800000 ) == 0 ) { // Ft is zero (Denormals are Zero)
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_ContVal_ |= FPUflagD | FPUflagSD;
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_FdValUl_ = ( ( _FsValUl_ ^ _FtValUl_ ) & 0x80000000 ) | posFmax;
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return;
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}
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else if ( _FtValUl_ & 0x80000000 ) { // Ft is negative
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_ContVal_ |= FPUflagI | FPUflagSI;
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temp.f = sqrt( fabs( fpuDouble( _FtValUl_ ) ) );
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_FdValf_ = fpuDouble( _FsValUl_ ) / fpuDouble( temp.UL );
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}
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else { _FdValf_ = fpuDouble( _FsValUl_ ) / sqrt( fpuDouble( _FtValUl_ ) ); } // Ft is positive and not zero
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checkOverflow( _FdValUl_, 0, 1 );
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checkUnderflow( _FdValUl_, 0, 1 );
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}
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void SQRT_S() {
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if ( ( _FtValUl_ & 0xFF800000 ) == 0x80000000 ) { _FdValUl_ = 0x80000000; } // If Ft = -0
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else if ( _FtValUl_ & 0x80000000 ) { // If Ft is Negative
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_ContVal_ |= FPUflagI | FPUflagSI;
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_FdValf_ = sqrt( fabs( fpuDouble( _FtValUl_ ) ) );
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}
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else { _FdValf_ = sqrt( fpuDouble( _FtValUl_ ) ); } // If Ft is Positive
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clearFPUFlags( FPUflagD );
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}
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void SUB_S() {
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_FdValf_ = fpuDouble( _FsValUl_ ) - fpuDouble( _FtValUl_ );
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checkOverflow( _FdValUl_, FPUflagO | FPUflagSO, 1 );
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checkUnderflow( _FdValUl_, FPUflagU | FPUflagSU, 1 );
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}
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void SUBA_S() {
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_FAValf_ = fpuDouble( _FsValUl_ ) - fpuDouble( _FtValUl_ );
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checkOverflow( _FAValUl_, FPUflagO | FPUflagSO, 1 );
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checkUnderflow( _FAValUl_, FPUflagU | FPUflagSU, 1 );
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}
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} // End Namespace COP1
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/////////////////////////////////////////////////////////////////////
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// COP1 (FPU) Load/Store Instructions
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// These are actually EE opcodes but since they're related to FPU registers and such they
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// seem more appropriately located here.
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void LWC1() {
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u32 addr;
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addr = cpuRegs.GPR.r[_Rs_].UL[0] + (s16)(cpuRegs.code & 0xffff); // force sign extension to 32bit
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if (addr & 0x00000003) { Console.Error( "FPU (LWC1 Opcode): Invalid Unaligned Memory Address" ); return; } // Should signal an exception?
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fpuRegs.fpr[_Rt_].UL = memRead32(addr);
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}
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void SWC1() {
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u32 addr;
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addr = cpuRegs.GPR.r[_Rs_].UL[0] + (s16)(cpuRegs.code & 0xffff); // force sign extension to 32bit
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if (addr & 0x00000003) { Console.Error( "FPU (SWC1 Opcode): Invalid Unaligned Memory Address" ); return; } // Should signal an exception?
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memWrite32(addr, fpuRegs.fpr[_Rt_].UL);
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}
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} } }
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