mirror of https://github.com/PCSX2/pcsx2.git
970 lines
30 KiB
C++
970 lines
30 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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RAM
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---
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0x00100000-0x01ffffff this is the physical address for the ram.its cached there
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0x20100000-0x21ffffff uncached
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0x30100000-0x31ffffff uncached & accelerated
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0xa0000000-0xa1ffffff MIRROR might...???
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0x80000000-0x81ffffff MIRROR might... ????
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scratch pad
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----------
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0x70000000-0x70003fff scratch pad
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BIOS
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----
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0x1FC00000 - 0x1FFFFFFF un-cached
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0x9FC00000 - 0x9FFFFFFF cached
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0xBFC00000 - 0xBFFFFFFF un-cached
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*/
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#include "PrecompiledHeader.h"
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#include "IopCommon.h"
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#pragma warning(disable:4799) // No EMMS at end of function
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#include <wx/file.h>
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#include "VUmicro.h"
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#include "GS.h"
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#include "System/PageFaultSource.h"
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#include "ps2/BiosTools.h"
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#ifdef ENABLECACHE
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#include "Cache.h"
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#endif
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int MemMode = 0; // 0 is Kernel Mode, 1 is Supervisor Mode, 2 is User Mode
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void memSetKernelMode() {
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//Do something here
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MemMode = 0;
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}
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void memSetSupervisorMode() {
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}
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void memSetUserMode() {
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}
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u16 ba0R16(u32 mem)
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{
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//MEM_LOG("ba00000 Memory read16 address %x", mem);
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if (mem == 0x1a000006) {
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static int ba6;
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ba6++;
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if (ba6 == 3) ba6 = 0;
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return ba6;
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}
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return 0;
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}
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u8 *psM = NULL; //32mb Main Ram
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u8 *psR = NULL; //4mb rom area
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u8 *psR1 = NULL; //256kb rom1 area (actually 196kb, but can't mask this)
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u8 *psR2 = NULL; // 0x00080000
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u8 *psER = NULL; // 0x001C0000
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u8 *psS = NULL; //0.015 mb, scratch pad
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// Two 1 megabyte (max DMA) buffers for reading and writing to high memory (>32MB).
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// Such accesses are not documented as causing bus errors but as the memory does
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// not exist, reads should continue to return 0 and writes should be discarded.
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// Probably.
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static __aligned16 u8 highmem[0x200000];
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u8 *psMHR = &highmem[0];
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u8 *psMHW = &highmem[0x100000];
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#define CHECK_MEM(mem) //MyMemCheck(mem)
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void MyMemCheck(u32 mem)
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{
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if( mem == 0x1c02f2a0 )
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Console.WriteLn("yo; (mem == 0x1c02f2a0) in MyMemCheck...");
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}
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/////////////////////////////
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// REGULAR MEM START
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/////////////////////////////
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vtlbHandler null_handler;
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vtlbHandler tlb_fallback_0;
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vtlbHandler tlb_fallback_1;
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vtlbHandler tlb_fallback_2;
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vtlbHandler tlb_fallback_3;
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vtlbHandler tlb_fallback_4;
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vtlbHandler tlb_fallback_5;
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vtlbHandler tlb_fallback_6;
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vtlbHandler tlb_fallback_7;
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vtlbHandler tlb_fallback_8;
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vtlbHandler vu0_micro_mem[2]; // 0 - dynarec, 1 - interpreter
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vtlbHandler vu1_micro_mem[2]; // 0 - dynarec, 1 - interpreter
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vtlbHandler hw_by_page[0x10] = { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 };
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vtlbHandler gs_page_0;
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vtlbHandler gs_page_1;
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vtlbHandler iopHw_by_page_01;
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vtlbHandler iopHw_by_page_03;
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vtlbHandler iopHw_by_page_08;
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// Used to remap the VUmicro memory according to the VU0/VU1 dynarec setting.
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// (the VU memory operations are different for recs vs. interpreters)
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void memMapVUmicro()
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{
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vtlb_MapHandler(vu0_micro_mem[CpuVU0->IsInterpreter],0x11000000,0x00004000);
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vtlb_MapHandler(vu1_micro_mem[CpuVU1->IsInterpreter],0x11008000,0x00004000);
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// VU0/VU1 memory
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// (Like IOP memory, these are generally only used by the EE Bios kernel during
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// boot-up. Applications/games are "supposed" to use the thread-safe VIF
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// instead.)
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vtlb_MapBlock(VU0.Mem,0x11004000,0x00004000,0x1000);
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vtlb_MapBlock(VU1.Mem,0x1100c000,0x00004000);
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}
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void memMapPhy()
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{
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// Main memory
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vtlb_MapBlock(psM, 0x00000000,Ps2MemSize::Base);//mirrored on first 256 mb ?
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// High memory, uninstalled on the configuration we emulate
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vtlb_MapHandler(null_handler, Ps2MemSize::Base, 0x10000000 - Ps2MemSize::Base);
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// Various ROMs (all read-only)
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vtlb_MapBlock(psR, 0x1fc00000,Ps2MemSize::Rom);
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vtlb_MapBlock(psR1, 0x1e000000,Ps2MemSize::Rom1);
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vtlb_MapBlock(psR2, 0x1e400000,Ps2MemSize::Rom2);
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vtlb_MapBlock(psER, 0x1e040000,Ps2MemSize::ERom);
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// IOP memory
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// (used by the EE Bios Kernel during initial hardware initialization, Apps/Games
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// are "supposed" to use the thread-safe SIF instead.)
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vtlb_MapBlock(psxM,0x1c000000,0x00800000);
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// Generic Handlers; These fallback to mem* stuff...
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vtlb_MapHandler(tlb_fallback_1,0x10000000,0x10000);
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vtlb_MapHandler(tlb_fallback_7,0x14000000,0x10000);
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vtlb_MapHandler(tlb_fallback_4,0x18000000,0x10000);
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vtlb_MapHandler(tlb_fallback_5,0x1a000000,0x10000);
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vtlb_MapHandler(tlb_fallback_6,0x12000000,0x10000);
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vtlb_MapHandler(tlb_fallback_8,0x1f000000,0x10000);
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vtlb_MapHandler(tlb_fallback_3,0x1f400000,0x10000);
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vtlb_MapHandler(tlb_fallback_2,0x1f800000,0x10000);
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vtlb_MapHandler(tlb_fallback_8,0x1f900000,0x10000);
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// Hardware Register Handlers : specialized/optimized per-page handling of HW register accesses
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// (note that hw_by_page handles are assigned in memReset prior to calling this function)
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vtlb_MapHandler(hw_by_page[0x0], 0x10000000, 0x01000);
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vtlb_MapHandler(hw_by_page[0x1], 0x10001000, 0x01000);
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vtlb_MapHandler(hw_by_page[0x2], 0x10002000, 0x01000);
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vtlb_MapHandler(hw_by_page[0x3], 0x10003000, 0x01000);
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vtlb_MapHandler(hw_by_page[0x4], 0x10004000, 0x01000);
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vtlb_MapHandler(hw_by_page[0x5], 0x10005000, 0x01000);
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vtlb_MapHandler(hw_by_page[0x6], 0x10006000, 0x01000);
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vtlb_MapHandler(hw_by_page[0x7], 0x10007000, 0x01000);
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vtlb_MapHandler(hw_by_page[0xb], 0x1000b000, 0x01000);
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vtlb_MapHandler(hw_by_page[0xe], 0x1000e000, 0x01000);
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vtlb_MapHandler(hw_by_page[0xf], 0x1000f000, 0x01000);
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vtlb_MapHandler(gs_page_0, 0x12000000, 0x01000);
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vtlb_MapHandler(gs_page_1, 0x12001000, 0x01000);
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// "Secret" IOP HW mappings - Used by EE Bios Kernel during boot and generally
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// left untouched after that, as per EE/IOP thread safety rules.
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vtlb_MapHandler(iopHw_by_page_01, 0x1f801000, 0x01000);
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vtlb_MapHandler(iopHw_by_page_03, 0x1f803000, 0x01000);
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vtlb_MapHandler(iopHw_by_page_08, 0x1f808000, 0x01000);
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}
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//Why is this required ?
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void memMapKernelMem()
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{
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//lower 512 mb: direct map
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//vtlb_VMap(0x00000000,0x00000000,0x20000000);
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//0x8* mirror
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vtlb_VMap(0x80000000,0x00000000,0x20000000);
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//0xa* mirror
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vtlb_VMap(0xA0000000,0x00000000,0x20000000);
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}
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//what do do with these ?
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void memMapSupervisorMem()
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{
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}
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void memMapUserMem()
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{
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}
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static mem8_t __fastcall nullRead8(u32 mem) {
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MEM_LOG("Read uninstalled memory at address %08x", mem);
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return 0;
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}
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static mem16_t __fastcall nullRead16(u32 mem) {
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MEM_LOG("Read uninstalled memory at address %08x", mem);
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return 0;
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}
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static mem32_t __fastcall nullRead32(u32 mem) {
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MEM_LOG("Read uninstalled memory at address %08x", mem);
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return 0;
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}
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static void __fastcall nullRead64(u32 mem, mem64_t *out) {
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MEM_LOG("Read uninstalled memory at address %08x", mem);
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*out = 0;
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}
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static void __fastcall nullRead128(u32 mem, mem128_t *out) {
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MEM_LOG("Read uninstalled memory at address %08x", mem);
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*out = 0;
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}
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static void __fastcall nullWrite8(u32 mem, mem8_t value)
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{
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MEM_LOG("Write uninstalled memory at address %08x", mem);
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}
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static void __fastcall nullWrite16(u32 mem, mem16_t value)
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{
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MEM_LOG("Write uninstalled memory at address %08x", mem);
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}
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static void __fastcall nullWrite32(u32 mem, mem32_t value)
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{
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MEM_LOG("Write uninstalled memory at address %08x", mem);
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}
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static void __fastcall nullWrite64(u32 mem, const mem64_t *value)
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{
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MEM_LOG("Write uninstalled memory at address %08x", mem);
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}
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static void __fastcall nullWrite128(u32 mem, const mem128_t *value)
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{
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MEM_LOG("Write uninstalled memory at address %08x", mem);
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}
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template<int p>
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mem8_t __fastcall _ext_memRead8 (u32 mem)
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{
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switch (p)
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{
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case 1: // hwm
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return hwRead8(mem);
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case 3: // psh4
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return psxHw4Read8(mem);
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case 6: // gsm
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return gsRead8(mem);
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case 7: // dev9
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{
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mem8_t retval = DEV9read8(mem & ~0xa4000000);
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Console.WriteLn("DEV9 read8 %8.8lx: %2.2lx", mem & ~0xa4000000, retval);
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return retval;
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}
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}
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MEM_LOG("Unknown Memory Read8 from address %8.8x", mem);
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cpuTlbMissR(mem, cpuRegs.branch);
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return 0;
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}
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template<int p>
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mem16_t __fastcall _ext_memRead16(u32 mem)
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{
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switch (p)
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{
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case 1: // hwm
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return hwRead16(mem);
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case 4: // b80
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MEM_LOG("b800000 Memory read16 address %x", mem);
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return 0;
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case 5: // ba0
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return ba0R16(mem);
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case 6: // gsm
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return gsRead16(mem);
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case 7: // dev9
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{
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mem16_t retval = DEV9read16(mem & ~0xa4000000);
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Console.WriteLn("DEV9 read16 %8.8lx: %4.4lx", mem & ~0xa4000000, retval);
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return retval;
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}
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case 8: // spu2
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return SPU2read(mem);
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}
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MEM_LOG("Unknown Memory read16 from address %8.8x", mem);
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cpuTlbMissR(mem, cpuRegs.branch);
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return 0;
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}
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template<int p>
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mem32_t __fastcall _ext_memRead32(u32 mem)
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{
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switch (p)
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{
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case 6: // gsm
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return gsRead32(mem);
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case 7: // dev9
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{
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mem32_t retval = DEV9read32(mem & ~0xa4000000);
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Console.WriteLn("DEV9 read32 %8.8lx: %8.8lx", mem & ~0xa4000000, retval);
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return retval;
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}
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}
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MEM_LOG("Unknown Memory read32 from address %8.8x (Status=%8.8x)", mem, cpuRegs.CP0.n.Status.val);
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cpuTlbMissR(mem, cpuRegs.branch);
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return 0;
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}
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template<int p>
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void __fastcall _ext_memRead64(u32 mem, mem64_t *out)
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{
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switch (p)
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{
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case 6: // gsm
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*out = gsRead64(mem); return;
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}
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MEM_LOG("Unknown Memory read64 from address %8.8x", mem);
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cpuTlbMissR(mem, cpuRegs.branch);
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}
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template<int p>
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void __fastcall _ext_memRead128(u32 mem, mem128_t *out)
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{
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switch (p)
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{
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//case 1: // hwm
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// hwRead128(mem & ~0xa0000000, out); return;
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case 6: // gsm
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out[0] = gsRead64(mem );
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out[1] = gsRead64(mem+8); return;
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}
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MEM_LOG("Unknown Memory read128 from address %8.8x", mem);
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cpuTlbMissR(mem, cpuRegs.branch);
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}
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template<int p>
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void __fastcall _ext_memWrite8 (u32 mem, mem8_t value)
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{
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switch (p) {
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case 1: // hwm
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hwWrite8(mem, value);
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return;
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case 3: // psh4
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psxHw4Write8(mem, value); return;
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case 6: // gsm
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gsWrite8(mem, value); return;
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case 7: // dev9
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DEV9write8(mem & ~0xa4000000, value);
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Console.WriteLn("DEV9 write8 %8.8lx: %2.2lx", mem & ~0xa4000000, value);
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return;
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}
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MEM_LOG("Unknown Memory write8 to address %x with data %2.2x", mem, value);
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cpuTlbMissW(mem, cpuRegs.branch);
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}
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template<int p>
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void __fastcall _ext_memWrite16(u32 mem, mem16_t value)
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{
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switch (p) {
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case 1: // hwm
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hwWrite16(mem, value);
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return;
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case 5: // ba0
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MEM_LOG("ba00000 Memory write16 to address %x with data %x", mem, value);
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return;
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case 6: // gsm
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gsWrite16(mem, value); return;
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case 7: // dev9
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DEV9write16(mem & ~0xa4000000, value);
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Console.WriteLn("DEV9 write16 %8.8lx: %4.4lx", mem & ~0xa4000000, value);
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return;
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case 8: // spu2
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SPU2write(mem, value); return;
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}
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MEM_LOG("Unknown Memory write16 to address %x with data %4.4x", mem, value);
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cpuTlbMissW(mem, cpuRegs.branch);
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}
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template<int p>
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void __fastcall _ext_memWrite32(u32 mem, mem32_t value)
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{
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switch (p) {
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case 6: // gsm
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gsWrite32(mem, value); return;
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case 7: // dev9
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DEV9write32(mem & ~0xa4000000, value);
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Console.WriteLn("DEV9 write32 %8.8lx: %8.8lx", mem & ~0xa4000000, value);
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return;
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}
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MEM_LOG("Unknown Memory write32 to address %x with data %8.8x", mem, value);
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cpuTlbMissW(mem, cpuRegs.branch);
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}
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template<int p>
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void __fastcall _ext_memWrite64(u32 mem, const mem64_t* value)
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{
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/*switch (p) {
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//case 1: // hwm
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// hwWrite64(mem & ~0xa0000000, *value);
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// return;
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//case 6: // gsm
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// gsWrite64(mem & ~0xa0000000, *value); return;
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}*/
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MEM_LOG("Unknown Memory write64 to address %x with data %8.8x_%8.8x", mem, (u32)(*value>>32), (u32)*value);
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cpuTlbMissW(mem, cpuRegs.branch);
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}
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template<int p>
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void __fastcall _ext_memWrite128(u32 mem, const mem128_t *value)
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{
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/*switch (p) {
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//case 1: // hwm
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// hwWrite128(mem & ~0xa0000000, value);
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// return;
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//case 6: // gsm
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// mem &= ~0xa0000000;
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// gsWrite64(mem, value[0]);
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// gsWrite64(mem+8, value[1]); return;
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}*/
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MEM_LOG("Unknown Memory write128 to address %x with data %8.8x_%8.8x_%8.8x_%8.8x", mem, ((u32*)value)[3], ((u32*)value)[2], ((u32*)value)[1], ((u32*)value)[0]);
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cpuTlbMissW(mem, cpuRegs.branch);
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}
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#define vtlb_RegisterHandlerTempl1(nam,t) vtlb_RegisterHandler(nam##Read8<t>,nam##Read16<t>,nam##Read32<t>,nam##Read64<t>,nam##Read128<t>, \
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nam##Write8<t>,nam##Write16<t>,nam##Write32<t>,nam##Write64<t>,nam##Write128<t>)
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#define vtlb_RegisterHandlerTempl2(nam,t,rec) vtlb_RegisterHandler(nam##Read8<t>,nam##Read16<t>,nam##Read32<t>,nam##Read64<t>,nam##Read128<t>, \
|
|
nam##Write8<t,rec>,nam##Write16<t,rec>,nam##Write32<t,rec>,nam##Write64<t,rec>,nam##Write128<t,rec>)
|
|
|
|
typedef void __fastcall ClearFunc_t( u32 addr, u32 qwc );
|
|
|
|
template<int vunum, bool dynarec>
|
|
static __forceinline void ClearVuFunc( u32 addr, u32 size )
|
|
{
|
|
if( dynarec )
|
|
{
|
|
if( vunum==0 )
|
|
CpuVU0->Clear(addr,size);
|
|
else
|
|
CpuVU1->Clear(addr,size);
|
|
}
|
|
else
|
|
{
|
|
if( vunum==0 )
|
|
CpuVU0->Clear(addr,size);
|
|
else
|
|
CpuVU1->Clear(addr,size);
|
|
}
|
|
}
|
|
|
|
template<int vunum>
|
|
mem8_t __fastcall vuMicroRead8(u32 addr)
|
|
{
|
|
addr&=(vunum==0)?0xfff:0x3fff;
|
|
VURegs* vu=(vunum==0)?&VU0:&VU1;
|
|
|
|
return vu->Micro[addr];
|
|
}
|
|
|
|
template<int vunum>
|
|
mem16_t __fastcall vuMicroRead16(u32 addr)
|
|
{
|
|
addr&=(vunum==0)?0xfff:0x3fff;
|
|
VURegs* vu=(vunum==0)?&VU0:&VU1;
|
|
|
|
return *(u16*)&vu->Micro[addr];
|
|
}
|
|
|
|
template<int vunum>
|
|
mem32_t __fastcall vuMicroRead32(u32 addr)
|
|
{
|
|
addr&=(vunum==0)?0xfff:0x3fff;
|
|
VURegs* vu=(vunum==0)?&VU0:&VU1;
|
|
|
|
return *(u32*)&vu->Micro[addr];
|
|
}
|
|
|
|
template<int vunum>
|
|
void __fastcall vuMicroRead64(u32 addr,mem64_t* data)
|
|
{
|
|
addr&=(vunum==0)?0xfff:0x3fff;
|
|
VURegs* vu=(vunum==0)?&VU0:&VU1;
|
|
|
|
*data=*(u64*)&vu->Micro[addr];
|
|
}
|
|
|
|
template<int vunum>
|
|
void __fastcall vuMicroRead128(u32 addr,mem128_t* data)
|
|
{
|
|
addr&=(vunum==0)?0xfff:0x3fff;
|
|
VURegs* vu=(vunum==0)?&VU0:&VU1;
|
|
|
|
data[0]=*(u64*)&vu->Micro[addr];
|
|
data[1]=*(u64*)&vu->Micro[addr+8];
|
|
}
|
|
|
|
// Profiled VU writes: Happen very infrequently, with exception of BIOS initialization (at most twice per
|
|
// frame in-game, and usually none at all after BIOS), so cpu clears aren't much of a big deal.
|
|
|
|
template<int vunum, bool dynrec>
|
|
void __fastcall vuMicroWrite8(u32 addr,mem8_t data)
|
|
{
|
|
addr &= (vunum==0) ? 0xfff : 0x3fff;
|
|
VURegs& vu = (vunum==0) ? VU0 : VU1;
|
|
|
|
if (vu.Micro[addr]!=data)
|
|
{
|
|
ClearVuFunc<vunum, dynrec>(addr&(~7), 8); // Clear before writing new data (clearing 8 bytes because an instruction is 8 bytes) (cottonvibes)
|
|
vu.Micro[addr]=data;
|
|
}
|
|
}
|
|
|
|
template<int vunum, bool dynrec>
|
|
void __fastcall vuMicroWrite16(u32 addr,mem16_t data)
|
|
{
|
|
addr &= (vunum==0) ? 0xfff : 0x3fff;
|
|
VURegs& vu = (vunum==0) ? VU0 : VU1;
|
|
|
|
if (*(u16*)&vu.Micro[addr]!=data)
|
|
{
|
|
ClearVuFunc<vunum, dynrec>(addr&(~7), 8);
|
|
*(u16*)&vu.Micro[addr]=data;
|
|
}
|
|
}
|
|
|
|
template<int vunum, bool dynrec>
|
|
void __fastcall vuMicroWrite32(u32 addr,mem32_t data)
|
|
{
|
|
addr &= (vunum==0) ? 0xfff : 0x3fff;
|
|
VURegs& vu = (vunum==0) ? VU0 : VU1;
|
|
|
|
if (*(u32*)&vu.Micro[addr]!=data)
|
|
{
|
|
ClearVuFunc<vunum, dynrec>(addr&(~7), 8);
|
|
*(u32*)&vu.Micro[addr]=data;
|
|
}
|
|
}
|
|
|
|
template<int vunum, bool dynrec>
|
|
void __fastcall vuMicroWrite64(u32 addr,const mem64_t* data)
|
|
{
|
|
addr &= (vunum==0) ? 0xfff : 0x3fff;
|
|
VURegs& vu = (vunum==0) ? VU0 : VU1;
|
|
|
|
if (*(u64*)&vu.Micro[addr]!=data[0])
|
|
{
|
|
ClearVuFunc<vunum, dynrec>(addr&(~7), 8);
|
|
*(u64*)&vu.Micro[addr]=data[0];
|
|
}
|
|
}
|
|
|
|
template<int vunum, bool dynrec>
|
|
void __fastcall vuMicroWrite128(u32 addr,const mem128_t* data)
|
|
{
|
|
addr &= (vunum==0) ? 0xfff : 0x3fff;
|
|
VURegs& vu = (vunum==0) ? VU0 : VU1;
|
|
|
|
if (*(u64*)&vu.Micro[addr]!=data[0] || *(u64*)&vu.Micro[addr+8]!=data[1])
|
|
{
|
|
ClearVuFunc<vunum, dynrec>(addr&(~7), 16);
|
|
*(u64*)&vu.Micro[addr]=data[0];
|
|
*(u64*)&vu.Micro[addr+8]=data[1];
|
|
}
|
|
}
|
|
|
|
void memSetPageAddr(u32 vaddr, u32 paddr)
|
|
{
|
|
//Console.WriteLn("memSetPageAddr: %8.8x -> %8.8x", vaddr, paddr);
|
|
|
|
vtlb_VMap(vaddr,paddr,0x1000);
|
|
|
|
}
|
|
|
|
void memClearPageAddr(u32 vaddr)
|
|
{
|
|
//Console.WriteLn("memClearPageAddr: %8.8x", vaddr);
|
|
|
|
vtlb_VMapUnmap(vaddr,0x1000); // -> whut ?
|
|
|
|
#ifdef FULLTLB
|
|
// memLUTRK[vaddr >> 12] = 0;
|
|
// memLUTWK[vaddr >> 12] = 0;
|
|
#endif
|
|
}
|
|
|
|
///////////////////////////////////////////////////////////////////////////
|
|
// PS2 Memory Init / Reset / Shutdown
|
|
|
|
class mmap_PageFaultHandler : public EventListener_PageFault
|
|
{
|
|
protected:
|
|
void OnPageFaultEvent( const PageFaultInfo& info, bool& handled );
|
|
};
|
|
|
|
mmap_PageFaultHandler mmap_faultHandler;
|
|
|
|
static const uint m_allMemSize =
|
|
Ps2MemSize::Rom + Ps2MemSize::Rom1 + Ps2MemSize::Rom2 + Ps2MemSize::ERom +
|
|
Ps2MemSize::Base + Ps2MemSize::Hardware + Ps2MemSize::Scratch;
|
|
|
|
static u8* m_psAllMem = NULL;
|
|
|
|
void memAlloc()
|
|
{
|
|
if( m_psAllMem == NULL )
|
|
m_psAllMem = vtlb_malloc( m_allMemSize, 4096 );
|
|
|
|
if( m_psAllMem == NULL)
|
|
throw Exception::OutOfMemory( "memAlloc > failed to allocate PS2's base ram/rom/scratchpad." );
|
|
|
|
u8* curpos = m_psAllMem;
|
|
psM = curpos; curpos += Ps2MemSize::Base;
|
|
psR = curpos; curpos += Ps2MemSize::Rom;
|
|
psR1 = curpos; curpos += Ps2MemSize::Rom1;
|
|
psR2 = curpos; curpos += Ps2MemSize::Rom2;
|
|
psER = curpos; curpos += Ps2MemSize::ERom;
|
|
psH = curpos; curpos += Ps2MemSize::Hardware;
|
|
psS = curpos; //curpos += Ps2MemSize::Scratch;
|
|
|
|
Source_PageFault.Add( mmap_faultHandler );
|
|
}
|
|
|
|
void memShutdown()
|
|
{
|
|
Source_PageFault.Remove( mmap_faultHandler );
|
|
|
|
vtlb_free( m_psAllMem, m_allMemSize );
|
|
m_psAllMem = NULL;
|
|
psM = psR = psR1 = psR2 = psER = psS = psH = NULL;
|
|
vtlb_Term();
|
|
}
|
|
|
|
void memBindConditionalHandlers()
|
|
{
|
|
if( hw_by_page[0xf] == -1 ) return;
|
|
|
|
vtlbMemR32FP* page0F32( EmuConfig.Speedhacks.IntcStat ? hwRead32_page_0F_INTC_HACK : hwRead32_page_0F );
|
|
vtlbMemR64FP* page0F64( EmuConfig.Speedhacks.IntcStat ? hwRead64_generic_INTC_HACK : hwRead64_generic );
|
|
|
|
vtlb_ReassignHandler( hw_by_page[0xf],
|
|
_ext_memRead8<1>, _ext_memRead16<1>, page0F32, page0F64, hwRead128_generic,
|
|
_ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_page_0F, hwWrite64_generic, hwWrite128_generic
|
|
);
|
|
}
|
|
|
|
// Resets memory mappings, unmaps TLBs, reloads bios roms, etc.
|
|
void memReset()
|
|
{
|
|
// VTLB Protection Preparations.
|
|
//HostSys::MemProtect( m_psAllMem, m_allMemSize, Protect_ReadWrite );
|
|
|
|
// Note!! Ideally the vtlb should only be initialized once, and then subsequent
|
|
// resets of the system hardware would only clear vtlb mappings, but since the
|
|
// rest of the emu is not really set up to support a "soft" reset of that sort
|
|
// we opt for the hard/safe version.
|
|
|
|
memzero_ptr<m_allMemSize>( m_psAllMem );
|
|
#ifdef ENABLECACHE
|
|
memset(pCache,0,sizeof(_cacheS)*64);
|
|
#endif
|
|
|
|
vtlb_Init();
|
|
|
|
null_handler = vtlb_RegisterHandler(nullRead8, nullRead16, nullRead32, nullRead64, nullRead128,
|
|
nullWrite8, nullWrite16, nullWrite32, nullWrite64, nullWrite128);
|
|
|
|
tlb_fallback_0 = vtlb_RegisterHandlerTempl1(_ext_mem,0);
|
|
tlb_fallback_3 = vtlb_RegisterHandlerTempl1(_ext_mem,3);
|
|
tlb_fallback_4 = vtlb_RegisterHandlerTempl1(_ext_mem,4);
|
|
tlb_fallback_5 = vtlb_RegisterHandlerTempl1(_ext_mem,5);
|
|
//tlb_fallback_6 = vtlb_RegisterHandlerTempl1(_ext_mem,6);
|
|
tlb_fallback_7 = vtlb_RegisterHandlerTempl1(_ext_mem,7);
|
|
tlb_fallback_8 = vtlb_RegisterHandlerTempl1(_ext_mem,8);
|
|
|
|
// Dynarec versions of VUs
|
|
vu0_micro_mem[0] = vtlb_RegisterHandlerTempl2(vuMicro,0,true);
|
|
vu1_micro_mem[0] = vtlb_RegisterHandlerTempl2(vuMicro,1,true);
|
|
|
|
// Interpreter versions of VUs
|
|
vu0_micro_mem[1] = vtlb_RegisterHandlerTempl2(vuMicro,0,false);
|
|
vu1_micro_mem[1] = vtlb_RegisterHandlerTempl2(vuMicro,1,false);
|
|
|
|
//////////////////////////////////////////////////////////////////////////////////////////
|
|
// IOP's "secret" Hardware Register mapping, accessible from the EE (and meant for use
|
|
// by debugging or BIOS only). The IOP's hw regs are divided into three main pages in
|
|
// the 0x1f80 segment, and then another oddball page for CDVD in the 0x1f40 segment.
|
|
//
|
|
|
|
using namespace IopMemory;
|
|
|
|
tlb_fallback_2 = vtlb_RegisterHandler(
|
|
iopHwRead8_generic, iopHwRead16_generic, iopHwRead32_generic, _ext_memRead64<2>, _ext_memRead128<2>,
|
|
iopHwWrite8_generic, iopHwWrite16_generic, iopHwWrite32_generic, _ext_memWrite64<2>, _ext_memWrite128<2>
|
|
);
|
|
|
|
iopHw_by_page_01 = vtlb_RegisterHandler(
|
|
iopHwRead8_Page1, iopHwRead16_Page1, iopHwRead32_Page1, _ext_memRead64<2>, _ext_memRead128<2>,
|
|
iopHwWrite8_Page1, iopHwWrite16_Page1, iopHwWrite32_Page1, _ext_memWrite64<2>, _ext_memWrite128<2>
|
|
);
|
|
|
|
iopHw_by_page_03 = vtlb_RegisterHandler(
|
|
iopHwRead8_Page3, iopHwRead16_Page3, iopHwRead32_Page3, _ext_memRead64<2>, _ext_memRead128<2>,
|
|
iopHwWrite8_Page3, iopHwWrite16_Page3, iopHwWrite32_Page3, _ext_memWrite64<2>, _ext_memWrite128<2>
|
|
);
|
|
|
|
iopHw_by_page_08 = vtlb_RegisterHandler(
|
|
iopHwRead8_Page8, iopHwRead16_Page8, iopHwRead32_Page8, _ext_memRead64<2>, _ext_memRead128<2>,
|
|
iopHwWrite8_Page8, iopHwWrite16_Page8, iopHwWrite32_Page8, _ext_memWrite64<2>, _ext_memWrite128<2>
|
|
);
|
|
|
|
|
|
//////////////////////////////////////////////////////////////////////////////////////////
|
|
// psHw Optimized Mappings
|
|
// The HW Registers have been split into pages to improve optimization.
|
|
// Anything not explicitly mapped into one of the hw_by_page handlers will be handled
|
|
// by the default/generic tlb_fallback_1 handler.
|
|
|
|
tlb_fallback_1 = vtlb_RegisterHandler(
|
|
_ext_memRead8<1>, _ext_memRead16<1>, hwRead32_generic, hwRead64_generic, hwRead128_generic,
|
|
_ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_generic, hwWrite64_generic, hwWrite128_generic
|
|
);
|
|
|
|
hw_by_page[0x0] = vtlb_RegisterHandler(
|
|
_ext_memRead8<1>, _ext_memRead16<1>, hwRead32_page_00, hwRead64_page_00, hwRead128_page_00,
|
|
_ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_page_00, hwWrite64_page_00, hwWrite128_generic
|
|
);
|
|
|
|
hw_by_page[0x1] = vtlb_RegisterHandler(
|
|
_ext_memRead8<1>, _ext_memRead16<1>, hwRead32_page_01, hwRead64_page_01, hwRead128_page_01,
|
|
_ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_page_01, hwWrite64_page_01, hwWrite128_generic
|
|
);
|
|
|
|
hw_by_page[0x2] = vtlb_RegisterHandler(
|
|
_ext_memRead8<1>, _ext_memRead16<1>, hwRead32_page_02, hwRead64_page_02, hwRead128_page_02,
|
|
_ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_page_02, hwWrite64_page_02, hwWrite128_generic
|
|
);
|
|
|
|
hw_by_page[0x3] = vtlb_RegisterHandler(
|
|
_ext_memRead8<1>, _ext_memRead16<1>, hwRead32_generic, hwRead64_generic, hwRead128_generic,
|
|
_ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_page_03, hwWrite64_page_03, hwWrite128_generic
|
|
);
|
|
|
|
hw_by_page[0x4] = vtlb_RegisterHandler(
|
|
_ext_memRead8<1>, _ext_memRead16<1>, hwRead32_generic, hwRead64_generic, ReadFIFO_page_4,
|
|
_ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_generic, hwWrite64_generic, WriteFIFO_page_4
|
|
);
|
|
|
|
hw_by_page[0x5] = vtlb_RegisterHandler(
|
|
_ext_memRead8<1>, _ext_memRead16<1>, hwRead32_generic, hwRead64_generic, ReadFIFO_page_5,
|
|
_ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_generic, hwWrite64_generic, WriteFIFO_page_5
|
|
);
|
|
|
|
hw_by_page[0x6] = vtlb_RegisterHandler(
|
|
_ext_memRead8<1>, _ext_memRead16<1>, hwRead32_generic, hwRead64_generic, ReadFIFO_page_6,
|
|
_ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_generic, hwWrite64_generic, WriteFIFO_page_6
|
|
);
|
|
|
|
hw_by_page[0x7] = vtlb_RegisterHandler(
|
|
_ext_memRead8<1>, _ext_memRead16<1>, hwRead32_generic, hwRead64_generic, ReadFIFO_page_7,
|
|
_ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_generic, hwWrite64_generic, WriteFIFO_page_7
|
|
);
|
|
|
|
hw_by_page[0xb] = vtlb_RegisterHandler(
|
|
_ext_memRead8<1>, _ext_memRead16<1>, hwRead32_generic, hwRead64_generic, hwRead128_generic,
|
|
_ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_page_0B, hwWrite64_generic, hwWrite128_generic
|
|
);
|
|
|
|
hw_by_page[0xe] = vtlb_RegisterHandler(
|
|
_ext_memRead8<1>, _ext_memRead16<1>, hwRead32_generic, hwRead64_generic, hwRead128_generic,
|
|
_ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_page_0E, hwWrite64_page_0E, hwWrite128_generic
|
|
);
|
|
|
|
hw_by_page[0xf] = vtlb_NewHandler();
|
|
memBindConditionalHandlers();
|
|
|
|
//////////////////////////////////////////////////////////////////////
|
|
// GS Optimized Mappings
|
|
|
|
tlb_fallback_6 = vtlb_RegisterHandler(
|
|
_ext_memRead8<6>, _ext_memRead16<6>, _ext_memRead32<6>, _ext_memRead64<6>, _ext_memRead128<6>,
|
|
_ext_memWrite8<6>, _ext_memWrite16<6>, _ext_memWrite32<6>, gsWrite64_generic, gsWrite128_generic
|
|
);
|
|
|
|
gs_page_0 = vtlb_RegisterHandler(
|
|
_ext_memRead8<6>, _ext_memRead16<6>, _ext_memRead32<6>, _ext_memRead64<6>, _ext_memRead128<6>,
|
|
_ext_memWrite8<6>, _ext_memWrite16<6>, _ext_memWrite32<6>, gsWrite64_page_00, gsWrite128_page_00
|
|
);
|
|
|
|
gs_page_1 = vtlb_RegisterHandler(
|
|
_ext_memRead8<6>, _ext_memRead16<6>, _ext_memRead32<6>, _ext_memRead64<6>, _ext_memRead128<6>,
|
|
_ext_memWrite8<6>, _ext_memWrite16<6>, _ext_memWrite32<6>, gsWrite64_page_01, gsWrite128_page_01
|
|
);
|
|
|
|
//vtlb_Reset();
|
|
|
|
// reset memLUT (?)
|
|
//vtlb_VMap(0x00000000,0x00000000,0x20000000);
|
|
//vtlb_VMapUnmap(0x20000000,0x60000000);
|
|
|
|
memMapPhy();
|
|
memMapVUmicro();
|
|
memMapKernelMem();
|
|
memMapSupervisorMem();
|
|
memMapUserMem();
|
|
memSetKernelMode();
|
|
|
|
vtlb_VMap(0x00000000,0x00000000,0x20000000);
|
|
vtlb_VMapUnmap(0x20000000,0x60000000);
|
|
|
|
LoadBIOS();
|
|
}
|
|
|
|
//////////////////////////////////////////////////////////////////////////////////////////
|
|
// Memory Protection and Block Checking, vtlb Style!
|
|
//
|
|
// For the first time code is recompiled (executed), the PS2 ram page for that code is
|
|
// protected using Virtual Memory (mprotect). If the game modifies its own code then this
|
|
// protection causes an *exception* to be raised (signal in Linux), which is handled by
|
|
// unprotecting the page and switching the recompiled block to "manual" protection.
|
|
//
|
|
// Manual protection uses a simple brute-force memcmp of the recompiled code to the code
|
|
// currently in RAM for *each time* the block is executed. Fool-proof, but slow, which
|
|
// is why we default to using the exception-based protection scheme described above.
|
|
//
|
|
// Why manual blocks? Because many games contain code and data in the same 4k page, so
|
|
// we *cannot* automatically recompile and reprotect pages, lest we end up recompiling and
|
|
// reprotecting them constantly (Which would be very slow). As a counter, the R5900 side
|
|
// of the block checking code does try to periodically re-protect blocks [going from manual
|
|
// back to protected], so that blocks which underwent a single invalidation don't need to
|
|
// incur a permanent performance penalty.
|
|
//
|
|
// Page Granularity:
|
|
// Fortunately for us MIPS and x86 use the same page granularity for TLB and memory
|
|
// protection, so we can use a 1:1 correspondence when protecting pages. Page granularity
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// is 4096 (4k), which is why you'll see a lot of 0xfff's, >><< 12's, and 0x1000's in the
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// code below.
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//
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enum vtlb_ProtectionMode
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{
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ProtMode_None = 0, // page is 'unaccounted' -- neither protected nor unprotected
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ProtMode_Write, // page is under write protection (exception handler)
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ProtMode_Manual // page is under manual protection (self-checked at execution)
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};
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struct vtlb_PageProtectionInfo
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{
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// Ram De-mapping -- used to convert fully translated/mapped offsets into psM back
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// into their originating ps2 physical ram address. Values are assigned when pages
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// are marked for protection.
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u32 ReverseRamMap;
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vtlb_ProtectionMode Mode;
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};
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static __aligned16 vtlb_PageProtectionInfo m_PageProtectInfo[Ps2MemSize::Base >> 12];
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// returns:
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// -1 - unchecked block (resides in ROM, thus is integrity is constant)
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// 0 - page is using Write protection
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// 1 - page is using manual protection (recompiler must include execution-time
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// self-checking of block integrity)
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//
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int mmap_GetRamPageInfo( u32 paddr )
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{
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paddr &= ~0xfff;
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uptr ptr = (uptr)PSM( paddr );
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uptr rampage = ptr - (uptr)psM;
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if (rampage >= Ps2MemSize::Base)
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return -1; //not in ram, no tracking done ...
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rampage >>= 12;
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return ( m_PageProtectInfo[rampage].Mode == ProtMode_Manual ) ? 1 : 0;
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}
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// paddr - physically mapped address
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void mmap_MarkCountedRamPage( u32 paddr )
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{
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paddr &= ~0xfff;
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uptr ptr = (uptr)PSM( paddr );
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int rampage = (ptr - (uptr)psM) >> 12;
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// Important: reassign paddr here, since TLB changes could alter the paddr->psM mapping
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// (and clear blocks accordingly), but don't necessarily clear the protection status.
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m_PageProtectInfo[rampage].ReverseRamMap = paddr;
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if( m_PageProtectInfo[rampage].Mode == ProtMode_Write )
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return; // skip town if we're already protected.
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|
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DbgCon.WriteLn( Color_Gray, (m_PageProtectInfo[rampage].Mode == ProtMode_Manual) ?
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"dyna_page_reset @ 0x%05x" : "Write-protected page @ 0x%05x",
|
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paddr>>12
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);
|
|
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m_PageProtectInfo[rampage].Mode = ProtMode_Write;
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HostSys::MemProtect( &psM[rampage<<12], __pagesize, Protect_ReadOnly );
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}
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// offset - offset of address relative to psM.
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static __forceinline void mmap_ClearCpuBlock( uint offset )
|
|
{
|
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int rampage = offset >> 12;
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|
|
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// Assertion: This function should never be run on a block that's already under
|
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// manual protection. Indicates a logic error in the recompiler or protection code.
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|
pxAssertMsg( m_PageProtectInfo[rampage].Mode != ProtMode_Manual,
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"Attempted to clear a block that is already under manual protection." );
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|
|
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HostSys::MemProtect( &psM[rampage<<12], __pagesize, Protect_ReadWrite );
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m_PageProtectInfo[rampage].Mode = ProtMode_Manual;
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Cpu->Clear( m_PageProtectInfo[rampage].ReverseRamMap, 0x400 );
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}
|
|
|
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void mmap_PageFaultHandler::OnPageFaultEvent( const PageFaultInfo& info, bool& handled )
|
|
{
|
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// get bad virtual address
|
|
uptr offset = info.addr - (uptr)psM;
|
|
if( offset >= Ps2MemSize::Base ) return;
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|
|
|
mmap_ClearCpuBlock( offset );
|
|
handled = true;
|
|
}
|
|
|
|
// Clears all block tracking statuses, manual protection flags, and write protection.
|
|
// This does not clear any recompiler blocks. It is assumed (and necessary) for the caller
|
|
// to ensure the EErec is also reset in conjunction with calling this function.
|
|
void mmap_ResetBlockTracking()
|
|
{
|
|
DevCon.WriteLn( "vtlb/mmap: Block Tracking reset..." );
|
|
memzero( m_PageProtectInfo );
|
|
HostSys::MemProtect( psM, Ps2MemSize::Base, Protect_ReadWrite );
|
|
}
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