mirror of https://github.com/PCSX2/pcsx2.git
762 lines
20 KiB
C++
762 lines
20 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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// Note on INTC usage: All counters code is always called from inside the context of an
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// event test, so instead of using the iopTestIntc we just set the 0x1070 flags directly.
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// The EventText function will pick it up.
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#include "PrecompiledHeader.h"
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#include "IopCommon.h"
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#include <math.h>
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/* Config.PsxType == 1: PAL:
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VBlank interlaced 50.00 Hz
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VBlank non-interlaced 49.76 Hz
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HBlank 15.625 KHz
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Config.PsxType == 0: NSTC
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VBlank interlaced 59.94 Hz
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VBlank non-interlaced 59.82 Hz
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HBlank 15.73426573 KHz */
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// Misc IOP Clocks
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#define PSXPIXEL ((int)(PSXCLK / 13500000))
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#define PSXSOUNDCLK ((int)(48000))
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psxCounter psxCounters[NUM_COUNTERS];
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s32 psxNextCounter;
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u32 psxNextsCounter;
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u8 psxhblankgate = 0;
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u8 psxvblankgate = 0;
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// flags when the gate is off or counter disabled. (do not count)
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#define IOPCNT_STOPPED (0x10000000ul)
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// used to disable targets until after an overflow
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#define IOPCNT_FUTURE_TARGET (0x1000000000ULL)
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#define IOPCNT_ENABLE_GATE (1<<0) // enables gate-based counters
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#define IOPCNT_INT_TARGET (1<<4) // 0x10 triggers an interrupt on targets
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#define IOPCNT_INT_OVERFLOW (1<<5) // 0x20 triggers an interrupt on overflows
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#define IOPCNT_ALT_SOURCE (1<<8) // 0x100 uses hblank on counters 1 and 3, and PSXCLOCK on counter 0
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// Use an arbitrary value to flag HBLANK counters.
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// These counters will be counted by the hblank gates coming from the EE,
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// which ensures they stay 100% in sync with the EE's hblank counters.
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#define PSXHBLANK 0x2001
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static void psxRcntReset(int index)
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{
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psxCounters[index].count = 0;
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psxCounters[index].mode&= ~0x18301C00;
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psxCounters[index].sCycleT = psxRegs.cycle;
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}
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static void _rcntSet( int cntidx )
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{
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u64 overflowCap = (cntidx>=3) ? 0x100000000ULL : 0x10000;
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u64 c;
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const psxCounter& counter = psxCounters[cntidx];
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// psxNextCounter is relative to the psxRegs.cycle when rcntUpdate() was last called.
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// However, the current _rcntSet could be called at any cycle count, so we need to take
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// that into account. Adding the difference from that cycle count to the current one
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// will do the trick!
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if( counter.mode & IOPCNT_STOPPED || counter.rate == PSXHBLANK) return;
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// check for special cases where the overflow or target has just passed
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// (we probably missed it because we're doing/checking other things)
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if( counter.count > overflowCap || counter.count > counter.target )
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{
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psxNextCounter = 4;
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return;
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}
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c = (u64)((overflowCap - counter.count) * counter.rate) - (psxRegs.cycle - counter.sCycleT);
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c += psxRegs.cycle - psxNextsCounter; // adjust for time passed since last rcntUpdate();
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if(c < (u64)psxNextCounter)
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{
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psxNextCounter = (u32)c;
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psxSetNextBranch( psxNextsCounter, psxNextCounter ); //Need to update on counter resets/target changes
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}
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//if((counter.mode & 0x10) == 0 || psxCounters[i].target > 0xffff) continue;
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if( counter.target & IOPCNT_FUTURE_TARGET ) return;
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c = (s64)((counter.target - counter.count) * counter.rate) - (psxRegs.cycle - counter.sCycleT);
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c += psxRegs.cycle - psxNextsCounter; // adjust for time passed since last rcntUpdate();
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if(c < (u64)psxNextCounter)
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{
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psxNextCounter = (u32)c;
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psxSetNextBranch( psxNextsCounter, psxNextCounter ); //Need to update on counter resets/target changes
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}
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}
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void psxRcntInit() {
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int i;
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memzero( psxCounters );
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for (i=0; i<3; i++) {
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psxCounters[i].rate = 1;
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psxCounters[i].mode|= 0x0400;
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psxCounters[i].target = IOPCNT_FUTURE_TARGET;
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}
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for (i=3; i<6; i++) {
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psxCounters[i].rate = 1;
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psxCounters[i].mode|= 0x0400;
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psxCounters[i].target = IOPCNT_FUTURE_TARGET;
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}
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psxCounters[0].interrupt = 0x10;
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psxCounters[1].interrupt = 0x20;
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psxCounters[2].interrupt = 0x40;
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psxCounters[3].interrupt = 0x04000;
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psxCounters[4].interrupt = 0x08000;
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psxCounters[5].interrupt = 0x10000;
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if (SPU2async != NULL)
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{
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psxCounters[6].rate = 768*12;
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psxCounters[6].CycleT = psxCounters[6].rate;
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psxCounters[6].mode = 0x8;
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}
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if (USBasync != NULL)
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{
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psxCounters[7].rate = PSXCLK/1000;
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psxCounters[7].CycleT = psxCounters[7].rate;
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psxCounters[7].mode = 0x8;
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}
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#ifdef ENABLE_NEW_IOPDMA
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psxCounters[8].rate = 2000;
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psxCounters[8].CycleT = psxCounters[7].rate;
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psxCounters[8].mode = 0x8;
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#endif
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for (i=0; i<8; i++)
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psxCounters[i].sCycleT = psxRegs.cycle;
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// Tell the IOP to branch ASAP, so that timers can get
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// configured properly.
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psxNextCounter = 1;
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psxNextsCounter = psxRegs.cycle;
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}
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static void __fastcall _rcntTestTarget( int i )
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{
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if( psxCounters[i].count < psxCounters[i].target ) return;
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PSXCNT_LOG("IOP Counter[%d] target 0x%I64x >= 0x%I64x (mode: %x)",
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i, psxCounters[i].count, psxCounters[i].target, psxCounters[i].mode);
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if (psxCounters[i].mode & IOPCNT_INT_TARGET)
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{
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// Target interrupt
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if(psxCounters[i].mode & 0x80)
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psxCounters[i].mode &= ~0x0400; // Interrupt flag
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psxCounters[i].mode |= 0x0800; // Target flag
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psxHu32(0x1070) |= psxCounters[i].interrupt;
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}
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if (psxCounters[i].mode & 0x08)
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{
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// Reset on target
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psxCounters[i].count -= psxCounters[i].target;
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if(!(psxCounters[i].mode & 0x40))
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{
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Console.WriteLn("Counter %x repeat intr not set on zero ret, ignoring target", i);
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psxCounters[i].target |= IOPCNT_FUTURE_TARGET;
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}
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} else psxCounters[i].target |= IOPCNT_FUTURE_TARGET;
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}
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static __forceinline void _rcntTestOverflow( int i )
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{
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u64 maxTarget = ( i < 3 ) ? 0xffff : 0xfffffffful;
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if( psxCounters[i].count <= maxTarget ) return;
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PSXCNT_LOG("IOP Counter[%d] overflow 0x%I64x >= 0x%I64x (mode: %x)",
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i, psxCounters[i].count, maxTarget, psxCounters[i].mode );
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if(psxCounters[i].mode & IOPCNT_INT_OVERFLOW)
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{
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// Overflow interrupt
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psxHu32(0x1070) |= psxCounters[i].interrupt;
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psxCounters[i].mode |= 0x1000; // Overflow flag
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if(psxCounters[i].mode & 0x80)
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psxCounters[i].mode &= ~0x0400; // Interrupt flag
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}
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// Update count and target.
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// Count wraps around back to zero, while the target is restored (if needed).
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// (high bit of the target gets set by rcntWtarget when the target is behind
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// the counter value, and thus should not be flagged until after an overflow)
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psxCounters[i].count &= maxTarget;
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psxCounters[i].target &= maxTarget;
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}
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/*
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Gate:
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TM_NO_GATE 000
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TM_GATE_ON_Count 001
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TM_GATE_ON_ClearStart 011
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TM_GATE_ON_Clear_OFF_Start 101
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TM_GATE_ON_Start 111
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V-blank ----+ +----------------------------+ +------
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+----+ +----+
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TM_NO_GATE:
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0================================>============
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TM_GATE_ON_Count:
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<---->0==========================><---->0=====
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TM_GATE_ON_ClearStart:
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0====>0================================>0=====
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TM_GATE_ON_Clear_OFF_Start:
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0====><-------------------------->0====><-----
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TM_GATE_ON_Start:
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<---->0==========================>============
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*/
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static void _psxCheckStartGate( int i )
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{
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if(!(psxCounters[i].mode & IOPCNT_ENABLE_GATE)) return; //Ignore Gate
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switch((psxCounters[i].mode & 0x6) >> 1)
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{
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case 0x0: //GATE_ON_count - stop count on gate start:
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// get the current count at the time of stoppage:
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psxCounters[i].count = ( i < 3 ) ?
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psxRcntRcount16( i ) : psxRcntRcount32( i );
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psxCounters[i].mode |= IOPCNT_STOPPED;
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return;
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case 0x1: //GATE_ON_ClearStart - count normally with resets after every end gate
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// do nothing - All counting will be done on a need-to-count basis.
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return;
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case 0x2: //GATE_ON_Clear_OFF_Start - start counting on gate start, stop on gate end
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psxCounters[i].count = 0;
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psxCounters[i].sCycleT = psxRegs.cycle;
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psxCounters[i].mode &= ~IOPCNT_STOPPED;
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break;
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case 0x3: //GATE_ON_Start - start and count normally on gate end (no restarts or stops or clears)
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// do nothing!
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return;
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}
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_rcntSet( i );
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}
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static void _psxCheckEndGate(int i)
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{
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if(!(psxCounters[i].mode & IOPCNT_ENABLE_GATE)) return; //Ignore Gate
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switch((psxCounters[i].mode & 0x6) >> 1)
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{
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case 0x0: //GATE_ON_count - reset and start counting
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case 0x1: //GATE_ON_ClearStart - count normally with resets after every end gate
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psxCounters[i].count = 0;
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psxCounters[i].sCycleT = psxRegs.cycle;
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psxCounters[i].mode &= ~IOPCNT_STOPPED;
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break;
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case 0x2: //GATE_ON_Clear_OFF_Start - start counting on gate start, stop on gate end
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psxCounters[i].count = ( i < 3 ) ?
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psxRcntRcount16( i ) : psxRcntRcount32( i );
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psxCounters[i].mode |= IOPCNT_STOPPED;
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return; // do not set the counter
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case 0x3: //GATE_ON_Start - start and count normally (no restarts or stops or clears)
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if( psxCounters[i].mode & IOPCNT_STOPPED )
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{
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psxCounters[i].count = 0;
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psxCounters[i].sCycleT = psxRegs.cycle;
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psxCounters[i].mode &= ~IOPCNT_STOPPED;
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}
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break;
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}
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_rcntSet( i );
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}
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void psxCheckStartGate16(int i)
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{
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pxAssert( i < 3 );
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if(i == 0) // hSync counting...
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{
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// AlternateSource/scanline counters for Gates 1 and 3.
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// We count them here so that they stay nicely synced with the EE's hsync.
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const u32 altSourceCheck = IOPCNT_ALT_SOURCE | IOPCNT_ENABLE_GATE;
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const u32 stoppedGateCheck = (IOPCNT_STOPPED | altSourceCheck );
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// count if alt source is enabled and either:
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// * the gate is enabled and not stopped.
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// * the gate is disabled.
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if( (psxCounters[1].mode & altSourceCheck) == IOPCNT_ALT_SOURCE ||
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(psxCounters[1].mode & stoppedGateCheck ) == altSourceCheck )
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{
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psxCounters[1].count++;
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_rcntTestTarget( 1 );
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_rcntTestOverflow( 1 );
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}
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if( (psxCounters[3].mode & altSourceCheck) == IOPCNT_ALT_SOURCE ||
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(psxCounters[3].mode & stoppedGateCheck ) == altSourceCheck )
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{
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psxCounters[3].count++;
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_rcntTestTarget( 3 );
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_rcntTestOverflow( 3 );
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}
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}
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_psxCheckStartGate( i );
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}
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void psxCheckEndGate16(int i)
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{
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pxAssert(i < 3);
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_psxCheckEndGate( i );
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}
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static void psxCheckStartGate32(int i)
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{
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// 32 bit gate is called for gate 3 only. Ever.
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pxAssert(i == 3);
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_psxCheckStartGate( i );
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}
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static void psxCheckEndGate32(int i)
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{
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pxAssert(i == 3);
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_psxCheckEndGate( i );
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}
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void psxVBlankStart()
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{
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cdvdVsync();
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psxHu32(0x1070) |= 1;
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if(psxvblankgate & (1 << 1)) psxCheckStartGate16(1);
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if(psxvblankgate & (1 << 3)) psxCheckStartGate32(3);
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}
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void psxVBlankEnd()
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{
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psxHu32(0x1070) |= 0x800;
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if(psxvblankgate & (1 << 1)) psxCheckEndGate16(1);
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if(psxvblankgate & (1 << 3)) psxCheckEndGate32(3);
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}
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void psxRcntUpdate()
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{
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int i;
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//u32 change = 0;
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g_psxNextBranchCycle = psxRegs.cycle + 32;
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psxNextCounter = 0x7fffffff;
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psxNextsCounter = psxRegs.cycle;
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for (i=0; i<=5; i++)
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{
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s32 change = psxRegs.cycle - psxCounters[i].sCycleT;
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// don't count disabled or hblank counters...
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// We can't check the ALTSOURCE flag because the PSXCLOCK source *should*
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// be counted here.
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if( psxCounters[i].mode & IOPCNT_STOPPED ) continue;
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if( psxCounters[i].rate == PSXHBLANK ) continue;
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if( change <= 0 ) continue;
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psxCounters[i].count += change / psxCounters[i].rate;
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if(psxCounters[i].rate != 1)
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{
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change -= (change / psxCounters[i].rate) * psxCounters[i].rate;
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psxCounters[i].sCycleT = psxRegs.cycle - change;
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}
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else
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psxCounters[i].sCycleT = psxRegs.cycle;
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}
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// Do target/overflow testing
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// Optimization Note: This approach is very sound. Please do not try to unroll it
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// as the size of the Test functions will cause code cache clutter and slowness.
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for( i=0; i<6; i++ )
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{
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// don't do target/oveflow checks for hblankers. Those
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// checks are done when the counters are updated.
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if( psxCounters[i].rate == PSXHBLANK ) continue;
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if( psxCounters[i].mode & IOPCNT_STOPPED ) continue;
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_rcntTestTarget( i );
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_rcntTestOverflow( i );
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// perform second target test because if we overflowed above it's possible we
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// already shot past our target if it was very near zero.
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//if( psxCounters[i].count >= psxCounters[i].target ) _rcntTestTarget( i );
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}
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if(SPU2async)
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{
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const s32 difference = psxRegs.cycle - psxCounters[6].sCycleT;
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s32 c = psxCounters[6].CycleT;
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if(difference >= psxCounters[6].CycleT)
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{
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SPU2async(difference);
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psxCounters[6].sCycleT = psxRegs.cycle;
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psxCounters[6].CycleT = psxCounters[6].rate;
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}
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else c -= difference;
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psxNextCounter = c;
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}
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if(USBasync)
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{
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const s32 difference = psxRegs.cycle - psxCounters[7].sCycleT;
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s32 c = psxCounters[7].CycleT;
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if(difference >= psxCounters[7].CycleT)
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{
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USBasync(difference);
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psxCounters[7].sCycleT = psxRegs.cycle;
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psxCounters[7].CycleT = psxCounters[7].rate;
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}
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else c -= difference;
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if (c < psxNextCounter) psxNextCounter = c;
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}
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#ifdef ENABLE_NEW_IOPDMA
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// New Iop DMA handler WIP
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{
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const s32 difference = psxRegs.cycle - psxCounters[8].sCycleT;
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s32 c = psxCounters[8].CycleT;
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if(difference >= psxCounters[8].CycleT)
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{
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psxCounters[8].sCycleT = psxRegs.cycle;
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psxCounters[8].CycleT = psxCounters[8].rate;
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IopDmaUpdate(difference);
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}
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else c -= difference;
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if (c < psxNextCounter) psxNextCounter = c;
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}
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#endif
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for (i=0; i<6; i++) _rcntSet( i );
|
|
}
|
|
|
|
//////////////////////////////////////////////////////////////////////////////////////////
|
|
//
|
|
void psxRcntWcount16(int index, u16 value)
|
|
{
|
|
u32 change;
|
|
|
|
pxAssert( index < 3 );
|
|
PSXCNT_LOG("IOP Counter[%d] writeCount16 = %x", index, value);
|
|
|
|
if(psxCounters[index].rate != PSXHBLANK)
|
|
{
|
|
// Re-adjust the sCycleT to match where the counter is currently
|
|
// (remainder of the rate divided into the time passed will do the trick)
|
|
|
|
change = psxRegs.cycle - psxCounters[index].sCycleT;
|
|
psxCounters[index].sCycleT = psxRegs.cycle - (change % psxCounters[index].rate);
|
|
}
|
|
|
|
psxCounters[index].count = value & 0xffff;
|
|
psxCounters[index].target &= 0xffff;
|
|
_rcntSet( index );
|
|
}
|
|
|
|
//////////////////////////////////////////////////////////////////////////////////////////
|
|
//
|
|
void psxRcntWcount32(int index, u32 value)
|
|
{
|
|
u32 change;
|
|
|
|
pxAssert( index >= 3 && index < 6 );
|
|
PSXCNT_LOG("IOP Counter[%d] writeCount32 = %x", index, value);
|
|
|
|
if(psxCounters[index].rate != PSXHBLANK)
|
|
{
|
|
// Re-adjust the sCycleT to match where the counter is currently
|
|
// (remainder of the rate divided into the time passed will do the trick)
|
|
|
|
change = psxRegs.cycle - psxCounters[index].sCycleT;
|
|
psxCounters[index].sCycleT = psxRegs.cycle - (change % psxCounters[index].rate);
|
|
}
|
|
|
|
psxCounters[index].count = value & 0xffffffff;
|
|
psxCounters[index].target &= 0xffffffff;
|
|
_rcntSet( index );
|
|
}
|
|
|
|
//////////////////////////////////////////////////////////////////////////////////////////
|
|
//
|
|
__forceinline void psxRcntWmode16( int index, u32 value )
|
|
{
|
|
PSXCNT_LOG( "IOP Counter[%d] writeMode = 0x%04X", index, value );
|
|
|
|
jASSUME( index >= 0 && index < 3 );
|
|
psxCounter& counter = psxCounters[index];
|
|
|
|
counter.mode = value;
|
|
counter.mode |= 0x0400;
|
|
|
|
if( index == 2 )
|
|
{
|
|
switch(value & 0x200)
|
|
{
|
|
case 0x000: psxCounters[2].rate = 1; break;
|
|
case 0x200: psxCounters[2].rate = 8; break;
|
|
jNO_DEFAULT;
|
|
}
|
|
|
|
if((counter.mode & 0x7) == 0x7 || (counter.mode & 0x7) == 0x1)
|
|
{
|
|
counter.mode |= IOPCNT_STOPPED;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
// Counters 0 and 1 can select PIXEL or HSYNC as an alternate source:
|
|
counter.rate = 1;
|
|
|
|
if(value & IOPCNT_ALT_SOURCE)
|
|
counter.rate = (index==0) ? PSXPIXEL : PSXHBLANK;
|
|
|
|
if(counter.mode & IOPCNT_ENABLE_GATE)
|
|
{
|
|
// gated counters are added up as per the h/vblank timers.
|
|
// (the PIXEL alt source becomes a vsync gate)
|
|
counter.mode |= IOPCNT_STOPPED;
|
|
PSXCNT_LOG( "IOP Counter[%d] Gate Check set, value = 0x%04X", index, value );
|
|
if( index == 0 )
|
|
psxhblankgate |= 1; // fixme: these gate flags should be one var >_<
|
|
else
|
|
psxvblankgate |= 1<<1;
|
|
}
|
|
else
|
|
{
|
|
if( index == 0 )
|
|
psxhblankgate &= ~1;
|
|
else
|
|
psxvblankgate &= ~(1<<1);
|
|
}
|
|
}
|
|
|
|
counter.count = 0;
|
|
counter.sCycleT = psxRegs.cycle;
|
|
counter.target &= 0xffff;
|
|
|
|
_rcntSet( index );
|
|
}
|
|
|
|
//////////////////////////////////////////////////////////////////////////////////////////
|
|
//
|
|
__forceinline void psxRcntWmode32( int index, u32 value )
|
|
{
|
|
PSXCNT_LOG( "IOP Counter[%d] writeMode = 0x%04x", index, value );
|
|
|
|
jASSUME( index >= 3 && index < 6 );
|
|
psxCounter& counter = psxCounters[index];
|
|
|
|
counter.mode = value;
|
|
counter.mode |= 0x0400;
|
|
|
|
if( index == 3 )
|
|
{
|
|
// Counter 3 has the HBlank as an alternate source.
|
|
counter.rate = 1;
|
|
if(value & IOPCNT_ALT_SOURCE)
|
|
counter.rate = PSXHBLANK;
|
|
|
|
if(counter.mode & IOPCNT_ENABLE_GATE)
|
|
{
|
|
PSXCNT_LOG("IOP Counter[3] Gate Check set, value = %x", value);
|
|
counter.mode |= IOPCNT_STOPPED;
|
|
psxvblankgate |= 1<<3;
|
|
}
|
|
else psxvblankgate &= ~(1<<3);
|
|
}
|
|
else
|
|
{
|
|
switch(value & 0x6000)
|
|
{
|
|
case 0x0000: counter.rate = 1; break;
|
|
case 0x2000: counter.rate = 8; break;
|
|
case 0x4000: counter.rate = 16; break;
|
|
case 0x6000: counter.rate = 256; break;
|
|
}
|
|
|
|
// Need to set a rate and target
|
|
if((counter.mode & 0x7) == 0x7 || (counter.mode & 0x7) == 0x1)
|
|
{
|
|
Console.WriteLn( "Gate set on IOP Counter %d, disabling", index );
|
|
counter.mode |= IOPCNT_STOPPED;
|
|
}
|
|
}
|
|
|
|
counter.count = 0;
|
|
counter.sCycleT = psxRegs.cycle;
|
|
counter.target &= 0xffffffff;
|
|
_rcntSet( index );
|
|
}
|
|
|
|
//////////////////////////////////////////////////////////////////////////////////////////
|
|
//
|
|
void psxRcntWtarget16(int index, u32 value)
|
|
{
|
|
pxAssert( index < 3 );
|
|
PSXCNT_LOG("IOP Counter[%d] writeTarget16 = %lx", index, value);
|
|
psxCounters[index].target = value & 0xffff;
|
|
|
|
// protect the target from an early arrival.
|
|
// if the target is behind the current count, then set the target overflow
|
|
// flag, so that the target won't be active until after the next overflow.
|
|
|
|
if(psxCounters[index].target <= psxRcntCycles(index))
|
|
psxCounters[index].target |= IOPCNT_FUTURE_TARGET;
|
|
|
|
_rcntSet( index );
|
|
}
|
|
|
|
void psxRcntWtarget32(int index, u32 value)
|
|
{
|
|
pxAssert( index >= 3 && index < 6);
|
|
PSXCNT_LOG("IOP Counter[%d] writeTarget32 = %lx", index, value);
|
|
|
|
psxCounters[index].target = value;
|
|
|
|
// protect the target from an early arrival.
|
|
// if the target is behind the current count, then set the target overflow
|
|
// flag, so that the target won't be active until after the next overflow.
|
|
|
|
if(psxCounters[index].target <= psxRcntCycles(index))
|
|
psxCounters[index].target |= IOPCNT_FUTURE_TARGET;
|
|
|
|
_rcntSet( index );
|
|
}
|
|
|
|
u16 psxRcntRcount16(int index)
|
|
{
|
|
u32 retval = (u32)psxCounters[index].count;
|
|
|
|
pxAssert( index < 3 );
|
|
|
|
PSXCNT_LOG("IOP Counter[%d] readCount16 = %lx", index, (u16)retval );
|
|
|
|
// Don't count HBLANK timers
|
|
// Don't count stopped gates either.
|
|
|
|
if( !( psxCounters[index].mode & IOPCNT_STOPPED ) &&
|
|
( psxCounters[index].rate != PSXHBLANK ) )
|
|
{
|
|
u32 delta = (u32)((psxRegs.cycle - psxCounters[index].sCycleT) / psxCounters[index].rate);
|
|
retval += delta;
|
|
PSXCNT_LOG(" (delta = %lx)", delta );
|
|
}
|
|
|
|
return (u16)retval;
|
|
}
|
|
|
|
u32 psxRcntRcount32(int index)
|
|
{
|
|
u32 retval = (u32)psxCounters[index].count;
|
|
|
|
pxAssert( index >= 3 && index < 6 );
|
|
|
|
PSXCNT_LOG("IOP Counter[%d] readCount32 = %lx", index, retval );
|
|
|
|
if( !( psxCounters[index].mode & IOPCNT_STOPPED ) &&
|
|
( psxCounters[index].rate != PSXHBLANK ) )
|
|
{
|
|
u32 delta = (u32)((psxRegs.cycle - psxCounters[index].sCycleT) / psxCounters[index].rate);
|
|
retval += delta;
|
|
PSXCNT_LOG(" (delta = %lx)", delta );
|
|
}
|
|
|
|
return retval;
|
|
}
|
|
|
|
u64 psxRcntCycles(int index)
|
|
{
|
|
if(psxCounters[index].mode & IOPCNT_STOPPED || psxCounters[index].rate == PSXHBLANK ) return psxCounters[index].count;
|
|
return (u64)(psxCounters[index].count + (u32)((psxRegs.cycle - psxCounters[index].sCycleT) / psxCounters[index].rate));
|
|
}
|
|
|
|
void psxRcntSetGates()
|
|
{
|
|
if(psxCounters[0].mode & IOPCNT_ENABLE_GATE)
|
|
psxhblankgate |= 1;
|
|
else
|
|
psxhblankgate &= ~1;
|
|
|
|
if(psxCounters[1].mode & IOPCNT_ENABLE_GATE)
|
|
psxvblankgate |= 1<<1;
|
|
else
|
|
psxvblankgate &= ~(1<<1);
|
|
|
|
if(psxCounters[3].mode & IOPCNT_ENABLE_GATE)
|
|
psxvblankgate |= 1<<3;
|
|
else
|
|
psxvblankgate &= ~(1<<3);
|
|
}
|
|
|
|
void SaveStateBase::psxRcntFreeze()
|
|
{
|
|
FreezeTag( "iopCounters" );
|
|
|
|
Freeze(psxCounters);
|
|
Freeze(psxNextCounter);
|
|
Freeze(psxNextsCounter);
|
|
|
|
if( IsLoading() )
|
|
psxRcntSetGates();
|
|
}
|