mirror of https://github.com/PCSX2/pcsx2.git
384 lines
10 KiB
C++
384 lines
10 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include "Common.h"
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#include "Vif.h"
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#include "Gif_Unit.h"
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#include "Vif_Dma.h"
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u16 vifqwc = 0;
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static u32 qwctag(u32 mask)
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{
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return (dmacRegs.rbor.ADDR + (mask & dmacRegs.rbsr.RMSK));
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}
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static u16 QWCinVIFMFIFO(u32 DrainADDR)
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{
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u32 ret;
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SPR_LOG("VIF MFIFO Requesting %x QWC from the MFIFO Base %x MFIFO Top %x, SPR MADR %x Drain %x", vif1ch.qwc, dmacRegs.rbor.ADDR, dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK + 16, spr0ch.madr, DrainADDR);
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//Calculate what we have in the fifo.
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if(DrainADDR <= spr0ch.madr)
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{
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//Drain is below the tadr, calculate the difference between them
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ret = (spr0ch.madr - DrainADDR) >> 4;
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}
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else
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{
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u32 limit = dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK + 16;
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//Drain is higher than SPR so it has looped round,
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//calculate from base to the SPR tag addr and what is left in the top of the ring
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ret = ((spr0ch.madr - dmacRegs.rbor.ADDR) + (limit - DrainADDR)) >> 4;
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}
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SPR_LOG("%x Available of the %x requested", ret, vif1ch.qwc);
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return ret;
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}
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static __fi bool mfifoVIF1rbTransfer()
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{
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u32 maddr = dmacRegs.rbor.ADDR;
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u32 msize = dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK + 16;
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u16 mfifoqwc = min(QWCinVIFMFIFO(vif1ch.madr), vif1ch.qwc);
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u32 *src;
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bool ret;
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if(mfifoqwc == 0) return true; //Cant do anything, lets forget it
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/* Check if the transfer should wrap around the ring buffer */
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if ((vif1ch.madr + (mfifoqwc << 4)) > (msize))
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{
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int s1 = ((msize) - vif1ch.madr) >> 2;
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SPR_LOG("Split MFIFO");
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/* it does, so first copy 's1' bytes from 'addr' to 'data' */
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vif1ch.madr = qwctag(vif1ch.madr);
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src = (u32*)PSM(vif1ch.madr);
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if (src == NULL) return false;
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if (vif1.irqoffset.enabled)
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ret = VIF1transfer(src + vif1.irqoffset.value, s1 - vif1.irqoffset.value);
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else
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ret = VIF1transfer(src, s1);
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if (ret)
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{
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if(vif1.irqoffset.value != 0) DevCon.Warning("VIF1 MFIFO Offest != 0! vifoffset=%x", vif1.irqoffset.value);
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/* and second copy 's2' bytes from 'maddr' to '&data[s1]' */
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vif1ch.madr = maddr;
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src = (u32*)PSM(maddr);
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if (src == NULL) return false;
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VIF1transfer(src, ((mfifoqwc << 2) - s1));
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}
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}
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else
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{
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SPR_LOG("Direct MFIFO");
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/* it doesn't, so just transfer 'qwc*4' words */
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src = (u32*)PSM(vif1ch.madr);
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if (src == NULL) return false;
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if (vif1.irqoffset.enabled)
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ret = VIF1transfer(src + vif1.irqoffset.value, mfifoqwc * 4 - vif1.irqoffset.value);
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else
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ret = VIF1transfer(src, mfifoqwc << 2);
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}
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return ret;
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}
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static __fi void mfifo_VIF1chain()
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{
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/* Is QWC = 0? if so there is nothing to transfer */
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if ((vif1ch.qwc == 0))
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{
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vif1.inprogress &= ~1;
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return;
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}
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if (vif1ch.madr >= dmacRegs.rbor.ADDR &&
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vif1ch.madr < (dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK + 16))
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{
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//if(vif1ch.madr == (dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK + 16)) DevCon.Warning("Edge VIF1");
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vif1ch.madr = qwctag(vif1ch.madr);
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mfifoVIF1rbTransfer();
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vif1ch.tadr = qwctag(vif1ch.tadr);
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vif1ch.madr = qwctag(vif1ch.madr);
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if(QWCinVIFMFIFO(vif1ch.madr) == 0) vif1.inprogress |= 0x10;
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//vifqwc -= startqwc - vif1ch.qwc;
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}
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else
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{
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tDMA_TAG *pMem = dmaGetAddr(vif1ch.madr, !vif1ch.chcr.DIR);
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SPR_LOG("Non-MFIFO Location");
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//No need to exit on non-mfifo as it is indirect anyway, so it can be transferring this while spr refills the mfifo
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if (pMem == NULL) return;
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if (vif1.irqoffset.enabled)
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VIF1transfer((u32*)pMem + vif1.irqoffset.value, vif1ch.qwc * 4 - vif1.irqoffset.value);
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else
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VIF1transfer((u32*)pMem, vif1ch.qwc << 2);
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}
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}
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void mfifoVifMaskMem(int id)
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{
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switch (id) {
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//These five transfer data following the tag, need to check its within the buffer (Front Mission 4)
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case TAG_CNT:
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case TAG_NEXT:
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case TAG_CALL:
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case TAG_RET:
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case TAG_END:
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if(vif1ch.madr < dmacRegs.rbor.ADDR) //probably not needed but we will check anyway.
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{
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//DevCon.Warning("VIF MFIFO MADR below bottom of ring buffer, wrapping VIF MADR = %x Ring Bottom %x", vif1ch.madr, dmacRegs.rbor.ADDR);
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vif1ch.madr = qwctag(vif1ch.madr);
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}
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if(vif1ch.madr > (dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK)) //Usual scenario is the tag is near the end (Front Mission 4)
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{
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//DevCon.Warning("VIF MFIFO MADR outside top of ring buffer, wrapping VIF MADR = %x Ring Top %x", vif1ch.madr, (dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK)+16);
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vif1ch.madr = qwctag(vif1ch.madr);
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}
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break;
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default:
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//Do nothing as the MADR could be outside
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break;
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}
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}
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void mfifoVIF1transfer(int qwc)
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{
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tDMA_TAG *ptag;
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g_vif1Cycles = 0;
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if (qwc > 0)
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{
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//vifqwc += qwc;
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SPR_LOG("Added %x qw to mfifo,Vif CHCR %x Stalled %x done %x", qwc, vif1ch.chcr._u32, vif1.vifstalled.enabled, vif1.done);
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if (vif1.inprogress & 0x10)
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{
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if(vif1ch.chcr.STR == true && !(cpuRegs.interrupt & (1<<DMAC_MFIFO_VIF)))
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{
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SPR_LOG("Data Added, Resuming");
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CPU_INT(DMAC_MFIFO_VIF, 16);
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}
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//Apparently this is bad, i guess so, the data is going to memory rather than the FIFO
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//vif1Regs.stat.FQC = 0x10; // FQC=16
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}
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vif1.inprogress &= ~0x10;
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return;
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}
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if (vif1ch.qwc == 0)
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{
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vif1ch.tadr = qwctag(vif1ch.tadr);
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ptag = dmaGetAddr(vif1ch.tadr, false);
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if (vif1ch.chcr.TTE)
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{
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bool ret;
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static __aligned16 u128 masked_tag;
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masked_tag._u64[0] = 0;
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masked_tag._u64[1] = *((u64*)ptag + 1);
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VIF_LOG("\tVIF1 SrcChain TTE=1, data = 0x%08x.%08x", masked_tag._u32[3], masked_tag._u32[2]);
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if (vif1.irqoffset.enabled)
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{
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ret = VIF1transfer((u32*)&masked_tag + vif1.irqoffset.value, 4 - vif1.irqoffset.value, true); //Transfer Tag on stall
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//ret = VIF1transfer((u32*)ptag + (2 + vif1.irqoffset), 2 - vif1.irqoffset); //Transfer Tag on stall
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}
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else
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{
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vif1.irqoffset.value = 2;
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vif1.irqoffset.enabled = true;
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ret = VIF1transfer((u32*)&masked_tag + 2, 2, true); //Transfer Tag
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//ret = VIF1transfer((u32*)ptag + 2, 2); //Transfer Tag
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}
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if (!ret && vif1.irqoffset.enabled)
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{
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vif1.inprogress &= ~1;
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return; //IRQ set by VIFTransfer
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} //else vif1.vifstalled.enabled = false;
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g_vif1Cycles += 2;
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}
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vif1.irqoffset.value = 0;
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vif1.irqoffset.enabled = false;
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vif1ch.unsafeTransfer(ptag);
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vif1ch.madr = ptag[1]._u32;
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//vifqwc--;
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SPR_LOG("dmaChain %8.8x_%8.8x size=%d, id=%d, madr=%lx, tadr=%lx mfifo qwc = %x spr0 madr = %x",
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ptag[1]._u32, ptag[0]._u32, vif1ch.qwc, ptag->ID, vif1ch.madr, vif1ch.tadr, vifqwc, spr0ch.madr);
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vif1.done |= hwDmacSrcChainWithStack(vif1ch, ptag->ID);
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mfifoVifMaskMem(ptag->ID);
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if (vif1ch.chcr.TIE && ptag->IRQ)
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{
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VIF_LOG("dmaIrq Set");
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vif1.done = true;
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}
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if(vif1ch.qwc > 0) vif1.inprogress |= 1;
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vif1ch.tadr = qwctag(vif1ch.tadr);
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if(QWCinVIFMFIFO(vif1ch.tadr) == 0) vif1.inprogress |= 0x10;
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}
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else
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{
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DevCon.Warning("Vif MFIFO QWC not 0 on tag");
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}
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SPR_LOG("mfifoVIF1transfer end %x madr %x, tadr %x vifqwc %x", vif1ch.chcr._u32, vif1ch.madr, vif1ch.tadr, vifqwc);
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}
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void vifMFIFOInterrupt()
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{
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g_vif1Cycles = 0;
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VIF_LOG("vif mfifo interrupt");
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if( gifRegs.stat.APATH == 2 && gifUnit.gifPath[1].isDone())
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{
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gifRegs.stat.APATH = 0;
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gifRegs.stat.OPH = 0;
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if(gifUnit.checkPaths(1,0,1)) gifUnit.Execute(false, true);
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}
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if (dmacRegs.ctrl.MFD != MFD_VIF1) {
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DevCon.Warning("Not in VIF MFIFO mode! Stopping VIF MFIFO");
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return;
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}
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if (vif1ch.chcr.DIR) {
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bool isDirect = (vif1.cmd & 0x7f) == 0x50;
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bool isDirectHL = (vif1.cmd & 0x7f) == 0x51;
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if((isDirect && !gifUnit.CanDoPath2())
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|| (isDirectHL && !gifUnit.CanDoPath2HL())) {
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GUNIT_WARN("vifMFIFOInterrupt() - Waiting for Path 2 to be ready");
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CPU_INT(DMAC_MFIFO_VIF, 128);
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return;
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}
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}
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if(vif1.waitforvu == true)
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{
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// DevCon.Warning("Waiting on VU1 MFIFO");
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//CPU_INT(DMAC_MFIFO_VIF, 16);
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return;
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}
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// We need to check the direction, if it is downloading from the GS,
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// we handle that separately (KH2 for testing)
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// Simulated GS transfer time done, clear the flags
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if (vif1.irq && vif1.tag.size == 0) {
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SPR_LOG("VIF MFIFO Code Interrupt detected");
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vif1Regs.stat.INT = true;
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hwIntcIrq(INTC_VIF1);
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--vif1.irq;
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if (vif1Regs.stat.test(VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS)) {
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//vif1Regs.stat.FQC = 0; // FQC=0
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//vif1ch.chcr.STR = false;
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vif1Regs.stat.FQC = min((u16)0x10, vif1ch.qwc);
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if((vif1ch.qwc > 0 || !vif1.done) && !(vif1.inprogress & 0x10)) {
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VIF_LOG("VIF1 MFIFO Stalled");
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return;
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}
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}
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}
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//Mirroring change to VIF0
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if (vif1.cmd) {
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if (vif1.done && vif1ch.qwc == 0) vif1Regs.stat.VPS = VPS_WAITING;
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}
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else {
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vif1Regs.stat.VPS = VPS_IDLE;
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}
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if(vif1.inprogress & 0x10) {
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FireMFIFOEmpty();
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if(!(vif1.done && vif1ch.qwc == 0))return;
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}
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vif1.vifstalled.enabled = false;
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if (vif1.done == false || vif1ch.qwc) {
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switch(vif1.inprogress & 1) {
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case 0: //Set up transfer
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if (QWCinVIFMFIFO(vif1ch.tadr) == 0) {
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vif1.inprogress |= 0x10;
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CPU_INT(DMAC_MFIFO_VIF, 4 );
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return;
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}
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mfifoVIF1transfer(0);
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vif1Regs.stat.FQC = min((u16)0x10, vif1ch.qwc);
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case 1: //Transfer data
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if(vif1.inprogress & 0x1) //Just in case the tag breaks early (or something wierd happens)!
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mfifo_VIF1chain();
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//Sanity check! making sure we always have non-zero values
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if(!(vif1Regs.stat.VGW && gifUnit.gifPath[GIF_PATH_3].state != GIF_PATH_IDLE)) //If we're waiting on GIF, stop looping, (can be over 1000 loops!)
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CPU_INT(DMAC_MFIFO_VIF, (g_vif1Cycles == 0 ? 4 : g_vif1Cycles) );
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vif1Regs.stat.FQC = min((u16)0x10, vif1ch.qwc);
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return;
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}
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return;
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}
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vif1.vifstalled.enabled = false;
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vif1.irqoffset.enabled = false;
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vif1.done = 1;
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g_vif1Cycles = 0;
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vif1Regs.stat.FQC = min((u16)0x10, vif1ch.qwc);
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vif1ch.chcr.STR = false;
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hwDmacIrq(DMAC_VIF1);
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DMA_LOG("VIF1 MFIFO DMA End");
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vif1Regs.stat.FQC = 0;
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}
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