mirror of https://github.com/PCSX2/pcsx2.git
175 lines
6.9 KiB
C++
175 lines
6.9 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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namespace x86Emitter {
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// --------------------------------------------------------------------------------------
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// xImplSimd_MovHL
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// --------------------------------------------------------------------------------------
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// Moves to/from high/low portions of an xmm register.
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// These instructions cannot be used in reg/reg form.
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//
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struct xImplSimd_MovHL
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{
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u16 Opcode;
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void PS( const xRegisterSSE& to, const ModSibBase& from ) const;
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void PS( const ModSibBase& to, const xRegisterSSE& from ) const;
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void PD( const xRegisterSSE& to, const ModSibBase& from ) const;
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void PD( const ModSibBase& to, const xRegisterSSE& from ) const;
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};
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// --------------------------------------------------------------------------------------
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// xImplSimd_MovHL_RtoR
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// --------------------------------------------------------------------------------------
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// RegtoReg forms of MOVHL/MOVLH -- these are the same opcodes as MOVH/MOVL but
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// do something kinda different! Fun!
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//
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struct xImplSimd_MovHL_RtoR
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{
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u16 Opcode;
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void PS( const xRegisterSSE& to, const xRegisterSSE& from ) const;
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void PD( const xRegisterSSE& to, const xRegisterSSE& from ) const;
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};
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// --------------------------------------------------------------------------------------
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// xImplSimd_MoveSSE
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// --------------------------------------------------------------------------------------
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// Legends in their own right: MOVAPS / MOVAPD / MOVUPS / MOVUPD
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//
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// All implementations of Unaligned Movs will, when possible, use aligned movs instead.
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// This happens when using Mem,Reg or Reg,Mem forms where the address is simple displacement
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// which can be checked for alignment at runtime.
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//
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struct xImplSimd_MoveSSE
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{
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u8 Prefix;
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bool isAligned;
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void operator()( const xRegisterSSE& to, const xRegisterSSE& from ) const;
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void operator()( const xRegisterSSE& to, const ModSibBase& from ) const;
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void operator()( const ModSibBase& to, const xRegisterSSE& from ) const;
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};
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// --------------------------------------------------------------------------------------
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// xImplSimd_MoveDQ
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// --------------------------------------------------------------------------------------
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// Implementations for MOVDQA / MOVDQU
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//
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// All implementations of Unaligned Movs will, when possible, use aligned movs instead.
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// This happens when using Mem,Reg or Reg,Mem forms where the address is simple displacement
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// which can be checked for alignment at runtime.
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struct xImplSimd_MoveDQ
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{
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u8 Prefix;
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bool isAligned;
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void operator()( const xRegisterSSE& to, const xRegisterSSE& from ) const;
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void operator()( const xRegisterSSE& to, const ModSibBase& from ) const;
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void operator()( const ModSibBase& to, const xRegisterSSE& from ) const;
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};
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// --------------------------------------------------------------------------------------
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// xImplSimd_Blend
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// --------------------------------------------------------------------------------------
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// Blend - Conditional copying of values in src into dest.
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//
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struct xImplSimd_Blend
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{
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// [SSE-4.1] Conditionally copies dword values from src to dest, depending on the
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// mask bits in the immediate operand (bits [3:0]). Each mask bit corresponds to a
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// dword element in a 128-bit operand.
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//
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// If a mask bit is 1, then the corresponding dword in the source operand is copied
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// to dest, else the dword element in dest is left unchanged.
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//
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xImplSimd_DestRegImmSSE PS;
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// [SSE-4.1] Conditionally copies quadword values from src to dest, depending on the
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// mask bits in the immediate operand (bits [1:0]). Each mask bit corresponds to a
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// quadword element in a 128-bit operand.
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//
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// If a mask bit is 1, then the corresponding dword in the source operand is copied
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// to dest, else the dword element in dest is left unchanged.
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//
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xImplSimd_DestRegImmSSE PD;
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// [SSE-4.1] Conditionally copies dword values from src to dest, depending on the
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// mask (bits [3:0]) in XMM0 (yes, the fixed register). Each mask bit corresponds
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// to a dword element in the 128-bit operand.
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//
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// If a mask bit is 1, then the corresponding dword in the source operand is copied
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// to dest, else the dword element in dest is left unchanged.
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//
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xImplSimd_DestRegSSE VPS;
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// [SSE-4.1] Conditionally copies quadword values from src to dest, depending on the
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// mask (bits [1:0]) in XMM0 (yes, the fixed register). Each mask bit corresponds
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// to a quadword element in the 128-bit operand.
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//
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// If a mask bit is 1, then the corresponding dword in the source operand is copied
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// to dest, else the dword element in dest is left unchanged.
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//
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xImplSimd_DestRegSSE VPD;
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};
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// --------------------------------------------------------------------------------------
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// xImplSimd_PMove
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// --------------------------------------------------------------------------------------
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// Packed Move with Sign or Zero extension.
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//
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struct xImplSimd_PMove
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{
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u16 OpcodeBase;
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// [SSE-4.1] Zero/Sign-extend the low byte values in src into word integers
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// and store them in dest.
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void BW( const xRegisterSSE& to, const xRegisterSSE& from ) const;
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void BW( const xRegisterSSE& to, const ModSib64& from ) const;
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// [SSE-4.1] Zero/Sign-extend the low byte values in src into dword integers
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// and store them in dest.
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void BD( const xRegisterSSE& to, const xRegisterSSE& from ) const;
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void BD( const xRegisterSSE& to, const ModSib32& from ) const;
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// [SSE-4.1] Zero/Sign-extend the low byte values in src into qword integers
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// and store them in dest.
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void BQ( const xRegisterSSE& to, const xRegisterSSE& from ) const;
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void BQ( const xRegisterSSE& to, const ModSib16& from ) const;
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// [SSE-4.1] Zero/Sign-extend the low word values in src into dword integers
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// and store them in dest.
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void WD( const xRegisterSSE& to, const xRegisterSSE& from ) const;
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void WD( const xRegisterSSE& to, const ModSib64& from ) const;
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// [SSE-4.1] Zero/Sign-extend the low word values in src into qword integers
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// and store them in dest.
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void WQ( const xRegisterSSE& to, const xRegisterSSE& from ) const;
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void WQ( const xRegisterSSE& to, const ModSib32& from ) const;
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// [SSE-4.1] Zero/Sign-extend the low dword values in src into qword integers
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// and store them in dest.
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void DQ( const xRegisterSSE& to, const xRegisterSSE& from ) const;
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void DQ( const xRegisterSSE& to, const ModSib64& from ) const;
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};
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}
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