mirror of https://github.com/PCSX2/pcsx2.git
497 lines
12 KiB
C++
497 lines
12 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2009 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include "IopCommon.h"
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#include "Sif.h"
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using namespace R3000A;
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// Dma0/1 in Mdec.c
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// Dma3 in CdRom.c
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// Dma8 in PsxSpd.c
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// Dma11/12 in PsxSio2.c
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bool iopsifbusy[2] = { false, false };
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extern bool eesifbusy[2];
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static void __fastcall psxDmaGeneric(u32 madr, u32 bcr, u32 chcr, u32 spuCore, _SPU2writeDMA4Mem spu2WriteFunc, _SPU2readDMA4Mem spu2ReadFunc)
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{
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const char dmaNum = spuCore ? '7' : '4';
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/*if (chcr & 0x400) DevCon.Status("SPU 2 DMA %c linked list chain mode! chcr = %x madr = %x bcr = %x\n", dmaNum, chcr, madr, bcr);
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if (chcr & 0x40000000) DevCon.Warning("SPU 2 DMA %c Unusual bit set on 'to' direction chcr = %x madr = %x bcr = %x\n", dmaNum, chcr, madr, bcr);
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if ((chcr & 0x1) == 0) DevCon.Status("SPU 2 DMA %c loading from spu2 memory chcr = %x madr = %x bcr = %x\n", dmaNum, chcr, madr, bcr);*/
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const int size = (bcr >> 16) * (bcr & 0xFFFF);
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// Update the spu2 to the current cycle before initiating the DMA
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if (SPU2async)
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{
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SPU2async(psxRegs.cycle - psxCounters[6].sCycleT);
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//Console.Status("cycles sent to SPU2 %x\n", psxRegs.cycle - psxCounters[6].sCycleT);
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psxCounters[6].sCycleT = psxRegs.cycle;
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psxCounters[6].CycleT = size * 3;
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psxNextCounter -= (psxRegs.cycle - psxNextsCounter);
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psxNextsCounter = psxRegs.cycle;
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if (psxCounters[6].CycleT < psxNextCounter)
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psxNextCounter = psxCounters[6].CycleT;
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if((g_psxNextBranchCycle - psxNextsCounter) > (u32)psxNextCounter)
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{
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//DevCon.Warning("SPU2async Setting new counter branch, old %x new %x ((%x - %x = %x) > %x delta)", g_psxNextBranchCycle, psxNextsCounter + psxNextCounter, g_psxNextBranchCycle, psxNextsCounter, (g_psxNextBranchCycle - psxNextsCounter), psxNextCounter);
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g_psxNextBranchCycle = psxNextsCounter + psxNextCounter;
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}
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}
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switch (chcr)
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{
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case 0x01000201: //cpu to spu2 transfer
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PSXDMA_LOG("*** DMA %c - mem2spu *** %x addr = %x size = %x", dmaNum, chcr, madr, bcr);
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spu2WriteFunc((u16 *)iopPhysMem(madr), size*2);
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break;
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case 0x01000200: //spu2 to cpu transfer
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PSXDMA_LOG("*** DMA %c - spu2mem *** %x addr = %x size = %x", dmaNum, chcr, madr, bcr);
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spu2ReadFunc((u16 *)iopPhysMem(madr), size*2);
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psxCpu->Clear(spuCore ? HW_DMA7_MADR : HW_DMA4_MADR, size);
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break;
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default:
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Console.Error("*** DMA %c - SPU unknown *** %x addr = %x size = %x", dmaNum, chcr, madr, bcr);
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break;
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}
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}
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void psxDma2(u32 madr, u32 bcr, u32 chcr) // GPU
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{
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HW_DMA2_CHCR &= ~0x01000000;
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psxDmaInterrupt(2);
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}
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/* psxDma3 is in CdRom.cpp */
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void psxDma4(u32 madr, u32 bcr, u32 chcr) // SPU2's Core 0
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{
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psxDmaGeneric(madr, bcr, chcr, 0, SPU2writeDMA4Mem, SPU2readDMA4Mem);
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}
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int psxDma4Interrupt()
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{
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HW_DMA4_CHCR &= ~0x01000000;
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psxDmaInterrupt(4);
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iopIntcIrq(9);
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return 1;
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}
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void psxDma6(u32 madr, u32 bcr, u32 chcr)
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{
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u32 *mem = (u32 *)iopPhysMem(madr);
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PSXDMA_LOG("*** DMA 6 - OT *** %lx addr = %lx size = %lx", chcr, madr, bcr);
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if (chcr == 0x11000002)
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{
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while (bcr--)
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{
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*mem-- = (madr - 4) & 0xffffff;
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madr -= 4;
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}
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mem++;
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*mem = 0xffffff;
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}
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else
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{
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// Unknown option
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PSXDMA_LOG("*** DMA 6 - OT unknown *** %lx addr = %lx size = %lx", chcr, madr, bcr);
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}
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HW_DMA6_CHCR &= ~0x01000000;
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psxDmaInterrupt(6);
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}
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void psxDma7(u32 madr, u32 bcr, u32 chcr) // SPU2's Core 1
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{
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psxDmaGeneric(madr, bcr, chcr, 1, SPU2writeDMA7Mem, SPU2readDMA7Mem);
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}
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int psxDma7Interrupt()
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{
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HW_DMA7_CHCR &= ~0x01000000;
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psxDmaInterrupt2(0);
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return 1;
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}
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void psxDma8(u32 madr, u32 bcr, u32 chcr)
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{
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const int size = (bcr >> 16) * (bcr & 0xFFFF) * 8;
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switch (chcr & 0x01000201)
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{
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case 0x01000201: //cpu to dev9 transfer
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PSXDMA_LOG("*** DMA 8 - DEV9 mem2dev9 *** %lx addr = %lx size = %lx", chcr, madr, bcr);
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DEV9writeDMA8Mem((u32*)iopPhysMem(madr), size);
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break;
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case 0x01000200: //dev9 to cpu transfer
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PSXDMA_LOG("*** DMA 8 - DEV9 dev9mem *** %lx addr = %lx size = %lx", chcr, madr, bcr);
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DEV9readDMA8Mem((u32*)iopPhysMem(madr), size);
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break;
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default:
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PSXDMA_LOG("*** DMA 8 - DEV9 unknown *** %lx addr = %lx size = %lx", chcr, madr, bcr);
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break;
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}
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HW_DMA8_CHCR &= ~0x01000000;
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psxDmaInterrupt2(1);
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}
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void psxDma9(u32 madr, u32 bcr, u32 chcr)
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{
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SIF_LOG("IOP: dmaSIF0 chcr = %lx, madr = %lx, bcr = %lx, tadr = %lx", chcr, madr, bcr, HW_DMA9_TADR);
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iopsifbusy[0] = true;
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psHu32(SBUS_F240) |= 0x2000;
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if (eesifbusy[0])
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{
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SIF0Dma();
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psHu32(SBUS_F240) &= ~0x20;
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psHu32(SBUS_F240) &= ~0x2000;
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}
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}
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void psxDma10(u32 madr, u32 bcr, u32 chcr)
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{
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SIF_LOG("IOP: dmaSIF1 chcr = %lx, madr = %lx, bcr = %lx", chcr, madr, bcr);
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iopsifbusy[1] = true;
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psHu32(SBUS_F240) |= 0x4000;
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if (eesifbusy[1])
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{
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XMMRegisters::Freeze();
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SIF1Dma();
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psHu32(SBUS_F240) &= ~0x40;
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psHu32(SBUS_F240) &= ~0x100;
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psHu32(SBUS_F240) &= ~0x4000;
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XMMRegisters::Thaw();
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}
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}
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/* psxDma11 & psxDma 12 are in IopSio2,cpp, along with the appropriate interrupt functions. */
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void dev9Interrupt()
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{
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if ((dev9Handler != NULL) && (dev9Handler() != 1)) return;
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iopIntcIrq(13);
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hwIntcIrq(INTC_SBUS);
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}
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void dev9Irq(int cycles)
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{
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PSX_INT(IopEvt_DEV9, cycles);
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}
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void usbInterrupt()
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{
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if (usbHandler != NULL && (usbHandler() != 1)) return;
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iopIntcIrq(22);
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hwIntcIrq(INTC_SBUS);
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}
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void usbIrq(int cycles)
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{
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PSX_INT(IopEvt_USB, cycles);
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}
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void fwIrq()
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{
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iopIntcIrq(24);
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hwIntcIrq(INTC_SBUS);
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}
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void spu2DMA4Irq()
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{
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SPU2interruptDMA4();
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HW_DMA4_CHCR &= ~0x01000000;
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psxDmaInterrupt(4);
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}
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void spu2DMA7Irq()
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{
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SPU2interruptDMA7();
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HW_DMA7_CHCR &= ~0x01000000;
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psxDmaInterrupt2(0);
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}
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void spu2Irq()
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{
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iopIntcIrq(9);
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hwIntcIrq(INTC_SBUS);
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}
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void iopIntcIrq(uint irqType)
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{
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psxHu32(0x1070) |= 1 << irqType;
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iopTestIntc();
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}
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//////////////////////////////////////////////////////////////////////////////////////////////
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//
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// Gigaherz's "Improved DMA Handling" Engine WIP...
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//
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#ifdef ENABLE_NEW_IOPDMA
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s32 spu2DmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
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{
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// FIXME: change the plugin interfaces so that they are aware of this new dma handler
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/*
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u32 bytes = 1024;
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if(bytesLeft<1024)
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bytes=bytesLeft;
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*/
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u32 bytes=bytesLeft;
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// Update the spu2 to the current cycle before initiating the DMA
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if (SPU2async)
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{
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SPU2async(psxRegs.cycle - psxCounters[6].sCycleT);
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//Console.Status("cycles sent to SPU2 %x\n", psxRegs.cycle - psxCounters[6].sCycleT);
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psxCounters[6].sCycleT = psxRegs.cycle;
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psxCounters[6].CycleT = bytes * 3;
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psxNextCounter -= (psxRegs.cycle - psxNextsCounter);
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psxNextsCounter = psxRegs.cycle;
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if (psxCounters[6].CycleT < psxNextCounter)
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psxNextCounter = psxCounters[6].CycleT;
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}
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if(channel==7)
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SPU2readDMA7Mem((u16 *)data, bytes/2);
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else
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SPU2readDMA4Mem((u16 *)data, bytes/2);
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*bytesProcessed = bytes;
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return 0;
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}
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s32 spu2DmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
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{
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// FIXME: change the plugin interfaces so that they are aware of this new dma handler
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/*
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u32 bytes = 1024;
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if(bytesLeft<1024)
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bytes=bytesLeft;
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*/
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u32 bytes=bytesLeft;
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// Update the spu2 to the current cycle before initiating the DMA
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if (SPU2async)
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{
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SPU2async(psxRegs.cycle - psxCounters[6].sCycleT);
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//Console.Status("cycles sent to SPU2 %x\n", psxRegs.cycle - psxCounters[6].sCycleT);
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psxCounters[6].sCycleT = psxRegs.cycle;
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psxCounters[6].CycleT = bytes * 3;
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psxNextCounter -= (psxRegs.cycle - psxNextsCounter);
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psxNextsCounter = psxRegs.cycle;
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if (psxCounters[6].CycleT < psxNextCounter)
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psxNextCounter = psxCounters[6].CycleT;
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}
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if(channel==7)
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SPU2writeDMA7Mem((u16 *)data, bytes/2);
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else
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SPU2writeDMA4Mem((u16 *)data, bytes/2);
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*bytesProcessed = bytes;
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return 0;
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}
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void spu2DmaInterrupt(s32 channel)
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{
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if(channel==7)
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SPU2interruptDMA7();
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else
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SPU2interruptDMA4();
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}
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//typedef s32(* DmaHandler)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
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//typedef void (* DmaIHandler)(s32 channel);
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s32 errDmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
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s32 errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
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DmaStatusInfo IopChannels[DMA_CHANNEL_MAX]; // I dont' knwo how many there are, 10?
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DmaHandlerInfo IopDmaHandlers[DMA_CHANNEL_MAX] =
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{
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{0}, //0
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{0}, //1
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{0}, //2
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{cdvdDmaRead, errDmaWrite, cdvdDmaInterrupt}, //3: CDVD
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{spu2DmaRead, spu2DmaWrite, spu2DmaInterrupt}, //4: Spu Core0
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{0}, //5
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{0}, //6: OT?
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{spu2DmaRead, spu2DmaWrite, spu2DmaInterrupt}, //7: Spu Core1
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{0},//{dev9DmaRead, dev9DmaWrite, dev9DmaInterrupt}, //8: Dev9
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{0},//{sif0DmaRead, sif0DmaWrite, sif0DmaInterrupt}, //9: SIF0
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{0},//{sif1DmaRead, sif1DmaWrite, sif1DmaInterrupt}, //10: SIF1
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{0}, // Sio2
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{0}, // Sio2
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};
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const char* IopDmaNames[DMA_CHANNEL_MAX] =
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{
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"Ps1 Mdec",
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"Ps1 Mdec",
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"Ps1 Gpu",
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"CDVD",
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"SPU/SPU2 Core0",
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"?",
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"OT",
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"SPU2 Core1", //7: Spu Core1
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"Dev9", //8: Dev9
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"Sif0", //9: SIF0
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"Sif1", //10: SIF1
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"Sio2",//...
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"Sio2",
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"?", "?", "?"
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};
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// Prototypes. To be implemented later (or in other parts of the emulator)
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void SetDmaUpdateTarget(u32 delay)
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{
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psxCounters[8].CycleT = delay;
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}
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void RaiseDmaIrq(u32 channel)
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{
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if(channel<7)
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psxDmaInterrupt(channel);
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else
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psxDmaInterrupt2(channel-7);
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}
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// WARNING: CALLER ****[MUST]**** CALL IopDmaUpdate RIGHT AFTER THIS!
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void IopDmaStart(int channel, u32 chcr, u32 madr, u32 bcr)
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{
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// I dont' really understand this, but it's used above. Is this BYTES OR WHAT?
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int size = 4* (bcr >> 16) * (bcr & 0xFFFF);
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IopChannels[channel].Control = chcr | DMA_CTRL_ACTIVE;
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IopChannels[channel].MemAddr = madr;
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IopChannels[channel].ByteCount = size;
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SetDmaUpdateTarget(0);
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}
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void IopDmaUpdate(u32 elapsed)
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{
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s32 MinDelay = 0x7FFFFFFF;
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for (int i = 0;i < DMA_CHANNEL_MAX;i++)
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{
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DmaStatusInfo *ch = IopChannels + i;
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if (ch->Control&DMA_CTRL_ACTIVE)
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{
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ch->Target -= elapsed;
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if (ch->Target <= 0)
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{
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if (ch->ByteCount <= 0)
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{
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ch->Control &= ~DMA_CTRL_ACTIVE;
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RaiseDmaIrq(i);
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IopDmaHandlers[i].Interrupt(i);
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}
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else
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{
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// TODO: Make sure it's the right order
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DmaHandler handler = (ch->Control & DMA_CTRL_DIRECTION) ? IopDmaHandlers[i].Write : IopDmaHandlers[i].Read;
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u32 BCount = 0;
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s32 Target = (handler) ? handler(i, (u32*)iopPhysMem(ch->MemAddr), ch->ByteCount, &BCount) : 0;
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if(BCount>0)
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{
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psxCpu->Clear(ch->MemAddr, BCount/4);
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}
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int TTarget = 100;
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if (Target < 0)
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{
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// TODO: ... What to do if the plugin errors? :P
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}
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else if (BCount != 0)
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{
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ch->MemAddr += BCount;
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ch->ByteCount -= BCount;
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TTarget = BCount; // / ch->Width;
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}
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if (Target != 0) TTarget = Target;
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if (ch->Target<MinDelay) MinDelay = TTarget;
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ch->Target += TTarget;
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}
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}
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}
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}
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if(MinDelay<0x7FFFFFFF)
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SetDmaUpdateTarget(MinDelay);
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else
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SetDmaUpdateTarget(10000);
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}
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s32 errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
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{
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Console.Error("ERROR: Tried to read using DMA %d (%s). Ignoring.", 0, channel, IopDmaNames[channel]);
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*bytesProcessed = bytesLeft;
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return 0;
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}
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s32 errDmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
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{
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Console.Error("ERROR: Tried to write using DMA %d (%s). Ignoring.", 0, channel, IopDmaNames[channel]);
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*bytesProcessed = bytesLeft;
|
|
return 0;
|
|
}
|
|
|
|
|
|
#endif
|