mirror of https://github.com/PCSX2/pcsx2.git
517 lines
14 KiB
C++
517 lines
14 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include "Common.h"
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#include "System/SysThreads.h"
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#include "Gif.h"
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extern Fixed100 GetVerticalFrequency();
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extern __aligned16 u8 g_RealGSMem[Ps2MemSize::GSregs];
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enum CSR_FifoState
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{
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CSR_FIFO_NORMAL = 0, // Somwhere in between (Neither empty or almost full).
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CSR_FIFO_EMPTY, // Empty
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CSR_FIFO_FULL, // Almost Full
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CSR_FIFO_RESERVED // Reserved / Unused.
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};
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// --------------------------------------------------------------------------------------
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// tGS_CSR
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// --------------------------------------------------------------------------------------
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// This is the Control Register for the GS. It is a dual-instance register that returns
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// distinctly different values for most fields when read and written. In PCSX2 we house
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// the written version in the gsRegs buffer, and generate the readback version on-demand
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// from various other PCSX2 system statuses.
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union tGS_CSR
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{
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struct
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{
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// Write:
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// 0 - No action;
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// 1 - Old event is cleared and event is enabled.
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// Read:
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// 0 - No SIGNAL pending.
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// 1 - SIGNAL has been generated.
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u64 SIGNAL :1;
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// Write:
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// 0 - No action;
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// 1 - FINISH event is enabled.
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// Read:
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// 0 - No FINISH event pending.
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// 1 - FINISH event has been generated.
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u64 FINISH :1;
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// Hsync Interrupt Control
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// Write:
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// 0 - No action;
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// 1 - Hsync interrupt is enabled.
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// Read:
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// 0 - No Hsync interrupt pending.
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// 1 - Hsync interrupt has been generated.
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u64 HSINT :1;
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// Vsync Interrupt Control
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// Write:
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// 0 - No action;
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// 1 - Vsync interrupt is enabled.
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// Read:
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// 0 - No Vsync interrupt pending.
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// 1 - Vsync interrupt has been generated.
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u64 VSINT :1;
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// Rect Area Write Termination Control
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// 0 - No action;
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// 1 - Rect area write interrupt is enabled.
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// Read:
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// 0 - No RAWrite interrupt pending.
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// 1 - RAWrite interrupt has been generated.
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u64 EDWINT :1;
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u64 _zero1 :1;
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u64 _zero2 :1;
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u64 pad1 :1;
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// FLUSH (write-only!)
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// Write:
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// 0 - Resume drawing if suspended (?)
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// 1 - Flush the GS FIFO and suspend drawing
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// Read: Always returns 0. (?)
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u64 FLUSH :1;
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// RESET (write-only!)
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// Write:
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// 0 - Do nothing.
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// 1 - GS soft system reset. Clears FIFOs and resets IMR to all 1's.
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// (PCSX2 implementation also clears GIFpaths, though that behavior may differ on real HW).
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// Read: Always returns 0. (?)
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u64 RESET :1;
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u64 _pad2 :2;
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// (I have no idea what this reg is-- air)
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// Output value is updated by sampling the VSync. (?)
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u64 NFIELD :1;
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// Current Field of Display [page flipping] (read-only?)
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// 0 - EVEN
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// 1 - ODD
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u64 FIELD :1;
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// GS FIFO Status (read-only)
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// 00 - Somewhere in between
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// 01 - Empty
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// 10 - Almost Full
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// 11 - Reserved (unused)
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// Assign values using the CSR_FifoState enum.
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u64 FIFO :2;
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// Revision number of the GS (fairly arbitrary)
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u64 REV :8;
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// ID of the GS (also fairly arbitrary)
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u64 ID :8;
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};
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u64 _u64;
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struct
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{
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u32 _u32; // lower 32 bits (all useful content!)
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u32 _unused32; // upper 32 bits (unused -- should probably be 0)
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};
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void SwapField()
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{
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_u32 ^= 0x2000;
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}
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void Reset()
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{
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_u64 = 0;
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FIFO = CSR_FIFO_EMPTY;
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REV = 0x1B; // GS Revision
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ID = 0x55; // GS ID
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}
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bool HasAnyInterrupts() const { return (SIGNAL || FINISH || HSINT || VSINT || EDWINT); }
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u32 GetInterruptMask() const
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{
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return _u32 & 0x1f;
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}
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void SetAllInterrupts(bool value=true)
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{
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SIGNAL = FINISH = HSINT = VSINT = EDWINT = value;
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}
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tGS_CSR(u64 val) { _u64 = val; }
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tGS_CSR(u32 val) { _u32 = val; }
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tGS_CSR() { Reset(); }
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};
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// --------------------------------------------------------------------------------------
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// tGS_IMR
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// --------------------------------------------------------------------------------------
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union tGS_IMR
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{
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struct
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{
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u32 _reserved1 : 8;
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u32 SIGMSK : 1; // Signal evevnt interrupt mask
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u32 FINISHMSK : 1; // Finish event interrupt mask
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u32 HSMSK : 1; // HSync interrupt mask
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u32 VSMSK : 1; // VSync interrupt mask
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u32 EDWMSK : 1; // Rectangle write termination interrupt mask
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u32 _undefined : 2; // undefined bits should be set to 1.
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u32 _reserved2 : 17;
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};
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u32 _u32;
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void reset()
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{
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_u32 = 0;
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SIGMSK = FINISHMSK = HSMSK = VSMSK = EDWMSK = true;
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_undefined = 0x3;
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}
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void set(u32 value)
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{
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_u32 = (value & 0x1f00); // Set only the interrupt mask fields.
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_undefined = 0x3; // These should always be set.
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}
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bool masked() const { return (SIGMSK || FINISHMSK || HSMSK || VSMSK || EDWMSK); }
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};
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// --------------------------------------------------------------------------------------
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// GSRegSMODE1
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// --------------------------------------------------------------------------------------
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// Previously, the union was used to get the CMOD bit of the SMODE1 register
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// Commenting it out as it's unused right now. (Might potentially be useful in the future)
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//union GSRegSMODE1
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//{
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// struct
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// {
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// u32 RC : 3;
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// u32 LC : 7;
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// u32 T1248 : 2;
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// u32 SLCK : 1;
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// u32 CMOD : 2;
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// u32 EX : 1;
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// u32 PRST : 1;
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// u32 SINT : 1;
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// u32 XPCK : 1;
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// u32 PCK2 : 2;
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// u32 SPML : 4;
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// u32 GCONT : 1;
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// u32 PHS : 1;
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// u32 PVS : 1;
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// u32 PEHS : 1;
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// u32 PEVS : 1;
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// u32 CLKSEL : 2;
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// u32 NVCK : 1;
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// u32 SLCK2 : 1;
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// u32 VCKSEL : 2;
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// u32 VHP : 1;
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// u32 _PAD1 : 27;
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// };
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//
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// u64 SMODE1;
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//};
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// --------------------------------------------------------------------------------------
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// GSRegSIGBLID
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// --------------------------------------------------------------------------------------
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struct GSRegSIGBLID
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{
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u32 SIGID;
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u32 LBLID;
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};
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#define PS2MEM_GS g_RealGSMem
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#define PS2GS_BASE(mem) (PS2MEM_GS+(mem&0x13ff))
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#define CSRreg ((tGS_CSR&)*(PS2MEM_GS+0x1000))
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#define GSCSRr ((u32&)*(PS2MEM_GS+0x1000))
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#define GSIMR ((tGS_IMR&)*(PS2MEM_GS+0x1010))
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#define GSSIGLBLID ((GSRegSIGBLID&)*(PS2MEM_GS+0x1080))
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enum class GS_VideoMode : int
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{
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Uninitialized,
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Unknown,
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NTSC,
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PAL,
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VESA,
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SDTV_480P,
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SDTV_576P,
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HDTV_720P,
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HDTV_1080I,
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HDTV_1080P,
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DVD_NTSC,
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DVD_PAL
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};
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extern GS_VideoMode gsVideoMode;
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extern bool gsIsInterlaced;
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/////////////////////////////////////////////////////////////////////////////
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// MTGS Threaded Class Declaration
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// Uncomment this to enable the MTGS debug stack, which tracks to ensure reads
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// and writes stay synchronized. Warning: the debug stack is VERY slow.
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//#define RINGBUF_DEBUG_STACK
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enum MTGS_RingCommand
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{
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GS_RINGTYPE_P1
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, GS_RINGTYPE_P2
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, GS_RINGTYPE_P3
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, GS_RINGTYPE_VSYNC
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, GS_RINGTYPE_FRAMESKIP
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, GS_RINGTYPE_FREEZE
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, GS_RINGTYPE_RESET // issues a GSreset() command.
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, GS_RINGTYPE_SOFTRESET // issues a soft reset for the GIF
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, GS_RINGTYPE_MODECHANGE // for issued mode changes.
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, GS_RINGTYPE_CRC
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, GS_RINGTYPE_GSPACKET
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, GS_RINGTYPE_MTVU_GSPACKET
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, GS_RINGTYPE_INIT_READ_FIFO1
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, GS_RINGTYPE_INIT_READ_FIFO2
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};
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struct MTGS_FreezeData
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{
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freezeData* fdata;
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s32 retval; // value returned from the call, valid only after an mtgsWaitGS()
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};
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// --------------------------------------------------------------------------------------
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// SysMtgsThread
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// --------------------------------------------------------------------------------------
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class SysMtgsThread : public SysThreadBase
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{
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typedef SysThreadBase _parent;
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public:
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// note: when m_ReadPos == m_WritePos, the fifo is empty
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// Threading info: m_ReadPos is updated by the MTGS thread. m_WritePos is updated by the EE thread
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std::atomic<unsigned int> m_ReadPos; // cur pos gs is reading from
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std::atomic<unsigned int> m_WritePos; // cur pos ee thread is writing to
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std::atomic<bool> m_RingBufferIsBusy;
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std::atomic<bool> m_SignalRingEnable;
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std::atomic<int> m_SignalRingPosition;
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std::atomic<int> m_QueuedFrameCount;
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std::atomic<bool> m_VsyncSignalListener;
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Mutex m_mtx_RingBufferBusy; // Is obtained while processing ring-buffer data
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Mutex m_mtx_RingBufferBusy2; // This one gets released on semaXGkick waiting...
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Mutex m_mtx_WaitGS;
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Semaphore m_sem_OnRingReset;
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Semaphore m_sem_Vsync;
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// used to keep multiple threads from sending packets to the ringbuffer concurrently.
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// (currently not used or implemented -- is a planned feature for a future threaded VU1)
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//MutexLockRecursive m_PacketLocker;
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// Used to delay the sending of events. Performance is better if the ringbuffer
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// has more than one command in it when the thread is kicked.
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int m_CopyDataTally;
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Semaphore m_sem_OpenDone;
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std::atomic<bool> m_PluginOpened;
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// These vars maintain instance data for sending Data Packets.
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// Only one data packet can be constructed and uploaded at a time.
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uint m_packet_startpos; // size of the packet (data only, ie. not including the 16 byte command!)
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uint m_packet_size; // size of the packet (data only, ie. not including the 16 byte command!)
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uint m_packet_writepos; // index of the data location in the ringbuffer.
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#ifdef RINGBUF_DEBUG_STACK
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Threading::Mutex m_lock_Stack;
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#endif
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public:
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SysMtgsThread();
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virtual ~SysMtgsThread();
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// Waits for the GS to empty out the entire ring buffer contents.
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void WaitGS(bool syncRegs=true, bool weakWait=false, bool isMTVU=false);
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void ResetGS();
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void PrepDataPacket( MTGS_RingCommand cmd, u32 size );
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void PrepDataPacket( GIF_PATH pathidx, u32 size );
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void SendDataPacket();
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void SendGameCRC( u32 crc );
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void WaitForOpen();
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void Freeze( int mode, MTGS_FreezeData& data );
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void SendSimpleGSPacket( MTGS_RingCommand type, u32 offset, u32 size, GIF_PATH path );
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void SendSimplePacket( MTGS_RingCommand type, int data0, int data1, int data2 );
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void SendPointerPacket( MTGS_RingCommand type, u32 data0, void* data1 );
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u8* GetDataPacketPtr() const;
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void SetEvent();
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void PostVsyncStart();
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bool IsPluginOpened() const { return m_PluginOpened; }
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protected:
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void OpenPlugin();
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void ClosePlugin();
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void OnStart();
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void OnResumeReady();
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void OnSuspendInThread();
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void OnPauseInThread() {}
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void OnResumeInThread( bool IsSuspended );
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void OnCleanupInThread();
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void GenericStall( uint size );
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// Used internally by SendSimplePacket type functions
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void _FinishSimplePacket();
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void ExecuteTaskInThread();
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};
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// GetMTGS() is a required external implementation. This function is *NOT* provided
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// by the PCSX2 core library. It provides an interface for the linking User Interface
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// apps or DLLs to reference their own instance of SysMtgsThread (also allowing them
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// to extend the class and override virtual methods).
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//
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extern SysMtgsThread& GetMTGS();
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/////////////////////////////////////////////////////////////////////////////
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// Generalized GS Functions and Stuff
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extern s32 gsOpen();
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extern void gsClose();
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extern void gsReset();
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extern void gsOnModeChanged( Fixed100 framerate, u32 newTickrate );
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extern void gsSetVideoMode( GS_VideoMode mode );
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extern void gsResetFrameSkip();
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extern void gsPostVsyncStart();
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extern void gsFrameSkip();
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extern void gsUpdateFrequency( Pcsx2Config& config );
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// Some functions shared by both the GS and MTGS
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extern void _gs_ResetFrameskip();
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extern void gsWrite8(u32 mem, u8 value);
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extern void gsWrite16(u32 mem, u16 value);
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extern void gsWrite32(u32 mem, u32 value);
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extern void __fastcall gsWrite64_page_00( u32 mem, const mem64_t* value );
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extern void __fastcall gsWrite64_page_01( u32 mem, const mem64_t* value );
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extern void __fastcall gsWrite64_generic( u32 mem, const mem64_t* value );
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extern void __fastcall gsWrite128_page_00( u32 mem, const mem128_t* value );
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extern void __fastcall gsWrite128_page_01( u32 mem, const mem128_t* value );
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extern void __fastcall gsWrite128_generic( u32 mem, const mem128_t* value );
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extern u8 gsRead8(u32 mem);
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extern u16 gsRead16(u32 mem);
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extern u32 gsRead32(u32 mem);
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extern u64 gsRead64(u32 mem);
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void gsIrq();
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extern tGS_CSR CSRr;
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// GS Playback
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enum gsrun
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{
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GSRUN_TRANS1 = 1,
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GSRUN_TRANS2,
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GSRUN_TRANS3,
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GSRUN_VSYNC
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};
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#ifdef PCSX2_DEVBUILD
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extern int g_SaveGSStream;
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extern int g_nLeftGSFrames;
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#endif
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// Size of the ringbuffer as a power of 2 -- size is a multiple of simd128s.
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// (actual size is 1<<m_RingBufferSizeFactor simd vectors [128-bit values])
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// A value of 19 is a 8meg ring buffer. 18 would be 4 megs, and 20 would be 16 megs.
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// Default was 2mb, but some games with lots of MTGS activity want 8mb to run fast (rama)
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static const uint RingBufferSizeFactor = 19;
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// size of the ringbuffer in simd128's.
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static const uint RingBufferSize = 1<<RingBufferSizeFactor;
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// Mask to apply to ring buffer indices to wrap the pointer from end to
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// start (the wrapping is what makes it a ringbuffer, yo!)
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static const uint RingBufferMask = RingBufferSize - 1;
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struct MTGS_BufferedData
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{
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u128 m_Ring[RingBufferSize];
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u8 Regs[Ps2MemSize::GSregs];
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MTGS_BufferedData() {}
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u128& operator[]( uint idx )
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{
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pxAssert( idx < RingBufferSize );
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return m_Ring[idx];
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}
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};
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extern __aligned(32) MTGS_BufferedData RingBuffer;
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// FIXME: These belong in common with other memcpy tools. Will move them there later if no one
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// else beats me to it. --air
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inline void MemCopy_WrappedDest( const u128* src, u128* destBase, uint& destStart, uint destSize, uint len ) {
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uint endpos = destStart + len;
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if ( endpos < destSize ) {
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memcpy(&destBase[destStart], src, len*16);
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destStart += len;
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}
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else {
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uint firstcopylen = destSize - destStart;
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memcpy(&destBase[destStart], src, firstcopylen*16);
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destStart = endpos % destSize;
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memcpy(destBase, src+firstcopylen, destStart*16);
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}
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}
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inline void MemCopy_WrappedSrc( const u128* srcBase, uint& srcStart, uint srcSize, u128* dest, uint len ) {
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uint endpos = srcStart + len;
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if ( endpos < srcSize ) {
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memcpy(dest, &srcBase[srcStart], len*16);
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srcStart += len;
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}
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else {
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uint firstcopylen = srcSize - srcStart;
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memcpy(dest, &srcBase[srcStart], firstcopylen*16);
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srcStart = endpos % srcSize;
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memcpy(dest+firstcopylen, srcBase, srcStart*16);
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}
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}
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