mirror of https://github.com/PCSX2/pcsx2.git
232 lines
6.1 KiB
C
232 lines
6.1 KiB
C
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2009 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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enum vif0_stat_flags
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{
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VIF0_STAT_VPS_W = (1),
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VIF0_STAT_VPS_D = (2),
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VIF0_STAT_VPS_T = (3),
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VIF0_STAT_VPS = (3),
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VIF0_STAT_VEW = (1<<2),
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VIF0_STAT_MRK = (1<<6),
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VIF0_STAT_DBF = (1<<7),
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VIF0_STAT_VSS = (1<<8),
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VIF0_STAT_VFS = (1<<9),
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VIF0_STAT_VIS = (1<<10),
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VIF0_STAT_INT = (1<<11),
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VIF0_STAT_ER0 = (1<<12),
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VIF0_STAT_ER1 = (1<<13),
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VIF0_STAT_FQC = (15<<24)
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};
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enum vif1_stat_flags
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{
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VIF1_STAT_VPS_W = (1),
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VIF1_STAT_VPS_D = (2),
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VIF1_STAT_VPS_T = (3),
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VIF1_STAT_VPS = (3),
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VIF1_STAT_VEW = (1<<2),
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VIF1_STAT_VGW = (1<<3),
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VIF1_STAT_MRK = (1<<6),
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VIF1_STAT_DBF = (1<<7),
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VIF1_STAT_VSS = (1<<8),
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VIF1_STAT_VFS = (1<<9),
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VIF1_STAT_VIS = (1<<10),
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VIF1_STAT_INT = (1<<11),
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VIF1_STAT_ER0 = (1<<12),
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VIF1_STAT_ER1 = (1<<13),
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VIF1_STAT_FDR = (1<<23),
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VIF1_STAT_FQC = (31<<24)
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};
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// These are the stat flags that are the same for vif0 & vif1,
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// for occassions where we don't neccessarily know which we are using.
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enum vif_stat_flags
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{
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VIF_STAT_VPS_W = (1),
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VIF_STAT_VPS_D = (2),
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VIF_STAT_VPS_T = (3),
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VIF_STAT_VPS = (3),
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VIF_STAT_VEW = (1<<2),
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VIF_STAT_MRK = (1<<6),
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VIF_STAT_DBF = (1<<7),
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VIF_STAT_VSS = (1<<8),
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VIF_STAT_VFS = (1<<9),
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VIF_STAT_VIS = (1<<10),
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VIF_STAT_INT = (1<<11),
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VIF_STAT_ER0 = (1<<12),
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VIF_STAT_ER1 = (1<<13)
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};
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enum vif_status
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{
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VPS_IDLE = 0,
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VPS_WAITING = 1,
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VPS_DECODING = 2,
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VPS_TRANSFERRING = 3 // And decompressing.
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};
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//
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// Bitfield Structure
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//
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union tVIF_STAT {
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struct {
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u32 VPS : 2; // Vif(0/1) status; 00 - idle, 01 - waiting for data following vifcode, 10 - decoding vifcode, 11 - decompressing/trasferring data follwing vifcode.
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u32 VEW : 1; // E-bit wait (1 - wait, 0 - don't wait)
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u32 VGW : 1; // Status waiting for the end of gif transfer (Vif1 only)
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u32 reserved : 2;
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u32 MRK : 1; // Mark Detect
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u32 DBF : 1; // Double Buffer Flag
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u32 VSS : 1; // Stopped by STOP
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u32 VFS : 1; // Stopped by ForceBreak
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u32 VIS : 1; // Vif Interrupt Stall
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u32 INT : 1; // Intereupt by the i bit.
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u32 ER0 : 1; // DmaTag Mismatch error.
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u32 ER1 : 1; // VifCode error
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u32 reserved2 : 9;
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u32 FDR : 1; // VIF/FIFO transfer direction. (false - memory -> Vif, true - Vif -> memory)
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u32 FQC : 5; // Amount of data. Up to 8 qwords on Vif0, 16 on Vif1.
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};
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u32 _u32;
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tVIF_STAT(u32 val) { _u32 = val; }
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bool test(u32 flags) const { return !!(_u32 & flags); }
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void set_flags (u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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wxString desc() const { return wxsFormat(L"Stat: 0x%x", _u32); }
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};
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#define VIF_STAT(value) ((tVIF_STAT)(value))
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union tVIF_FBRST {
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struct {
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u32 RST : 1; // Resets Vif(0/1) when written.
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u32 FBK : 1; // Causes a Forcebreak to Vif((0/1) when true. (Stall)
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u32 STP : 1; // Stops after the end of the Vifcode in progress when true. (Stall)
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u32 STC : 1; // Cancels the Vif(0/1) stall and clears Vif Stats VSS, VFS, VIS, INT, ER0 & ER1.
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u32 reserved : 28;
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};
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u32 _u32;
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tVIF_FBRST(u32 val) { _u32 = val; }
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bool test (u32 flags) const { return !!(_u32 & flags); }
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void set_flags (u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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wxString desc() const { return wxsFormat(L"Fbrst: 0x%x", _u32); }
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};
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#define FBRST(value) ((tVIF_FBRST)(value))
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union tVIF_ERR {
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struct {
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u32 MII : 1; // Masks Stat INT.
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u32 ME0 : 1; // Masks Stat Err0.
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u32 ME1 : 1; // Masks Stat Err1.
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u32 reserved : 29;
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};
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u32 _u32;
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tVIF_ERR (u32 val) { _u32 = val; }
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void write(u32 val) { _u32 = val; }
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bool test (u32 flags) const { return !!(_u32 & flags); }
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void set_flags (u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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wxString desc() const { return wxsFormat(L"Err: 0x%x", _u32); }
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};
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struct vifCycle
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{
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u8 cl, wl;
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u8 pad[2];
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};
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struct VIFregisters {
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tVIF_STAT stat;
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u32 pad0[3];
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u32 fbrst;
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u32 pad1[3];
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tVIF_ERR err;
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u32 pad2[3];
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u32 mark;
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u32 pad3[3];
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vifCycle cycle; //data write cycle
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u32 pad4[3];
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u32 mode;
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u32 pad5[3];
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u32 num;
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u32 pad6[3];
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u32 mask;
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u32 pad7[3];
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u32 code;
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u32 pad8[3];
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u32 itops;
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u32 pad9[3];
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u32 base; // Not used in VIF0
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u32 pad10[3];
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u32 ofst; // Not used in VIF0
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u32 pad11[3];
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u32 tops; // Not used in VIF0
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u32 pad12[3];
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u32 itop;
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u32 pad13[3];
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u32 top; // Not used in VIF0
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u32 pad14[3];
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u32 mskpath3;
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u32 pad15[3];
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u32 r0; // row0 register
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u32 pad16[3];
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u32 r1; // row1 register
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u32 pad17[3];
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u32 r2; // row2 register
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u32 pad18[3];
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u32 r3; // row3 register
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u32 pad19[3];
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u32 c0; // col0 register
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u32 pad20[3];
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u32 c1; // col1 register
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u32 pad21[3];
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u32 c2; // col2 register
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u32 pad22[3];
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u32 c3; // col3 register
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u32 pad23[3];
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u32 offset; // internal UNPACK offset
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u32 addr;
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};
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extern VIFregisters *vifRegs;
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#define vif0RegsRef ((VIFregisters&)PS2MEM_HW[0x3800])
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#define vif1RegsRef ((VIFregisters&)PS2MEM_HW[0x3c00])
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#define vif0Regs (&vif0RegsRef)
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#define vif1Regs (&vif1RegsRef)
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#define _vifT template <int idx>
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#define vifX (idx ? vif1 : vif0)
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#define vifXRegs (idx ? (vif1Regs) : (vif0Regs))
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#define _f __forceinline
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extern void dmaVIF0();
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extern void dmaVIF1();
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extern void mfifoVIF1transfer(int qwc);
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extern bool VIF0transfer(u32 *data, int size, bool istag);
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extern bool VIF1transfer(u32 *data, int size, bool istag);
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extern void vifMFIFOInterrupt();
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