mirror of https://github.com/PCSX2/pcsx2.git
187 lines
3.3 KiB
C
187 lines
3.3 KiB
C
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2009 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include "Vif.h"
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enum VURegFlags
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{
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REG_STATUS_FLAG = 16,
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REG_MAC_FLAG = 17,
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REG_CLIP_FLAG = 18,
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REG_ACC_FLAG = 19, // dummy flag that indicates that VFACC is written/read (nothing to do with VI[19])
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REG_R = 20,
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REG_I = 21,
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REG_Q = 22,
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REG_P = 23, // only exists in micromode
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REG_VF0_FLAG = 24, // dummy flag that indicates VF0 is read (nothing to do with VI[24])
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REG_TPC = 26,
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REG_CMSAR0 = 27,
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REG_FBRST = 28,
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REG_VPU_STAT = 29,
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REG_CMSAR1 = 31
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};
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//interpreter hacks, WIP
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//#define INT_VUSTALLHACK //some games work without those, big speedup
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//#define INT_VUDOUBLEHACK
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enum VUStatus {
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VU_Ready = 0,
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VU_Run = 1,
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VU_Stop = 2,
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};
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union VECTOR {
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struct {
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float x,y,z,w;
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} f;
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struct {
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u32 x,y,z,w;
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} i;
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float F[4];
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u64 UD[2]; //128 bits
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s64 SD[2];
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u32 UL[4];
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s32 SL[4];
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u16 US[8];
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s16 SS[8];
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u8 UC[16];
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s8 SC[16];
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};
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struct REG_VI {
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union {
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float F;
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s32 SL;
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u32 UL;
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s16 SS[2];
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u16 US[2];
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s8 SC[4];
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u8 UC[4];
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};
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u32 padding[3]; // needs padding to make them 128bit; VU0 maps VU1's VI regs as 128bits to addr 0x4xx0 in
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// VU0 mem, with only lower 16 bits valid, and the upper 112bits are hardwired to 0 (cottonvibes)
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};
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//#define VUFLAG_BREAKONMFLAG 0x00000001
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#define VUFLAG_MFLAGSET 0x00000002
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struct fdivPipe {
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int enable;
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REG_VI reg;
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u32 sCycle;
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u32 Cycle;
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u32 statusflag;
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};
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struct efuPipe {
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int enable;
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REG_VI reg;
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u32 sCycle;
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u32 Cycle;
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};
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struct fmacPipe {
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int enable;
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int reg;
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int xyzw;
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u32 sCycle;
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u32 Cycle;
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u32 macflag;
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u32 statusflag;
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u32 clipflag;
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};
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struct ialuPipe {
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int enable;
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int reg;
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u32 sCycle;
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u32 Cycle;
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};
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struct VURegs {
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VECTOR VF[32]; // VF and VI need to be first in this struct for proper mapping
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REG_VI VI[32]; // needs to be 128bit x 32 (cottonvibes)
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VECTOR ACC;
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REG_VI q;
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REG_VI p;
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u32 macflag;
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u32 statusflag;
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u32 clipflag;
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u32 cycle;
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u32 flags;
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void (*vuExec)(VURegs*);
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VIFregisters *vifRegs;
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u8 *Mem;
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u8 *Micro;
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u32 code;
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u32 maxmem;
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u32 maxmicro;
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u16 branch;
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u16 ebit;
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u32 branchpc;
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fmacPipe fmac[8];
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fdivPipe fdiv;
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efuPipe efu;
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ialuPipe ialu[8];
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VURegs() :
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Mem( NULL )
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, Micro( NULL )
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{
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}
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};
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enum VUPipeState
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{
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VUPIPE_NONE = 0,
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VUPIPE_FMAC,
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VUPIPE_FDIV,
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VUPIPE_EFU,
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VUPIPE_IALU,
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VUPIPE_BRANCH,
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VUPIPE_XGKICK
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};
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struct _VURegsNum {
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u8 pipe; // if 0xff, COP2
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u8 VFwrite;
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u8 VFwxyzw;
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u8 VFr0xyzw;
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u8 VFr1xyzw;
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u8 VFread0;
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u8 VFread1;
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u32 VIwrite;
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u32 VIread;
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int cycles;
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};
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extern VURegs* g_pVU1;
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extern __aligned16 VURegs VU0;
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#define VU1 (*g_pVU1)
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extern u32* GET_VU_MEM(VURegs* VU, u32 addr);
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