mirror of https://github.com/PCSX2/pcsx2.git
399 lines
10 KiB
C++
399 lines
10 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#define _PC_ // disables MIPS opcode macros.
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#include "IopCommon.h"
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#include "Sif.h"
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_sif sif2;
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static bool done = false;
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static __fi void Sif2Init()
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{
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SIF_LOG("SIF2 DMA start... free %x iop busy %x", sif2.fifo.sif_free(), sif2.iop.busy);
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done = false;
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sif2.ee.cycles = 0;
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sif2.iop.cycles = 0;
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}
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__fi bool WriteFifoSingleWord()
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{
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// There's some data ready to transfer into the fifo..
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SIF_LOG("Write Single word to SIF2 Fifo");
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sif2.fifo.write((u32*)&psxHu32(HW_PS1_GPU_DATA), 1);
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if (sif2.fifo.size > 0) psxHu32(0x1000f300) &= ~0x4000000;
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return true;
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}
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__fi bool ReadFifoSingleWord()
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{
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u32 ptag[4];
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//SIF_LOG(" EE SIF doing transfer %04Xqw to %08X", readSize, sif2dma.madr);
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SIF_LOG("Read Fifo SIF2 Single Word IOP Busy %x Fifo Size %x SIF2 CHCR %x", sif2.iop.busy, sif2.fifo.size, HW_DMA2_CHCR);
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sif2.fifo.read((u32*)&ptag[0], 1);
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psHu32(0x1000f3e0) = ptag[0];
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if (sif2.fifo.size == 0) psxHu32(0x1000f300) |= 0x4000000;
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if (sif2.iop.busy && sif2.fifo.size <= 8)SIF2Dma();
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return true;
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}
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// Write from Fifo to EE.
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static __fi bool WriteFifoToEE()
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{
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const int readSize = std::min((s32)sif2dma.qwc, sif2.fifo.size >> 2);
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tDMA_TAG *ptag;
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//SIF_LOG(" EE SIF doing transfer %04Xqw to %08X", readSize, sif2dma.madr);
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SIF_LOG("Write Fifo to EE: ----------- %lX of %lX", readSize << 2, sif2dma.qwc << 2);
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ptag = sif2dma.getAddr(sif2dma.madr, DMAC_SIF2, true);
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if (ptag == NULL)
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{
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DevCon.Warning("Write Fifo to EE: ptag == NULL");
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return false;
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}
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sif2.fifo.read((u32*)ptag, readSize << 2);
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// Clearing handled by vtlb memory protection and manual blocks.
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//Cpu->Clear(sif2dma.madr, readSize*4);
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sif2dma.madr += readSize << 4;
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sif2.ee.cycles += readSize; // fixme : BIAS is factored in above
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sif2dma.qwc -= readSize;
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return true;
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}
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// Write IOP to Fifo.
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static __fi bool WriteIOPtoFifo()
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{
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// There's some data ready to transfer into the fifo..
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const int writeSize = std::min(sif2.iop.counter, sif2.fifo.sif_free());
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SIF_LOG("Write IOP to Fifo: +++++++++++ %lX of %lX", writeSize, sif2.iop.counter);
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sif2.fifo.write((u32*)iopPhysMem(hw_dma2.madr), writeSize);
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hw_dma2.madr += writeSize << 2;
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// iop is 1/8th the clock rate of the EE and psxcycles is in words (not quadwords).
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sif2.iop.cycles += (writeSize >> 2)/* * BIAS*/; // fixme : should be >> 4
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sif2.iop.counter -= writeSize;
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//PSX_INT(IopEvt_SIF2, sif2.iop.cycles);
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if (sif2.iop.counter == 0) hw_dma2.madr = sif2data & 0xffffff;
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if (sif2.fifo.size > 0) psxHu32(0x1000f300) &= ~0x4000000;
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return true;
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}
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// Read Fifo into an ee tag, transfer it to sif2dma, and process it.
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static __fi bool ProcessEETag()
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{
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alignas(16) static u32 tag[4];
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tDMA_TAG& ptag(*(tDMA_TAG*)tag);
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sif2.fifo.read((u32*)&tag[0], 4); // Tag
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SIF_LOG("SIF2 EE read tag: %x %x %x %x", tag[0], tag[1], tag[2], tag[3]);
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sif2dma.unsafeTransfer(&ptag);
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sif2dma.madr = tag[1];
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SIF_LOG("SIF2 EE dest chain tag madr:%08X qwc:%04X id:%X irq:%d(%08X_%08X)",
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sif2dma.madr, sif2dma.qwc, ptag.ID, ptag.IRQ, tag[1], tag[0]);
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if (sif2dma.chcr.TIE && ptag.IRQ)
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{
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//Console.WriteLn("SIF2 TIE");
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sif2.ee.end = true;
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}
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switch (ptag.ID)
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{
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case TAG_CNT: break;
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case TAG_CNTS:
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break;
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case TAG_END:
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sif2.ee.end = true;
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break;
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}
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return true;
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}
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// Read Fifo into an iop tag, and transfer it to hw_dma9. And presumably process it.
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static __fi bool ProcessIOPTag()
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{
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//sif2.iop.data = *(sifData *)iopPhysMem(hw_dma2.madr); //comment this out and replace words below
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// Process DMA tag at hw_dma9.tadr
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if (HW_DMA2_CHCR & 0x400) DevCon.Warning("First bit %x", sif2.iop.data.data);
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sif2.iop.data.words = sif2.iop.data.data >> 24; // Round up to nearest 4.
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// send the EE's side of the DMAtag. The tag is only 64 bits, with the upper 64 bits
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// ignored by the EE.
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// We're only copying the first 24 bits. Bits 30 and 31 (checked below) are Stop/IRQ bits.
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//psxHu32(HW_PS1_GPU_DATA) += 4;
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sif2.iop.counter = (HW_DMA2_BCR_H16 * HW_DMA2_BCR_L16); //makes it do more stuff?? //sif2words;
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/*if (HW_DMA2_CHCR & 0x400)
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{
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if (sif2.iop.counter == 0) hw_dma2.madr = sif2data & 0xFFFFFF;
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else hw_dma2.madr += 2;
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}
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else hw_dma2.madr += 2;
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// IOP tags have an IRQ bit and an End of Transfer bit:
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if ((sif2data & 0xFFFFFF) == 0xFFFFFF || (HW_DMA2_CHCR & 0x200)) */sif2.iop.end = true;
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DevCon.Warning("SIF2 IOP Tag: madr=%lx, counter=%lx (%08X_%08X)", hw_dma2.madr, sif2.iop.counter, sif2words, sif2data);
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return true;
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}
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// Stop transferring ee, and signal an interrupt.
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static __fi void EndEE()
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{
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SIF_LOG("Sif2: End EE");
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sif2.ee.end = false;
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sif2.ee.busy = false;
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if (sif2.ee.cycles == 0)
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{
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SIF_LOG("SIF2 EE: cycles = 0");
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sif2.ee.cycles = 1;
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}
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CPU_INT(DMAC_SIF2, sif2.ee.cycles*BIAS);
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}
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// Stop transferring iop, and signal an interrupt.
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static __fi void EndIOP()
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{
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SIF_LOG("Sif2: End IOP");
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sif2data = 0;
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//sif2.iop.end = false;
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sif2.iop.busy = false;
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if (sif2.iop.cycles == 0)
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{
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DevCon.Warning("SIF2 IOP: cycles = 0");
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sif2.iop.cycles = 1;
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}
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// iop is 1/8th the clock rate of the EE and psxcycles is in words (not quadwords)
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// So when we're all done, the equation looks like thus:
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//PSX_INT(IopEvt_SIF2, ( ( sif2.iop.cycles*BIAS ) / 4 ) / 8);
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PSX_INT(IopEvt_SIF2, sif2.iop.cycles);
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}
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// Handle the EE transfer.
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static __fi void HandleEETransfer()
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{
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if (!sif2dma.chcr.STR)
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{
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//DevCon.Warning("Replacement for irq prevention hack EE SIF2");
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sif2.ee.end = false;
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sif2.ee.busy = false;
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return;
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}
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/*if (sif2dma.qwc == 0)
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if (sif2dma.chcr.MOD == NORMAL_MODE)
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if (!sif2.ee.end){
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DevCon.Warning("sif2 irq prevented");
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done = true;
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return;
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}*/
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if (sif2dma.qwc <= 0)
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{
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if ((sif2dma.chcr.MOD == NORMAL_MODE) || sif2.ee.end)
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{
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// Stop transferring ee, and signal an interrupt.
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done = true;
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EndEE();
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}
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else if (sif2.fifo.size >= 4) // Read a tag
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{
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// Read Fifo into an ee tag, transfer it to sif2dma
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// and process it.
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DevCon.Warning("SIF2 EE Chain?!");
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ProcessEETag();
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}
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}
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if (sif2dma.qwc > 0) // If we're writing something, continue to do so.
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{
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// Write from Fifo to EE.
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if (sif2.fifo.size > 0)
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{
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WriteFifoToEE();
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}
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}
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}
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// Handle the IOP transfer.
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// Note: Test any changes in this function against Grandia III.
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// What currently happens is this:
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// SIF2 DMA start...
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// SIF + 4 = 4 (pos=4)
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// SIF2 IOP Tag: madr=19870, tadr=179cc, counter=8 (00000008_80019870)
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// SIF - 4 = 0 (pos=4)
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// SIF2 EE read tag: 90000002 935c0 0 0
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// SIF2 EE dest chain tag madr:000935C0 qwc:0002 id:1 irq:1(000935C0_90000002)
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// Write Fifo to EE: ----------- 0 of 8
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// SIF - 0 = 0 (pos=4)
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// Write IOP to Fifo: +++++++++++ 8 of 8
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// SIF + 8 = 8 (pos=12)
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// Write Fifo to EE: ----------- 8 of 8
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// SIF - 8 = 0 (pos=12)
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// Sif0: End IOP
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// Sif0: End EE
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// SIF2 DMA end...
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// What happens if (sif2.iop.counter > 0) is handled first is this
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// SIF2 DMA start...
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// ...
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// SIF + 8 = 8 (pos=12)
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// Sif0: End IOP
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// Write Fifo to EE: ----------- 8 of 8
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// SIF - 8 = 0 (pos=12)
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// SIF2 DMA end...
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static __fi void HandleIOPTransfer()
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{
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if (sif2.iop.counter <= 0) // If there's no more to transfer
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{
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if (sif2.iop.end)
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{
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// Stop transferring iop, and signal an interrupt.
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done = true;
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EndIOP();
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}
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else
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{
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// Read Fifo into an iop tag, and transfer it to hw_dma9.
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// And presumably process it.
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ProcessIOPTag();
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}
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}
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else
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{
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// Write IOP to Fifo.
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if (sif2.fifo.sif_free() > 0)
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{
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WriteIOPtoFifo();
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}
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else DevCon.Warning("Nothing free!");
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}
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}
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static __fi void Sif2End()
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{
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psHu32(SBUS_F240) &= ~0x80;
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psHu32(SBUS_F240) &= ~0x8000;
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DMA_LOG("SIF2 DMA End");
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}
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// Transfer IOP to EE, putting data in the fifo as an intermediate step.
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__fi void SIF2Dma()
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{
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int BusyCheck = 0;
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Sif2Init();
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do
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{
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//I realise this is very hacky in a way but its an easy way of checking if both are doing something
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BusyCheck = 0;
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if (sif2.iop.busy)
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{
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if (sif2.fifo.sif_free() > 0 || (sif2.iop.end && sif2.iop.counter == 0))
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{
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BusyCheck++;
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HandleIOPTransfer();
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}
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}
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if (sif2.ee.busy)
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{
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if (sif2.fifo.size >= 4 || (sif2.ee.end && sif2dma.qwc == 0))
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{
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BusyCheck++;
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HandleEETransfer();
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}
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}
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} while (/*!done && */BusyCheck > 0); // Substituting (sif2.ee.busy || sif2.iop.busy) breaks things.
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Sif2End();
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}
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__fi void sif2Interrupt()
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{
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if (!sif2.iop.end || sif2.iop.counter > 0)
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{
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SIF2Dma();
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return;
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}
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SIF_LOG("SIF2 IOP Intr end");
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HW_DMA2_CHCR &= ~0x01000000;
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psxDmaInterrupt2(2);
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}
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__fi void EEsif2Interrupt()
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{
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hwDmacIrq(DMAC_SIF2);
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sif2dma.chcr.STR = false;
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}
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__fi void dmaSIF2()
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{
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DevCon.Warning("SIF2 EE CHCR %x", sif2dma.chcr._u32);
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SIF_LOG(wxString(L"dmaSIF2" + sif2dma.cmqt_to_str()).To8BitData());
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if (sif2.fifo.readPos != sif2.fifo.writePos)
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{
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SIF_LOG("warning, sif2.fifoReadPos != sif2.fifoWritePos");
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}
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//if(sif2dma.chcr.MOD == CHAIN_MODE && sif2dma.qwc > 0) DevCon.Warning(L"SIF2 QWC on Chain CHCR " + sif2dma.chcr.desc());
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psHu32(SBUS_F240) |= 0x8000;
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sif2.ee.busy = true;
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// Okay, this here is needed currently (r3644).
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// FFX battles in the thunder plains map die otherwise, Phantasy Star 4 as well
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// These 2 games could be made playable again by increasing the time the EE or the IOP run,
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// showing that this is very timing sensible.
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// Doing this DMA unfortunately brings back an old warning in Legend of Legaia though, but it still works.
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//Updated 23/08/2011: The hangs are caused by the EE suspending SIF1 DMA and restarting it when in the middle
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//of processing a "REFE" tag, so the hangs can be solved by forcing the ee.end to be false
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// (as it should always be at the beginning of a DMA). using "if iop is busy" flags breaks Tom Clancy Rainbow Six.
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// Legend of Legaia doesn't throw a warning either :)
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//sif2.ee.end = false;
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SIF2Dma();
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}
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