mirror of https://github.com/PCSX2/pcsx2.git
992 lines
31 KiB
C++
992 lines
31 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include <time.h>
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#include <cmath>
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#include "Common.h"
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#include "R3000A.h"
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#include "Counters.h"
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#include "IopCounters.h"
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#include "GS.h"
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#include "VUmicro.h"
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#include "ps2/HwInternal.h"
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#include "Sio.h"
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using namespace Threading;
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extern u8 psxhblankgate;
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static const uint EECNT_FUTURE_TARGET = 0x10000000;
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static int gates = 0;
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uint g_FrameCount = 0;
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// Counter 4 takes care of scanlines - hSync/hBlanks
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// Counter 5 takes care of vSync/vBlanks
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Counter counters[4];
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SyncCounter hsyncCounter;
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SyncCounter vsyncCounter;
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u32 nextsCounter; // records the cpuRegs.cycle value of the last call to rcntUpdate()
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s32 nextCounter; // delta from nextsCounter, in cycles, until the next rcntUpdate()
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// Forward declarations needed because C/C++ both are wimpy single-pass compilers.
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static void rcntStartGate(bool mode, u32 sCycle);
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static void rcntEndGate(bool mode, u32 sCycle);
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static void rcntWcount(int index, u32 value);
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static void rcntWmode(int index, u32 value);
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static void rcntWtarget(int index, u32 value);
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static void rcntWhold(int index, u32 value);
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static bool IsAnalogVideoMode()
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{
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return (gsVideoMode == GS_VideoMode::PAL || gsVideoMode == GS_VideoMode::NTSC);
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}
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void rcntReset(int index) {
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counters[index].count = 0;
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counters[index].sCycleT = cpuRegs.cycle;
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}
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// Updates the state of the nextCounter value (if needed) to serve
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// any pending events for the given counter.
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// Call this method after any modifications to the state of a counter.
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static __fi void _rcntSet( int cntidx )
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{
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s32 c;
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pxAssume( cntidx <= 4 ); // rcntSet isn't valid for h/vsync counters.
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const Counter& counter = counters[cntidx];
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// Stopped or special hsync gate?
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if (!counter.mode.IsCounting || (counter.mode.ClockSource == 0x3) ) return;
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// check for special cases where the overflow or target has just passed
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// (we probably missed it because we're doing/checking other things)
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if( counter.count > 0x10000 || counter.count > counter.target )
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{
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nextCounter = 4;
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return;
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}
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// nextCounter is relative to the cpuRegs.cycle when rcntUpdate() was last called.
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// However, the current _rcntSet could be called at any cycle count, so we need to take
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// that into account. Adding the difference from that cycle count to the current one
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// will do the trick!
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c = ((0x10000 - counter.count) * counter.rate) - (cpuRegs.cycle - counter.sCycleT);
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c += cpuRegs.cycle - nextsCounter; // adjust for time passed since last rcntUpdate();
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if (c < nextCounter)
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{
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nextCounter = c;
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cpuSetNextEvent( nextsCounter, nextCounter ); //Need to update on counter resets/target changes
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}
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// Ignore target diff if target is currently disabled.
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// (the overflow is all we care about since it goes first, and then the
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// target will be turned on afterward, and handled in the next event test).
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if( counter.target & EECNT_FUTURE_TARGET )
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{
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return;
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}
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else
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{
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c = ((counter.target - counter.count) * counter.rate) - (cpuRegs.cycle - counter.sCycleT);
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c += cpuRegs.cycle - nextsCounter; // adjust for time passed since last rcntUpdate();
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if (c < nextCounter)
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{
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nextCounter = c;
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cpuSetNextEvent( nextsCounter, nextCounter ); //Need to update on counter resets/target changes
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}
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}
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}
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static __fi void cpuRcntSet()
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{
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int i;
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nextsCounter = cpuRegs.cycle;
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nextCounter = vsyncCounter.CycleT - (cpuRegs.cycle - vsyncCounter.sCycle);
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for (i = 0; i < 4; i++)
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_rcntSet( i );
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// sanity check!
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if( nextCounter < 0 ) nextCounter = 0;
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}
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void rcntInit()
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{
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int i;
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g_FrameCount = 0;
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memzero(counters);
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for (i=0; i<4; i++) {
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counters[i].rate = 2;
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counters[i].target = 0xffff;
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}
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counters[0].interrupt = 9;
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counters[1].interrupt = 10;
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counters[2].interrupt = 11;
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counters[3].interrupt = 12;
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hsyncCounter.Mode = MODE_HRENDER;
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hsyncCounter.sCycle = cpuRegs.cycle;
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vsyncCounter.Mode = MODE_VRENDER;
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vsyncCounter.sCycle = cpuRegs.cycle;
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for (i=0; i<4; i++) rcntReset(i);
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cpuRcntSet();
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}
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#ifndef _WIN32
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#include <sys/time.h>
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#endif
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static s64 m_iTicks=0;
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static u64 m_iStart=0;
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struct vSyncTimingInfo
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{
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Fixed100 Framerate; // frames per second (8 bit fixed)
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GS_VideoMode VideoMode; // used to detect change (interlaced/progressive)
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u32 Render; // time from vblank end to vblank start (cycles)
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u32 Blank; // time from vblank start to vblank end (cycles)
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u32 hSyncError; // rounding error after the duration of a rendered frame (cycles)
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u32 hRender; // time from hblank end to hblank start (cycles)
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u32 hBlank; // time from hblank start to hblank end (cycles)
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u32 hScanlinesPerFrame; // number of scanlines per frame (525/625 for NTSC/PAL)
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};
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static vSyncTimingInfo vSyncInfo;
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static void vSyncInfoCalc(vSyncTimingInfo* info, Fixed100 framesPerSecond, u32 scansPerFrame)
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{
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// I use fixed point math here to have strict control over rounding errors. --air
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// NOTE: mgs3 likes a /4 vsync, but many games prefer /2. This seems to indicate a
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// problem in the counters vsync gates somewhere.
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u64 Frame = ((u64)PS2CLK * 1000000ULL) / (framesPerSecond * 100).ToIntRounded();
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u64 HalfFrame = Frame / 2;
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// One test we have shows that VBlank lasts for ~22 HBlanks, another we have show that is the time it's off.
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// There exists a game (Legendz Gekitou! Saga Battle) Which runs REALLY slowly if VBlank is ~22 HBlanks, so the other test wins.
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u64 Blank = HalfFrame / 2; // PAL VBlank Period is off for roughly 22 HSyncs
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//I would have suspected this to be Frame - Blank, but that seems to completely freak it out
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//and the test results are completely wrong. It seems 100% the same as the PS2 test on this,
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//So let's roll with it :P
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u64 Render = HalfFrame - Blank; // so use the half-frame value for these...
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// Important! The hRender/hBlank timers should be 50/50 for best results.
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// (this appears to be what the real EE's timing crystal does anyway)
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u64 Scanline = Frame / scansPerFrame;
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u64 hBlank = Scanline / 2;
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u64 hRender = Scanline - hBlank;
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if (!IsAnalogVideoMode())
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{
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hBlank /= 2;
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hRender /= 2;
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}
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info->Framerate = framesPerSecond;
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info->Render = (u32)(Render / 10000);
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info->Blank = (u32)(Blank / 10000);
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info->hRender = (u32)(hRender / 10000);
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info->hBlank = (u32)(hBlank / 10000);
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info->hScanlinesPerFrame = scansPerFrame;
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// Apply rounding:
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if ((Render - info->Render) >= 5000) info->Render++;
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else if ((Blank - info->Blank) >= 5000) info->Blank++;
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if ((hRender - info->hRender) >= 5000) info->hRender++;
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else if ((hBlank - info->hBlank) >= 5000) info->hBlank++;
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// Calculate accumulative hSync rounding error per half-frame:
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if (IsAnalogVideoMode()) // gets off the chart in that mode
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{
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u32 hSyncCycles = ((info->hRender + info->hBlank) * scansPerFrame) / 2;
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u32 vSyncCycles = (info->Render + info->Blank);
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info->hSyncError = vSyncCycles - hSyncCycles;
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//Console.Warning("%d",info->hSyncError);
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}
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else info->hSyncError = 0;
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// Note: In NTSC modes there is some small rounding error in the vsync too,
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// however it would take thousands of frames for it to amount to anything and
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// is thus not worth the effort at this time.
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}
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static const char* ReportVideoMode()
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{
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switch (gsVideoMode)
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{
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case GS_VideoMode::PAL: return "PAL";
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case GS_VideoMode::NTSC: return "NTSC";
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case GS_VideoMode::VESA: return "VESA";
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case GS_VideoMode::BIOS: return "BIOS";
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case GS_VideoMode::HDTV_480P: return "HDTV 480p";
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case GS_VideoMode::HDTV_576P: return "HDTV 576p";
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case GS_VideoMode::HDTV_720P: return "HDTV 720p";
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case GS_VideoMode::HDTV_1080I: return "HDTV 1080i";
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case GS_VideoMode::HDTV_1080P: return "HDTV 1080p";
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default: return "Unknown";
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}
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}
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Fixed100 GetVerticalFrequency()
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{
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switch (gsVideoMode)
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{
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case GS_VideoMode::Uninitialized: // SYSCALL instruction hasn't executed yet, give some temporary values.
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return 60;
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case GS_VideoMode::PAL:
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return EmuConfig.GS.FrameratePAL;
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case GS_VideoMode::NTSC:
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return EmuConfig.GS.FramerateNTSC;
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case GS_VideoMode::HDTV_480P:
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return 59.94;
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case GS_VideoMode::HDTV_1080P:
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case GS_VideoMode::HDTV_1080I:
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case GS_VideoMode::HDTV_576P:
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case GS_VideoMode::HDTV_720P:
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case GS_VideoMode::VESA:
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case GS_VideoMode::BIOS:
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return 60;
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default:
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// Pass NTSC vertical frequency value when unknown video mode is detected.
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return FRAMERATE_NTSC * 2;
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}
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}
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u32 UpdateVSyncRate()
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{
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// Notice: (and I probably repeat this elsewhere, but it's worth repeating)
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// The PS2's vsync timer is an *independent* crystal that is fixed to either 59.94 (NTSC)
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// or 50.0 (PAL) Hz. It has *nothing* to do with real TV timings or the real vsync of
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// the GS's output circuit. It is the same regardless if the GS is outputting interlace
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// or progressive scan content.
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Fixed100 framerate = GetVerticalFrequency() / 2;
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u32 scanlines = 0;
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bool isCustom = false;
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//Set up scanlines and framerate based on video mode
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switch (gsVideoMode)
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{
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case GS_VideoMode::Uninitialized: // SYSCALL instruction hasn't executed yet, give some temporary values.
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scanlines = SCANLINES_TOTAL_NTSC;
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break;
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case GS_VideoMode::PAL:
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isCustom = (EmuConfig.GS.FrameratePAL != 50.0);
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scanlines = SCANLINES_TOTAL_PAL;
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if (!gsIsInterlaced) scanlines += 3;
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break;
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case GS_VideoMode::NTSC:
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isCustom = (EmuConfig.GS.FramerateNTSC != 59.94);
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scanlines = SCANLINES_TOTAL_NTSC;
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if (!gsIsInterlaced) scanlines += 1;
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break;
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case GS_VideoMode::HDTV_480P:
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case GS_VideoMode::HDTV_1080P:
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case GS_VideoMode::HDTV_1080I:
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case GS_VideoMode::HDTV_576P:
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case GS_VideoMode::HDTV_720P:
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case GS_VideoMode::VESA:
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case GS_VideoMode::BIOS:
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scanlines = SCANLINES_TOTAL_NTSC;
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break;
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case GS_VideoMode::Unknown:
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default:
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// Falls through to default when unidentified mode parameter of SetGsCrt is detected.
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// For Release builds, keep using the NTSC timing values when unknown video mode is detected.
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// Assert will be triggered for debug/dev builds.
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scanlines = SCANLINES_TOTAL_NTSC;
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Console.Error("PCSX2-Counters: Unknown video mode detected");
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pxAssertDev(false , "Unknown video mode detected via SetGsCrt");
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}
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bool ActiveVideoMode = gsVideoMode != GS_VideoMode::Uninitialized;
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if (vSyncInfo.Framerate != framerate || vSyncInfo.VideoMode != gsVideoMode)
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{
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vSyncInfo.VideoMode = gsVideoMode;
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vSyncInfoCalc( &vSyncInfo, framerate, scanlines );
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if(ActiveVideoMode)
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Console.WriteLn( Color_Green, "(UpdateVSyncRate) Mode Changed to %s.", ReportVideoMode());
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if( isCustom && ActiveVideoMode)
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Console.Indent().WriteLn( Color_StrongGreen, "... with user configured refresh rate: %.02f Hz", 2 * framerate.ToFloat() );
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hsyncCounter.CycleT = vSyncInfo.hRender; // Amount of cycles before the counter will be updated
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vsyncCounter.CycleT = vSyncInfo.Render; // Amount of cycles before the counter will be updated
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cpuRcntSet();
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}
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Fixed100 fpslimit = framerate *
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( pxAssert( EmuConfig.GS.LimitScalar > 0 ) ? EmuConfig.GS.LimitScalar : 1.0 );
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//s64 debugme = GetTickFrequency() / 3000;
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s64 ticks = (GetTickFrequency()*500) / (fpslimit * 1000).ToIntRounded();
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if( m_iTicks != ticks )
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{
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m_iTicks = ticks;
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gsOnModeChanged( vSyncInfo.Framerate, m_iTicks );
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if (ActiveVideoMode)
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Console.WriteLn( Color_Green, "(UpdateVSyncRate) FPS Limit Changed : %.02f fps", fpslimit.ToFloat()*2 );
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}
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m_iStart = GetCPUTicks();
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return (u32)m_iTicks;
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}
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void frameLimitReset()
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{
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m_iStart = GetCPUTicks();
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}
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// Framelimiter - Measures the delta time between calls and stalls until a
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// certain amount of time passes if such time hasn't passed yet.
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// See the GS FrameSkip function for details on why this is here and not in the GS.
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static __fi void frameLimit()
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{
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// 999 means the user would rather just have framelimiting turned off...
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if( !EmuConfig.GS.FrameLimitEnable ) return;
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u64 uExpectedEnd = m_iStart + m_iTicks;
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u64 iEnd = GetCPUTicks();
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s64 sDeltaTime = iEnd - uExpectedEnd;
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// If the framerate drops too low, reset the expected value. This avoids
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// excessive amounts of "fast forward" syndrome which would occur if we
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// tried to catch up too much.
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if( sDeltaTime > m_iTicks*8 )
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{
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m_iStart = iEnd - m_iTicks;
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return;
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}
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// use the expected frame completion time as our starting point.
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// improves smoothness by making the framelimiter more adaptive to the
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// imperfect TIMESLICE() wait, and allows it to speed up a wee bit after
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// slow frames to "catch up."
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m_iStart = uExpectedEnd;
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// Shortcut for cases where no waiting is needed (they're running slow already,
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// so don't bog 'em down with extra math...)
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if( sDeltaTime >= 0 ) return;
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// If we're way ahead then we can afford to sleep the thread a bit.
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// (note, on Windows sleep(1) thru sleep(2) tend to be the least accurate sleeps,
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// and longer sleeps tend to be pretty reliable, so that's why the convoluted if/
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// else below. The same generally isn't true for Linux, but no harm either way
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// really.)
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s32 msec = (int)((sDeltaTime*-1000) / (s64)GetTickFrequency());
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if( msec > 4 ) Threading::Sleep( msec );
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else if( msec > 2 ) Threading::Sleep( 1 );
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// Sleep is not picture-perfect accurate, but it's actually not necessary to
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// maintain a "perfect" lock to uExpectedEnd anyway. if we're a little ahead
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// starting this frame, it'll just sleep longer the next to make up for it. :)
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}
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static __fi void VSyncStart(u32 sCycle)
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{
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GetCoreThread().VsyncInThread();
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Cpu->CheckExecutionState();
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if(EmuConfig.Trace.Enabled && EmuConfig.Trace.EE.m_EnableAll)
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SysTrace.EE.Counters.Write( " ================ EE COUNTER VSYNC START (frame: %d) ================", g_FrameCount );
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// EE Profiling and Debug code.
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// FIXME: should probably be moved to VsyncInThread, and handled
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// by UI implementations. (ie, AppCoreThread in PCSX2-wx interface).
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vSyncDebugStuff( g_FrameCount );
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CpuVU0->Vsync();
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CpuVU1->Vsync();
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if (!CSRreg.VSINT)
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{
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CSRreg.VSINT = true;
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if (!GSIMR.VSMSK)
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gsIrq();
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}
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hwIntcIrq(INTC_VBLANK_S);
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psxVBlankStart();
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gsPostVsyncStart();
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if (gates) rcntStartGate(true, sCycle); // Counters Start Gate code
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// INTC - VB Blank Start Hack --
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// Hack fix! This corrects a freezeup in Granda 2 where it decides to spin
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// on the INTC_STAT register after the exception handler has already cleared
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// it. But be warned! Set the value to larger than 4 and it breaks Dark
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// Cloud and other games. -_-
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// How it works: Normally the INTC raises exceptions immediately at the end of the
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// current branch test. But in the case of Grandia 2, the game's code is spinning
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// on the INTC status, and the exception handler (for some reason?) clears the INTC
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// before returning *and* returns to a location other than EPC. So the game never
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// gets to the point where it sees the INTC Irq set true.
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// (I haven't investigated why Dark Cloud freezes on larger values)
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// (all testing done using the recompiler -- dunno how the ints respond yet)
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//cpuRegs.eCycle[30] = 2;
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// Should no longer be required (Refraction)
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}
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static __fi void VSyncEnd(u32 sCycle)
|
|
{
|
|
if(EmuConfig.Trace.Enabled && EmuConfig.Trace.EE.m_EnableAll)
|
|
SysTrace.EE.Counters.Write( " ================ EE COUNTER VSYNC END (frame: %d) ================", g_FrameCount );
|
|
|
|
g_FrameCount++;
|
|
|
|
|
|
|
|
hwIntcIrq(INTC_VBLANK_E); // HW Irq
|
|
psxVBlankEnd(); // psxCounters vBlank End
|
|
if (gates) rcntEndGate(true, sCycle); // Counters End Gate Code
|
|
|
|
// FolderMemoryCard needs information on how much time has passed since the last write
|
|
// Call it every 60 frames
|
|
if (!(g_FrameCount % 60))
|
|
sioNextFrame();
|
|
|
|
frameLimit(); // limit FPS
|
|
|
|
//Do this here, breaks Dynasty Warriors otherwise.
|
|
CSRreg.SwapField();
|
|
// This doesn't seem to be needed here. Games only seem to break with regard to the
|
|
// vsyncstart irq.
|
|
//cpuRegs.eCycle[30] = 2;
|
|
}
|
|
|
|
//#define VSYNC_DEBUG // Uncomment this to enable some vSync Timer debugging features.
|
|
#ifdef VSYNC_DEBUG
|
|
static u32 hsc=0;
|
|
static int vblankinc = 0;
|
|
#endif
|
|
|
|
__fi void rcntUpdate_hScanline()
|
|
{
|
|
if( !cpuTestCycle( hsyncCounter.sCycle, hsyncCounter.CycleT ) ) return;
|
|
|
|
//iopEventAction = 1;
|
|
if (hsyncCounter.Mode & MODE_HBLANK) { //HBLANK Start
|
|
rcntStartGate(false, hsyncCounter.sCycle);
|
|
psxCheckStartGate16(0);
|
|
|
|
// Setup the hRender's start and end cycle information:
|
|
hsyncCounter.sCycle += vSyncInfo.hBlank; // start (absolute cycle value)
|
|
hsyncCounter.CycleT = vSyncInfo.hRender; // endpoint (delta from start value)
|
|
hsyncCounter.Mode = MODE_HRENDER;
|
|
}
|
|
else { //HBLANK END / HRENDER Begin
|
|
if (!CSRreg.HSINT)
|
|
{
|
|
CSRreg.HSINT = true;
|
|
if (!GSIMR.HSMSK)
|
|
gsIrq();
|
|
}
|
|
if (gates) rcntEndGate(false, hsyncCounter.sCycle);
|
|
if (psxhblankgate) psxCheckEndGate16(0);
|
|
|
|
// set up the hblank's start and end cycle information:
|
|
hsyncCounter.sCycle += vSyncInfo.hRender; // start (absolute cycle value)
|
|
hsyncCounter.CycleT = vSyncInfo.hBlank; // endpoint (delta from start value)
|
|
hsyncCounter.Mode = MODE_HBLANK;
|
|
|
|
# ifdef VSYNC_DEBUG
|
|
hsc++;
|
|
# endif
|
|
}
|
|
}
|
|
|
|
__fi void rcntUpdate_vSync()
|
|
{
|
|
s32 diff = (cpuRegs.cycle - vsyncCounter.sCycle);
|
|
if( diff < vsyncCounter.CycleT ) return;
|
|
|
|
if (vsyncCounter.Mode == MODE_VSYNC)
|
|
{
|
|
VSyncEnd(vsyncCounter.sCycle);
|
|
|
|
vsyncCounter.sCycle += vSyncInfo.Blank;
|
|
vsyncCounter.CycleT = vSyncInfo.Render;
|
|
vsyncCounter.Mode = MODE_VRENDER;
|
|
}
|
|
else // VSYNC end / VRENDER begin
|
|
{
|
|
VSyncStart(vsyncCounter.sCycle);
|
|
|
|
|
|
vsyncCounter.sCycle += vSyncInfo.Render;
|
|
vsyncCounter.CycleT = vSyncInfo.Blank;
|
|
vsyncCounter.Mode = MODE_VSYNC;
|
|
|
|
// Accumulate hsync rounding errors:
|
|
hsyncCounter.sCycle += vSyncInfo.hSyncError;
|
|
|
|
# ifdef VSYNC_DEBUG
|
|
vblankinc++;
|
|
if( vblankinc > 1 )
|
|
{
|
|
if( hsc != vSyncInfo.hScanlinesPerFrame )
|
|
Console.WriteLn( " ** vSync > Abnormal Scanline Count: %d", hsc );
|
|
hsc = 0;
|
|
vblankinc = 0;
|
|
}
|
|
# endif
|
|
}
|
|
}
|
|
|
|
static __fi void _cpuTestTarget( int i )
|
|
{
|
|
if (counters[i].count < counters[i].target) return;
|
|
|
|
if(counters[i].mode.TargetInterrupt) {
|
|
|
|
EECNT_LOG("EE Counter[%d] TARGET reached - mode=%x, count=%x, target=%x", i, counters[i].mode, counters[i].count, counters[i].target);
|
|
counters[i].mode.TargetReached = 1;
|
|
hwIntcIrq(counters[i].interrupt);
|
|
|
|
// The PS2 only resets if the interrupt is enabled - Tested on PS2
|
|
if (counters[i].mode.ZeroReturn)
|
|
counters[i].count -= counters[i].target; // Reset on target
|
|
else
|
|
counters[i].target |= EECNT_FUTURE_TARGET;
|
|
}
|
|
else counters[i].target |= EECNT_FUTURE_TARGET;
|
|
}
|
|
|
|
static __fi void _cpuTestOverflow( int i )
|
|
{
|
|
if (counters[i].count <= 0xffff) return;
|
|
|
|
if (counters[i].mode.OverflowInterrupt) {
|
|
EECNT_LOG("EE Counter[%d] OVERFLOW - mode=%x, count=%x", i, counters[i].mode, counters[i].count);
|
|
counters[i].mode.OverflowReached = 1;
|
|
hwIntcIrq(counters[i].interrupt);
|
|
}
|
|
|
|
// wrap counter back around zero, and enable the future target:
|
|
counters[i].count -= 0x10000;
|
|
counters[i].target &= 0xffff;
|
|
}
|
|
|
|
|
|
// forceinline note: this method is called from two locations, but one
|
|
// of them is the interpreter, which doesn't count. ;) So might as
|
|
// well forceinline it!
|
|
__fi void rcntUpdate()
|
|
{
|
|
rcntUpdate_vSync();
|
|
|
|
// Update counters so that we can perform overflow and target tests.
|
|
|
|
for (int i=0; i<=3; i++)
|
|
{
|
|
// We want to count gated counters (except the hblank which exclude below, and are
|
|
// counted by the hblank timer instead)
|
|
|
|
//if ( gates & (1<<i) ) continue;
|
|
|
|
if (!counters[i].mode.IsCounting ) continue;
|
|
|
|
if(counters[i].mode.ClockSource != 0x3) // don't count hblank sources
|
|
{
|
|
s32 change = cpuRegs.cycle - counters[i].sCycleT;
|
|
if( change < 0 ) change = 0; // sanity check!
|
|
|
|
counters[i].count += change / counters[i].rate;
|
|
change -= (change / counters[i].rate) * counters[i].rate;
|
|
counters[i].sCycleT = cpuRegs.cycle - change;
|
|
|
|
// Check Counter Targets and Overflows:
|
|
_cpuTestTarget( i );
|
|
_cpuTestOverflow( i );
|
|
}
|
|
else counters[i].sCycleT = cpuRegs.cycle;
|
|
}
|
|
|
|
cpuRcntSet();
|
|
}
|
|
|
|
static __fi void _rcntSetGate( int index )
|
|
{
|
|
if (counters[index].mode.EnableGate)
|
|
{
|
|
// If the Gate Source is hblank and the clock selection is also hblank
|
|
// then the gate is disabled and the counter acts as a normal hblank source.
|
|
|
|
if( !(counters[index].mode.GateSource == 0 && counters[index].mode.ClockSource == 3) )
|
|
{
|
|
EECNT_LOG( "EE Counter[%d] Using Gate! Source=%s, Mode=%d.",
|
|
index, counters[index].mode.GateSource ? "vblank" : "hblank", counters[index].mode.GateMode );
|
|
|
|
gates |= (1<<index);
|
|
counters[index].mode.IsCounting = 0;
|
|
rcntReset(index);
|
|
return;
|
|
}
|
|
else
|
|
EECNT_LOG( "EE Counter[%d] GATE DISABLED because of hblank source.", index );
|
|
}
|
|
|
|
gates &= ~(1<<index);
|
|
}
|
|
|
|
// mode - 0 means hblank source, 8 means vblank source.
|
|
static __fi void rcntStartGate(bool isVblank, u32 sCycle)
|
|
{
|
|
int i;
|
|
|
|
for (i=0; i <=3; i++)
|
|
{
|
|
//if ((mode == 0) && ((counters[i].mode & 0x83) == 0x83))
|
|
if (!isVblank && counters[i].mode.IsCounting && (counters[i].mode.ClockSource == 3) )
|
|
{
|
|
// Update counters using the hblank as the clock. This keeps the hblank source
|
|
// nicely in sync with the counters and serves as an optimization also, since these
|
|
// counter won't recieve special rcntUpdate scheduling.
|
|
|
|
// Note: Target and overflow tests must be done here since they won't be done
|
|
// currectly by rcntUpdate (since it's not being scheduled for these counters)
|
|
|
|
counters[i].count += HBLANK_COUNTER_SPEED;
|
|
_cpuTestTarget( i );
|
|
_cpuTestOverflow( i );
|
|
}
|
|
|
|
if (!(gates & (1<<i))) continue;
|
|
if ((!!counters[i].mode.GateSource) != isVblank) continue;
|
|
|
|
switch (counters[i].mode.GateMode) {
|
|
case 0x0: //Count When Signal is low (off)
|
|
|
|
// Just set the start cycle (sCycleT) -- counting will be done as needed
|
|
// for events (overflows, targets, mode changes, and the gate off below)
|
|
|
|
counters[i].count = rcntRcount(i);
|
|
counters[i].mode.IsCounting = 0;
|
|
counters[i].sCycleT = sCycle;
|
|
EECNT_LOG("EE Counter[%d] %s StartGate Type0, count = %x", i,
|
|
isVblank ? "vblank" : "hblank", counters[i].count );
|
|
break;
|
|
|
|
case 0x2: // reset and start counting on vsync end
|
|
// this is the vsync start so do nothing.
|
|
break;
|
|
|
|
case 0x1: //Reset and start counting on Vsync start
|
|
case 0x3: //Reset and start counting on Vsync start and end
|
|
counters[i].mode.IsCounting = 1;
|
|
counters[i].count = 0;
|
|
counters[i].target &= 0xffff;
|
|
counters[i].sCycleT = sCycle;
|
|
EECNT_LOG("EE Counter[%d] %s StartGate Type%d, count = %x", i,
|
|
isVblank ? "vblank" : "hblank", counters[i].mode.GateMode, counters[i].count );
|
|
break;
|
|
}
|
|
}
|
|
|
|
// No need to update actual counts here. Counts are calculated as needed by reads to
|
|
// rcntRcount(). And so long as sCycleT is set properly, any targets or overflows
|
|
// will be scheduled and handled.
|
|
|
|
// Note: No need to set counters here. They'll get set when control returns to
|
|
// rcntUpdate, since we're being called from there anyway.
|
|
}
|
|
|
|
// mode - 0 means hblank signal, 8 means vblank signal.
|
|
static __fi void rcntEndGate(bool isVblank , u32 sCycle)
|
|
{
|
|
int i;
|
|
|
|
for(i=0; i <=3; i++) { //Gates for counters
|
|
if (!(gates & (1<<i))) continue;
|
|
if ((!!counters[i].mode.GateSource) != isVblank) continue;
|
|
|
|
switch (counters[i].mode.GateMode) {
|
|
case 0x0: //Count When Signal is low (off)
|
|
|
|
// Set the count here. Since the timer is being turned off it's
|
|
// important to record its count at this point (it won't be counted by
|
|
// calls to rcntUpdate).
|
|
counters[i].mode.IsCounting = 1;
|
|
counters[i].sCycleT = cpuRegs.cycle;
|
|
|
|
EECNT_LOG("EE Counter[%d] %s EndGate Type0, count = %x", i,
|
|
isVblank ? "vblank" : "hblank", counters[i].count );
|
|
break;
|
|
|
|
case 0x1: // Reset and start counting on Vsync start
|
|
// this is the vsync end so do nothing
|
|
break;
|
|
|
|
case 0x2: //Reset and start counting on Vsync end
|
|
case 0x3: //Reset and start counting on Vsync start and end
|
|
counters[i].mode.IsCounting = 1;
|
|
counters[i].count = 0;
|
|
counters[i].target &= 0xffff;
|
|
counters[i].sCycleT = sCycle;
|
|
EECNT_LOG("EE Counter[%d] %s EndGate Type%d, count = %x", i,
|
|
isVblank ? "vblank" : "hblank", counters[i].mode.GateMode, counters[i].count );
|
|
break;
|
|
}
|
|
}
|
|
// Note: No need to set counters here. They'll get set when control returns to
|
|
// rcntUpdate, since we're being called from there anyway.
|
|
}
|
|
|
|
static __fi u32 rcntCycle(int index)
|
|
{
|
|
if (counters[index].mode.IsCounting && (counters[index].mode.ClockSource != 0x3))
|
|
return counters[index].count + ((cpuRegs.cycle - counters[index].sCycleT) / counters[index].rate);
|
|
else
|
|
return counters[index].count;
|
|
}
|
|
|
|
static __fi void rcntWmode(int index, u32 value)
|
|
{
|
|
if(counters[index].mode.IsCounting) {
|
|
if(counters[index].mode.ClockSource != 0x3) {
|
|
|
|
u32 change = cpuRegs.cycle - counters[index].sCycleT;
|
|
if( change > 0 )
|
|
{
|
|
counters[index].count += change / counters[index].rate;
|
|
change -= (change / counters[index].rate) * counters[index].rate;
|
|
counters[index].sCycleT = cpuRegs.cycle - change;
|
|
}
|
|
}
|
|
}
|
|
else counters[index].sCycleT = cpuRegs.cycle;
|
|
|
|
// Clear OverflowReached and TargetReached flags (0xc00 mask), but *only* if they are set to 1 in the
|
|
// given value. (yes, the bits are cleared when written with '1's).
|
|
|
|
counters[index].modeval &= ~(value & 0xc00);
|
|
counters[index].modeval = (counters[index].modeval & 0xc00) | (value & 0x3ff);
|
|
EECNT_LOG("EE Counter[%d] writeMode = %x passed value=%x", index, counters[index].modeval, value );
|
|
|
|
switch (counters[index].mode.ClockSource) { //Clock rate divisers *2, they use BUSCLK speed not PS2CLK
|
|
case 0: counters[index].rate = 2; break;
|
|
case 1: counters[index].rate = 32; break;
|
|
case 2: counters[index].rate = 512; break;
|
|
case 3: counters[index].rate = vSyncInfo.hBlank+vSyncInfo.hRender; break;
|
|
}
|
|
|
|
_rcntSetGate( index );
|
|
_rcntSet( index );
|
|
}
|
|
|
|
static __fi void rcntWcount(int index, u32 value)
|
|
{
|
|
EECNT_LOG("EE Counter[%d] writeCount = %x, oldcount=%x, target=%x", index, value, counters[index].count, counters[index].target );
|
|
|
|
counters[index].count = value & 0xffff;
|
|
|
|
// reset the target, and make sure we don't get a premature target.
|
|
counters[index].target &= 0xffff;
|
|
if( counters[index].count > counters[index].target )
|
|
counters[index].target |= EECNT_FUTURE_TARGET;
|
|
|
|
// re-calculate the start cycle of the counter based on elapsed time since the last counter update:
|
|
if(counters[index].mode.IsCounting) {
|
|
if(counters[index].mode.ClockSource != 0x3) {
|
|
s32 change = cpuRegs.cycle - counters[index].sCycleT;
|
|
if( change > 0 ) {
|
|
change -= (change / counters[index].rate) * counters[index].rate;
|
|
counters[index].sCycleT = cpuRegs.cycle - change;
|
|
}
|
|
}
|
|
}
|
|
else counters[index].sCycleT = cpuRegs.cycle;
|
|
|
|
_rcntSet( index );
|
|
}
|
|
|
|
static __fi void rcntWtarget(int index, u32 value)
|
|
{
|
|
EECNT_LOG("EE Counter[%d] writeTarget = %x", index, value);
|
|
|
|
counters[index].target = value & 0xffff;
|
|
|
|
// guard against premature (instant) targeting.
|
|
// If the target is behind the current count, set it up so that the counter must
|
|
// overflow first before the target fires:
|
|
|
|
if(counters[index].mode.IsCounting) {
|
|
if(counters[index].mode.ClockSource != 0x3) {
|
|
|
|
u32 change = cpuRegs.cycle - counters[index].sCycleT;
|
|
if( change > 0 )
|
|
{
|
|
counters[index].count += change / counters[index].rate;
|
|
change -= (change / counters[index].rate) * counters[index].rate;
|
|
counters[index].sCycleT = cpuRegs.cycle - change;
|
|
}
|
|
}
|
|
}
|
|
|
|
if( counters[index].target <= rcntCycle(index) )
|
|
counters[index].target |= EECNT_FUTURE_TARGET;
|
|
|
|
_rcntSet( index );
|
|
}
|
|
|
|
static __fi void rcntWhold(int index, u32 value)
|
|
{
|
|
EECNT_LOG("EE Counter[%d] Hold Write = %x", index, value);
|
|
counters[index].hold = value;
|
|
}
|
|
|
|
__fi u32 rcntRcount(int index)
|
|
{
|
|
u32 ret;
|
|
|
|
// only count if the counter is turned on (0x80) and is not an hsync gate (!0x03)
|
|
if (counters[index].mode.IsCounting && (counters[index].mode.ClockSource != 0x3))
|
|
ret = counters[index].count + ((cpuRegs.cycle - counters[index].sCycleT) / counters[index].rate);
|
|
else
|
|
ret = counters[index].count;
|
|
|
|
// Spams the Console.
|
|
EECNT_LOG("EE Counter[%d] readCount32 = %x", index, ret);
|
|
return ret;
|
|
}
|
|
|
|
template< uint page >
|
|
__fi u16 rcntRead32( u32 mem )
|
|
{
|
|
// Important DevNote:
|
|
// Yes this uses a u16 return value on purpose! The upper bits 16 of the counter registers
|
|
// are all fixed to 0, so we always truncate everything in these two pages using a u16
|
|
// return value! --air
|
|
|
|
iswitch( mem ) {
|
|
icase(RCNT0_COUNT) return (u16)rcntRcount(0);
|
|
icase(RCNT0_MODE) return (u16)counters[0].modeval;
|
|
icase(RCNT0_TARGET) return (u16)counters[0].target;
|
|
icase(RCNT0_HOLD) return (u16)counters[0].hold;
|
|
|
|
icase(RCNT1_COUNT) return (u16)rcntRcount(1);
|
|
icase(RCNT1_MODE) return (u16)counters[1].modeval;
|
|
icase(RCNT1_TARGET) return (u16)counters[1].target;
|
|
icase(RCNT1_HOLD) return (u16)counters[1].hold;
|
|
|
|
icase(RCNT2_COUNT) return (u16)rcntRcount(2);
|
|
icase(RCNT2_MODE) return (u16)counters[2].modeval;
|
|
icase(RCNT2_TARGET) return (u16)counters[2].target;
|
|
|
|
icase(RCNT3_COUNT) return (u16)rcntRcount(3);
|
|
icase(RCNT3_MODE) return (u16)counters[3].modeval;
|
|
icase(RCNT3_TARGET) return (u16)counters[3].target;
|
|
}
|
|
|
|
return psHu16(mem);
|
|
}
|
|
|
|
template< uint page >
|
|
__fi bool rcntWrite32( u32 mem, mem32_t& value )
|
|
{
|
|
pxAssume( mem >= RCNT0_COUNT && mem < 0x10002000 );
|
|
|
|
// [TODO] : counters should actually just use the EE's hw register space for storing
|
|
// count, mode, target, and hold. This will allow for a simplified handler for register
|
|
// reads.
|
|
|
|
iswitch( mem ) {
|
|
icase(RCNT0_COUNT) return rcntWcount(0, value), false;
|
|
icase(RCNT0_MODE) return rcntWmode(0, value), false;
|
|
icase(RCNT0_TARGET) return rcntWtarget(0, value), false;
|
|
icase(RCNT0_HOLD) return rcntWhold(0, value), false;
|
|
|
|
icase(RCNT1_COUNT) return rcntWcount(1, value), false;
|
|
icase(RCNT1_MODE) return rcntWmode(1, value), false;
|
|
icase(RCNT1_TARGET) return rcntWtarget(1, value), false;
|
|
icase(RCNT1_HOLD) return rcntWhold(1, value), false;
|
|
|
|
icase(RCNT2_COUNT) return rcntWcount(2, value), false;
|
|
icase(RCNT2_MODE) return rcntWmode(2, value), false;
|
|
icase(RCNT2_TARGET) return rcntWtarget(2, value), false;
|
|
|
|
icase(RCNT3_COUNT) return rcntWcount(3, value), false;
|
|
icase(RCNT3_MODE) return rcntWmode(3, value), false;
|
|
icase(RCNT3_TARGET) return rcntWtarget(3, value), false;
|
|
}
|
|
|
|
// unhandled .. do memory writeback.
|
|
return true;
|
|
}
|
|
|
|
template u16 rcntRead32<0x00>( u32 mem );
|
|
template u16 rcntRead32<0x01>( u32 mem );
|
|
|
|
template bool rcntWrite32<0x00>( u32 mem, mem32_t& value );
|
|
template bool rcntWrite32<0x01>( u32 mem, mem32_t& value );
|
|
|
|
void SaveStateBase::rcntFreeze()
|
|
{
|
|
Freeze( counters );
|
|
Freeze( hsyncCounter );
|
|
Freeze( vsyncCounter );
|
|
Freeze( nextCounter );
|
|
Freeze( nextsCounter );
|
|
|
|
if( IsLoading() )
|
|
{
|
|
// make sure the gate flags are set based on the counter modes...
|
|
for( int i=0; i<4; i++ )
|
|
_rcntSetGate( i );
|
|
|
|
iopEventAction = 1; // probably not needed but won't hurt anything either.
|
|
}
|
|
}
|